1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <ethdev_driver.h>
14 #include <rte_bus_pci.h>
16 #include <rte_common.h>
17 #include <rte_interrupts.h>
18 #include <rte_malloc.h>
19 #include <rte_string_fns.h>
20 #include <rte_rwlock.h>
21 #include <rte_cycles.h>
23 #include <mlx5_malloc.h>
25 #include "mlx5_rxtx.h"
28 #include "mlx5_autoconf.h"
31 * Get the interface index from device name.
34 * Pointer to Ethernet device.
37 * Nonzero interface index on success, zero otherwise and rte_errno is set.
40 mlx5_ifindex(const struct rte_eth_dev *dev)
42 struct mlx5_priv *priv = dev->data->dev_private;
46 MLX5_ASSERT(priv->if_index);
47 if (priv->master && priv->sh->bond.ifindex > 0)
48 ifindex = priv->sh->bond.ifindex;
50 ifindex = priv->if_index;
57 * DPDK callback for Ethernet device configuration.
60 * Pointer to Ethernet device structure.
63 * 0 on success, a negative errno value otherwise and rte_errno is set.
66 mlx5_dev_configure(struct rte_eth_dev *dev)
68 struct mlx5_priv *priv = dev->data->dev_private;
69 unsigned int rxqs_n = dev->data->nb_rx_queues;
70 unsigned int txqs_n = dev->data->nb_tx_queues;
71 const uint8_t use_app_rss_key =
72 !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
75 if (use_app_rss_key &&
76 (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len !=
77 MLX5_RSS_HASH_KEY_LEN)) {
78 DRV_LOG(ERR, "port %u RSS key len must be %s Bytes long",
79 dev->data->port_id, RTE_STR(MLX5_RSS_HASH_KEY_LEN));
83 priv->rss_conf.rss_key =
84 mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE,
85 MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY);
86 if (!priv->rss_conf.rss_key) {
87 DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)",
88 dev->data->port_id, rxqs_n);
93 if ((dev->data->dev_conf.txmode.offloads &
94 RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) &&
95 rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) {
96 DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag",
100 memcpy(priv->rss_conf.rss_key,
102 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key :
103 rss_hash_default_key,
104 MLX5_RSS_HASH_KEY_LEN);
105 priv->rss_conf.rss_key_len = MLX5_RSS_HASH_KEY_LEN;
106 priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
107 priv->rxq_privs = mlx5_realloc(priv->rxq_privs,
108 MLX5_MEM_RTE | MLX5_MEM_ZERO,
109 sizeof(void *) * rxqs_n, 0,
111 if (priv->rxq_privs == NULL) {
112 DRV_LOG(ERR, "port %u cannot allocate rxq private data",
117 priv->rxqs = (void *)dev->data->rx_queues;
118 priv->txqs = (void *)dev->data->tx_queues;
119 if (txqs_n != priv->txqs_n) {
120 DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u",
121 dev->data->port_id, priv->txqs_n, txqs_n);
122 priv->txqs_n = txqs_n;
124 if (rxqs_n > priv->config.ind_table_max_size) {
125 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)",
126 dev->data->port_id, rxqs_n);
130 if (rxqs_n != priv->rxqs_n) {
131 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
132 dev->data->port_id, priv->rxqs_n, rxqs_n);
133 priv->rxqs_n = rxqs_n;
135 priv->skip_default_rss_reta = 0;
136 ret = mlx5_proc_priv_init(dev);
143 * Configure default RSS reta.
146 * Pointer to Ethernet device structure.
149 * 0 on success, a negative errno value otherwise and rte_errno is set.
152 mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev)
154 struct mlx5_priv *priv = dev->data->dev_private;
155 unsigned int rxqs_n = dev->data->nb_rx_queues;
158 unsigned int reta_idx_n;
160 unsigned int *rss_queue_arr = NULL;
161 unsigned int rss_queue_n = 0;
163 if (priv->skip_default_rss_reta)
165 rss_queue_arr = mlx5_malloc(0, rxqs_n * sizeof(unsigned int), 0,
167 if (!rss_queue_arr) {
168 DRV_LOG(ERR, "port %u cannot allocate RSS queue list (%u)",
169 dev->data->port_id, rxqs_n);
173 for (i = 0, j = 0; i < rxqs_n; i++) {
174 struct mlx5_rxq_data *rxq_data;
175 struct mlx5_rxq_ctrl *rxq_ctrl;
177 rxq_data = (*priv->rxqs)[i];
178 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
179 if (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
180 rss_queue_arr[j++] = i;
183 if (rss_queue_n > priv->config.ind_table_max_size) {
184 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)",
185 dev->data->port_id, rss_queue_n);
187 mlx5_free(rss_queue_arr);
190 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
191 dev->data->port_id, priv->rxqs_n, rxqs_n);
192 priv->rxqs_n = rxqs_n;
194 * If the requested number of RX queues is not a power of two,
195 * use the maximum indirection table size for better balancing.
196 * The result is always rounded to the next power of two.
198 reta_idx_n = (1 << log2above((rss_queue_n & (rss_queue_n - 1)) ?
199 priv->config.ind_table_max_size :
201 ret = mlx5_rss_reta_index_resize(dev, reta_idx_n);
203 mlx5_free(rss_queue_arr);
207 * When the number of RX queues is not a power of two,
208 * the remaining table entries are padded with reused WQs
209 * and hashes are not spread uniformly.
211 for (i = 0, j = 0; (i != reta_idx_n); ++i) {
212 (*priv->reta_idx)[i] = rss_queue_arr[j];
213 if (++j == rss_queue_n)
216 mlx5_free(rss_queue_arr);
221 * Sets default tuning parameters.
224 * Pointer to Ethernet device.
226 * Info structure output buffer.
229 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
231 struct mlx5_priv *priv = dev->data->dev_private;
233 /* Minimum CPU utilization. */
234 info->default_rxportconf.ring_size = 256;
235 info->default_txportconf.ring_size = 256;
236 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST;
237 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST;
238 if ((priv->link_speed_capa & RTE_ETH_LINK_SPEED_200G) |
239 (priv->link_speed_capa & RTE_ETH_LINK_SPEED_100G)) {
240 info->default_rxportconf.nb_queues = 16;
241 info->default_txportconf.nb_queues = 16;
242 if (dev->data->nb_rx_queues > 2 ||
243 dev->data->nb_tx_queues > 2) {
244 /* Max Throughput. */
245 info->default_rxportconf.ring_size = 2048;
246 info->default_txportconf.ring_size = 2048;
249 info->default_rxportconf.nb_queues = 8;
250 info->default_txportconf.nb_queues = 8;
251 if (dev->data->nb_rx_queues > 2 ||
252 dev->data->nb_tx_queues > 2) {
253 /* Max Throughput. */
254 info->default_rxportconf.ring_size = 4096;
255 info->default_txportconf.ring_size = 4096;
261 * Sets tx mbuf limiting parameters.
264 * Pointer to Ethernet device.
266 * Info structure output buffer.
269 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
271 struct mlx5_priv *priv = dev->data->dev_private;
272 struct mlx5_dev_config *config = &priv->config;
276 inlen = (config->txq_inline_max == MLX5_ARG_UNSET) ?
277 MLX5_SEND_DEF_INLINE_LEN :
278 (unsigned int)config->txq_inline_max;
279 MLX5_ASSERT(config->txq_inline_min >= 0);
280 inlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min);
281 inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX +
282 MLX5_ESEG_MIN_INLINE_SIZE -
285 MLX5_WQE_DSEG_SIZE * 2);
286 nb_max = (MLX5_WQE_SIZE_MAX +
287 MLX5_ESEG_MIN_INLINE_SIZE -
291 inlen) / MLX5_WSEG_SIZE;
292 info->tx_desc_lim.nb_seg_max = nb_max;
293 info->tx_desc_lim.nb_mtu_seg_max = nb_max;
297 * DPDK callback to get information about the device.
300 * Pointer to Ethernet device structure.
302 * Info structure output buffer.
305 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
307 struct mlx5_priv *priv = dev->data->dev_private;
308 struct mlx5_dev_config *config = &priv->config;
311 /* FIXME: we should ask the device for these values. */
312 info->min_rx_bufsize = 32;
313 info->max_rx_pktlen = 65536;
314 info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE;
316 * Since we need one CQ per QP, the limit is the minimum number
317 * between the two values.
319 max = RTE_MIN(priv->sh->device_attr.max_cq,
320 priv->sh->device_attr.max_qp);
321 /* max_rx_queues is uint16_t. */
322 max = RTE_MIN(max, (unsigned int)UINT16_MAX);
323 info->max_rx_queues = max;
324 info->max_tx_queues = max;
325 info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES;
326 info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev);
327 info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG;
328 info->rx_seg_capa.multi_pools = !config->mprq.enabled;
329 info->rx_seg_capa.offset_allowed = !config->mprq.enabled;
330 info->rx_seg_capa.offset_align_log2 = 0;
331 info->rx_offload_capa = (mlx5_get_rx_port_offloads() |
332 info->rx_queue_offload_capa);
333 info->tx_offload_capa = mlx5_get_tx_port_offloads(dev);
334 info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP;
335 info->if_index = mlx5_ifindex(dev);
336 info->reta_size = priv->reta_idx_n ?
337 priv->reta_idx_n : config->ind_table_max_size;
338 info->hash_key_size = MLX5_RSS_HASH_KEY_LEN;
339 info->speed_capa = priv->link_speed_capa;
340 info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK;
341 mlx5_set_default_params(dev, info);
342 mlx5_set_txlimit_params(dev, info);
343 info->switch_info.name = dev->data->name;
344 info->switch_info.domain_id = priv->domain_id;
345 info->switch_info.port_id = priv->representor_id;
346 if (priv->representor) {
349 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
350 struct mlx5_priv *opriv =
351 rte_eth_devices[port_id].data->dev_private;
354 opriv->representor ||
355 opriv->sh != priv->sh ||
356 opriv->domain_id != priv->domain_id)
359 * Override switch name with that of the master
362 info->switch_info.name = opriv->dev_data->name;
370 * Calculate representor ID from port switch info.
372 * Uint16 representor ID bits definition:
380 * Use this type if port is HPF.
383 * Encoded representor ID.
386 mlx5_representor_id_encode(const struct mlx5_switch_info *info,
387 enum rte_eth_representor_type hpf_type)
389 enum rte_eth_representor_type type = RTE_ETH_REPRESENTOR_VF;
390 uint16_t repr = info->port_name;
392 if (info->representor == 0)
394 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF)
395 type = RTE_ETH_REPRESENTOR_SF;
396 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFHPF) {
400 return MLX5_REPRESENTOR_ID(info->pf_num, type, repr);
404 * DPDK callback to get information about representor.
406 * Representor ID bits definition:
412 * Pointer to Ethernet device structure.
414 * Nullable info structure output buffer.
417 * negative on error, or the number of representor ranges.
420 mlx5_representor_info_get(struct rte_eth_dev *dev,
421 struct rte_eth_representor_info *info)
423 struct mlx5_priv *priv = dev->data->dev_private;
424 int n_type = 4; /* Representor types, VF, HPF@VF, SF and HPF@SF. */
425 int n_pf = 2; /* Number of PFs. */
432 n_entries = n_type * n_pf;
433 if ((uint32_t)n_entries > info->nb_ranges_alloc)
434 n_entries = info->nb_ranges_alloc;
436 info->controller = 0;
437 info->pf = priv->pf_bond >= 0 ? priv->pf_bond : 0;
438 for (pf = 0; pf < n_pf; ++pf) {
440 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF;
441 info->ranges[i].controller = 0;
442 info->ranges[i].pf = pf;
443 info->ranges[i].vf = 0;
444 info->ranges[i].id_base =
445 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0);
446 info->ranges[i].id_end =
447 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
448 snprintf(info->ranges[i].name,
449 sizeof(info->ranges[i].name), "pf%dvf", pf);
453 /* HPF range of VF type. */
454 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF;
455 info->ranges[i].controller = 0;
456 info->ranges[i].pf = pf;
457 info->ranges[i].vf = UINT16_MAX;
458 info->ranges[i].id_base =
459 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
460 info->ranges[i].id_end =
461 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
462 snprintf(info->ranges[i].name,
463 sizeof(info->ranges[i].name), "pf%dvf", pf);
468 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF;
469 info->ranges[i].controller = 0;
470 info->ranges[i].pf = pf;
471 info->ranges[i].vf = 0;
472 info->ranges[i].id_base =
473 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0);
474 info->ranges[i].id_end =
475 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
476 snprintf(info->ranges[i].name,
477 sizeof(info->ranges[i].name), "pf%dsf", pf);
481 /* HPF range of SF type. */
482 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF;
483 info->ranges[i].controller = 0;
484 info->ranges[i].pf = pf;
485 info->ranges[i].vf = UINT16_MAX;
486 info->ranges[i].id_base =
487 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
488 info->ranges[i].id_end =
489 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
490 snprintf(info->ranges[i].name,
491 sizeof(info->ranges[i].name), "pf%dsf", pf);
498 return n_type * n_pf;
502 * Get firmware version of a device.
505 * Ethernet device port.
507 * String output allocated by caller.
509 * Size of the output string, including terminating null byte.
512 * 0 on success, or the size of the non truncated string if too big.
515 mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
517 struct mlx5_priv *priv = dev->data->dev_private;
518 struct mlx5_dev_attr *attr = &priv->sh->device_attr;
519 size_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1;
524 strlcpy(fw_ver, attr->fw_ver, fw_size);
529 * Get supported packet types.
532 * Pointer to Ethernet device structure.
535 * A pointer to the supported Packet types array.
538 mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev)
540 static const uint32_t ptypes[] = {
541 /* refers to rxq_cq_to_pkt_type() */
543 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
544 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
545 RTE_PTYPE_L4_NONFRAG,
549 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
550 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
551 RTE_PTYPE_INNER_L4_NONFRAG,
552 RTE_PTYPE_INNER_L4_FRAG,
553 RTE_PTYPE_INNER_L4_TCP,
554 RTE_PTYPE_INNER_L4_UDP,
558 if (dev->rx_pkt_burst == mlx5_rx_burst ||
559 dev->rx_pkt_burst == mlx5_rx_burst_mprq ||
560 dev->rx_pkt_burst == mlx5_rx_burst_vec ||
561 dev->rx_pkt_burst == mlx5_rx_burst_mprq_vec)
567 * DPDK callback to change the MTU.
570 * Pointer to Ethernet device structure.
575 * 0 on success, a negative errno value otherwise and rte_errno is set.
578 mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
580 struct mlx5_priv *priv = dev->data->dev_private;
581 uint16_t kern_mtu = 0;
584 ret = mlx5_get_mtu(dev, &kern_mtu);
587 /* Set kernel interface MTU first. */
588 ret = mlx5_set_mtu(dev, mtu);
591 ret = mlx5_get_mtu(dev, &kern_mtu);
594 if (kern_mtu == mtu) {
596 DRV_LOG(DEBUG, "port %u adapter MTU set to %u",
597 dev->data->port_id, mtu);
605 * Configure the RX function to use.
608 * Pointer to private data structure.
611 * Pointer to selected Rx burst function.
614 mlx5_select_rx_function(struct rte_eth_dev *dev)
616 eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst;
618 MLX5_ASSERT(dev != NULL);
619 if (mlx5_check_vec_rx_support(dev) > 0) {
620 if (mlx5_mprq_enabled(dev)) {
621 rx_pkt_burst = mlx5_rx_burst_mprq_vec;
622 DRV_LOG(DEBUG, "port %u selected vectorized"
623 " MPRQ Rx function", dev->data->port_id);
625 rx_pkt_burst = mlx5_rx_burst_vec;
626 DRV_LOG(DEBUG, "port %u selected vectorized"
627 " SPRQ Rx function", dev->data->port_id);
629 } else if (mlx5_mprq_enabled(dev)) {
630 rx_pkt_burst = mlx5_rx_burst_mprq;
631 DRV_LOG(DEBUG, "port %u selected MPRQ Rx function",
634 DRV_LOG(DEBUG, "port %u selected SPRQ Rx function",
641 * Get the E-Switch parameters by port id.
646 * Device port id is valid, skip check. This flag is useful
647 * when trials are performed from probing and device is not
648 * flagged as valid yet (in attaching process).
649 * @param[out] es_domain_id
650 * E-Switch domain id.
651 * @param[out] es_port_id
652 * The port id of the port in the E-Switch.
655 * pointer to device private data structure containing data needed
656 * on success, NULL otherwise and rte_errno is set.
659 mlx5_port_to_eswitch_info(uint16_t port, bool valid)
661 struct rte_eth_dev *dev;
662 struct mlx5_priv *priv;
664 if (port >= RTE_MAX_ETHPORTS) {
668 if (!valid && !rte_eth_dev_is_valid_port(port)) {
672 dev = &rte_eth_devices[port];
673 priv = dev->data->dev_private;
674 if (!(priv->representor || priv->master)) {
682 * Get the E-Switch parameters by device instance.
686 * @param[out] es_domain_id
687 * E-Switch domain id.
688 * @param[out] es_port_id
689 * The port id of the port in the E-Switch.
692 * pointer to device private data structure containing data needed
693 * on success, NULL otherwise and rte_errno is set.
696 mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev)
698 struct mlx5_priv *priv;
700 priv = dev->data->dev_private;
701 if (!(priv->representor || priv->master)) {
709 * DPDK callback to retrieve hairpin capabilities.
712 * Pointer to Ethernet device structure.
714 * Storage for hairpin capability data.
717 * 0 on success, a negative errno value otherwise and rte_errno is set.
720 mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)
722 struct mlx5_priv *priv = dev->data->dev_private;
723 struct mlx5_dev_config *config = &priv->config;
725 if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) {
729 cap->max_nb_queues = UINT16_MAX;
730 cap->max_rx_2_tx = 1;
731 cap->max_tx_2_rx = 1;
732 cap->max_nb_desc = 8192;