drivers/net/mlx5/mlx5_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <ethdev_driver.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_mbuf.h>
  16 #include <rte_common.h>
  17 #include <rte_interrupts.h>
  18 #include <rte_malloc.h>
  19 #include <rte_string_fns.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_cycles.h>
  22
  23 #include <mlx5_malloc.h>
  24
  25 #include "mlx5_rxtx.h"
  26 #include "mlx5_rx.h"
  27 #include "mlx5_tx.h"
  28 #include "mlx5_autoconf.h"
  29
  30 /**
  31  * Get the interface index from device name.
  32  *
  33  * @param[in] dev
  34  *   Pointer to Ethernet device.
  35  *
  36  * @return
  37  *   Nonzero interface index on success, zero otherwise and rte_errno is set.
  38  */
  39 unsigned int
  40 mlx5_ifindex(const struct rte_eth_dev *dev)
  41 {
  42         struct mlx5_priv *priv = dev->data->dev_private;
  43         unsigned int ifindex;
  44
  45         MLX5_ASSERT(priv);
  46         MLX5_ASSERT(priv->if_index);
  47         if (priv->master && priv->sh->bond.ifindex > 0)
  48                 ifindex = priv->sh->bond.ifindex;
  49         else
  50                 ifindex = priv->if_index;
  51         if (!ifindex)
  52                 rte_errno = ENXIO;
  53         return ifindex;
  54 }
  55
  56 /**
  57  * DPDK callback for Ethernet device configuration.
  58  *
  59  * @param dev
  60  *   Pointer to Ethernet device structure.
  61  *
  62  * @return
  63  *   0 on success, a negative errno value otherwise and rte_errno is set.
  64  */
  65 int
  66 mlx5_dev_configure(struct rte_eth_dev *dev)
  67 {
  68         struct mlx5_priv *priv = dev->data->dev_private;
  69         unsigned int rxqs_n = dev->data->nb_rx_queues;
  70         unsigned int txqs_n = dev->data->nb_tx_queues;
  71         const uint8_t use_app_rss_key =
  72                 !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
  73         int ret = 0;
  74
  75         if (use_app_rss_key &&
  76             (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len !=
  77              MLX5_RSS_HASH_KEY_LEN)) {
  78                 DRV_LOG(ERR, "port %u RSS key len must be %s Bytes long",
  79                         dev->data->port_id, RTE_STR(MLX5_RSS_HASH_KEY_LEN));
  80                 rte_errno = EINVAL;
  81                 return -rte_errno;
  82         }
  83         priv->rss_conf.rss_key =
  84                 mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE,
  85                             MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY);
  86         if (!priv->rss_conf.rss_key) {
  87                 DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)",
  88                         dev->data->port_id, rxqs_n);
  89                 rte_errno = ENOMEM;
  90                 return -rte_errno;
  91         }
  92
  93         if ((dev->data->dev_conf.txmode.offloads &
  94                         RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) &&
  95                         rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) {
  96                 DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag",
  97                         dev->data->port_id);
  98                 return -rte_errno;
  99         }
 100         memcpy(priv->rss_conf.rss_key,
 101                use_app_rss_key ?
 102                dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key :
 103                rss_hash_default_key,
 104                MLX5_RSS_HASH_KEY_LEN);
 105         priv->rss_conf.rss_key_len = MLX5_RSS_HASH_KEY_LEN;
 106         priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
 107         priv->rxq_privs = mlx5_realloc(priv->rxq_privs,
 108                                        MLX5_MEM_RTE | MLX5_MEM_ZERO,
 109                                        sizeof(void *) * rxqs_n, 0,
 110                                        SOCKET_ID_ANY);
 111         if (priv->rxq_privs == NULL) {
 112                 DRV_LOG(ERR, "port %u cannot allocate rxq private data",
 113                         dev->data->port_id);
 114                 rte_errno = ENOMEM;
 115                 return -rte_errno;
 116         }
 117         priv->rxqs = (void *)dev->data->rx_queues;
 118         priv->txqs = (void *)dev->data->tx_queues;
 119         if (txqs_n != priv->txqs_n) {
 120                 DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u",
 121                         dev->data->port_id, priv->txqs_n, txqs_n);
 122                 priv->txqs_n = txqs_n;
 123         }
 124         if (rxqs_n > priv->config.ind_table_max_size) {
 125                 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)",
 126                         dev->data->port_id, rxqs_n);
 127                 rte_errno = EINVAL;
 128                 return -rte_errno;
 129         }
 130         if (rxqs_n != priv->rxqs_n) {
 131                 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
 132                         dev->data->port_id, priv->rxqs_n, rxqs_n);
 133                 priv->rxqs_n = rxqs_n;
 134         }
 135         priv->skip_default_rss_reta = 0;
 136         ret = mlx5_proc_priv_init(dev);
 137         if (ret)
 138                 return ret;
 139         return 0;
 140 }
 141
 142 /**
 143  * Configure default RSS reta.
 144  *
 145  * @param dev
 146  *   Pointer to Ethernet device structure.
 147  *
 148  * @return
 149  *   0 on success, a negative errno value otherwise and rte_errno is set.
 150  */
 151 int
 152 mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev)
 153 {
 154         struct mlx5_priv *priv = dev->data->dev_private;
 155         unsigned int rxqs_n = dev->data->nb_rx_queues;
 156         unsigned int i;
 157         unsigned int j;
 158         unsigned int reta_idx_n;
 159         int ret = 0;
 160         unsigned int *rss_queue_arr = NULL;
 161         unsigned int rss_queue_n = 0;
 162
 163         if (priv->skip_default_rss_reta)
 164                 return ret;
 165         rss_queue_arr = mlx5_malloc(0, rxqs_n * sizeof(unsigned int), 0,
 166                                     SOCKET_ID_ANY);
 167         if (!rss_queue_arr) {
 168                 DRV_LOG(ERR, "port %u cannot allocate RSS queue list (%u)",
 169                         dev->data->port_id, rxqs_n);
 170                 rte_errno = ENOMEM;
 171                 return -rte_errno;
 172         }
 173         for (i = 0, j = 0; i < rxqs_n; i++) {
 174                 struct mlx5_rxq_data *rxq_data;
 175                 struct mlx5_rxq_ctrl *rxq_ctrl;
 176
 177                 rxq_data = (*priv->rxqs)[i];
 178                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 179                 if (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
 180                         rss_queue_arr[j++] = i;
 181         }
 182         rss_queue_n = j;
 183         if (rss_queue_n > priv->config.ind_table_max_size) {
 184                 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)",
 185                         dev->data->port_id, rss_queue_n);
 186                 rte_errno = EINVAL;
 187                 mlx5_free(rss_queue_arr);
 188                 return -rte_errno;
 189         }
 190         DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
 191                 dev->data->port_id, priv->rxqs_n, rxqs_n);
 192         priv->rxqs_n = rxqs_n;
 193         /*
 194          * If the requested number of RX queues is not a power of two,
 195          * use the maximum indirection table size for better balancing.
 196          * The result is always rounded to the next power of two.
 197          */
 198         reta_idx_n = (1 << log2above((rss_queue_n & (rss_queue_n - 1)) ?
 199                                 priv->config.ind_table_max_size :
 200                                 rss_queue_n));
 201         ret = mlx5_rss_reta_index_resize(dev, reta_idx_n);
 202         if (ret) {
 203                 mlx5_free(rss_queue_arr);
 204                 return ret;
 205         }
 206         /*
 207          * When the number of RX queues is not a power of two,
 208          * the remaining table entries are padded with reused WQs
 209          * and hashes are not spread uniformly.
 210          */
 211         for (i = 0, j = 0; (i != reta_idx_n); ++i) {
 212                 (*priv->reta_idx)[i] = rss_queue_arr[j];
 213                 if (++j == rss_queue_n)
 214                         j = 0;
 215         }
 216         mlx5_free(rss_queue_arr);
 217         return ret;
 218 }
 219
 220 /**
 221  * Sets default tuning parameters.
 222  *
 223  * @param dev
 224  *   Pointer to Ethernet device.
 225  * @param[out] info
 226  *   Info structure output buffer.
 227  */
 228 static void
 229 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
 230 {
 231         struct mlx5_priv *priv = dev->data->dev_private;
 232
 233         /* Minimum CPU utilization. */
 234         info->default_rxportconf.ring_size = 256;
 235         info->default_txportconf.ring_size = 256;
 236         info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST;
 237         info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST;
 238         if ((priv->link_speed_capa & RTE_ETH_LINK_SPEED_200G) |
 239                 (priv->link_speed_capa & RTE_ETH_LINK_SPEED_100G)) {
 240                 info->default_rxportconf.nb_queues = 16;
 241                 info->default_txportconf.nb_queues = 16;
 242                 if (dev->data->nb_rx_queues > 2 ||
 243                     dev->data->nb_tx_queues > 2) {
 244                         /* Max Throughput. */
 245                         info->default_rxportconf.ring_size = 2048;
 246                         info->default_txportconf.ring_size = 2048;
 247                 }
 248         } else {
 249                 info->default_rxportconf.nb_queues = 8;
 250                 info->default_txportconf.nb_queues = 8;
 251                 if (dev->data->nb_rx_queues > 2 ||
 252                     dev->data->nb_tx_queues > 2) {
 253                         /* Max Throughput. */
 254                         info->default_rxportconf.ring_size = 4096;
 255                         info->default_txportconf.ring_size = 4096;
 256                 }
 257         }
 258 }
 259
 260 /**
 261  * Sets tx mbuf limiting parameters.
 262  *
 263  * @param dev
 264  *   Pointer to Ethernet device.
 265  * @param[out] info
 266  *   Info structure output buffer.
 267  */
 268 static void
 269 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
 270 {
 271         struct mlx5_priv *priv = dev->data->dev_private;
 272         struct mlx5_dev_config *config = &priv->config;
 273         unsigned int inlen;
 274         uint16_t nb_max;
 275
 276         inlen = (config->txq_inline_max == MLX5_ARG_UNSET) ?
 277                 MLX5_SEND_DEF_INLINE_LEN :
 278                 (unsigned int)config->txq_inline_max;
 279         MLX5_ASSERT(config->txq_inline_min >= 0);
 280         inlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min);
 281         inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX +
 282                                MLX5_ESEG_MIN_INLINE_SIZE -
 283                                MLX5_WQE_CSEG_SIZE -
 284                                MLX5_WQE_ESEG_SIZE -
 285                                MLX5_WQE_DSEG_SIZE * 2);
 286         nb_max = (MLX5_WQE_SIZE_MAX +
 287                   MLX5_ESEG_MIN_INLINE_SIZE -
 288                   MLX5_WQE_CSEG_SIZE -
 289                   MLX5_WQE_ESEG_SIZE -
 290                   MLX5_WQE_DSEG_SIZE -
 291                   inlen) / MLX5_WSEG_SIZE;
 292         info->tx_desc_lim.nb_seg_max = nb_max;
 293         info->tx_desc_lim.nb_mtu_seg_max = nb_max;
 294 }
 295
 296 /**
 297  * DPDK callback to get information about the device.
 298  *
 299  * @param dev
 300  *   Pointer to Ethernet device structure.
 301  * @param[out] info
 302  *   Info structure output buffer.
 303  */
 304 int
 305 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
 306 {
 307         struct mlx5_priv *priv = dev->data->dev_private;
 308         struct mlx5_dev_config *config = &priv->config;
 309         unsigned int max;
 310
 311         /* FIXME: we should ask the device for these values. */
 312         info->min_rx_bufsize = 32;
 313         info->max_rx_pktlen = 65536;
 314         info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE;
 315         /*
 316          * Since we need one CQ per QP, the limit is the minimum number
 317          * between the two values.
 318          */
 319         max = RTE_MIN(priv->sh->device_attr.max_cq,
 320                       priv->sh->device_attr.max_qp);
 321         /* max_rx_queues is uint16_t. */
 322         max = RTE_MIN(max, (unsigned int)UINT16_MAX);
 323         info->max_rx_queues = max;
 324         info->max_tx_queues = max;
 325         info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES;
 326         info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev);
 327         info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG;
 328         info->rx_seg_capa.multi_pools = !config->mprq.enabled;
 329         info->rx_seg_capa.offset_allowed = !config->mprq.enabled;
 330         info->rx_seg_capa.offset_align_log2 = 0;
 331         info->rx_offload_capa = (mlx5_get_rx_port_offloads() |
 332                                  info->rx_queue_offload_capa);
 333         info->tx_offload_capa = mlx5_get_tx_port_offloads(dev);
 334         info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP;
 335         info->if_index = mlx5_ifindex(dev);
 336         info->reta_size = priv->reta_idx_n ?
 337                 priv->reta_idx_n : config->ind_table_max_size;
 338         info->hash_key_size = MLX5_RSS_HASH_KEY_LEN;
 339         info->speed_capa = priv->link_speed_capa;
 340         info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK;
 341         mlx5_set_default_params(dev, info);
 342         mlx5_set_txlimit_params(dev, info);
 343         info->switch_info.name = dev->data->name;
 344         info->switch_info.domain_id = priv->domain_id;
 345         info->switch_info.port_id = priv->representor_id;
 346         if (priv->representor) {
 347                 uint16_t port_id;
 348
 349                 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
 350                         struct mlx5_priv *opriv =
 351                                 rte_eth_devices[port_id].data->dev_private;
 352
 353                         if (!opriv ||
 354                             opriv->representor ||
 355                             opriv->sh != priv->sh ||
 356                             opriv->domain_id != priv->domain_id)
 357                                 continue;
 358                         /*
 359                          * Override switch name with that of the master
 360                          * device.
 361                          */
 362                         info->switch_info.name = opriv->dev_data->name;
 363                         break;
 364                 }
 365         }
 366         return 0;
 367 }
 368
 369 /**
 370  * Calculate representor ID from port switch info.
 371  *
 372  * Uint16 representor ID bits definition:
 373  *   pf: 2
 374  *   type: 2
 375  *   vf/sf: 12
 376  *
 377  * @param info
 378  *   Port switch info.
 379  * @param hpf_type
 380  *   Use this type if port is HPF.
 381  *
 382  * @return
 383  *   Encoded representor ID.
 384  */
 385 uint16_t
 386 mlx5_representor_id_encode(const struct mlx5_switch_info *info,
 387                            enum rte_eth_representor_type hpf_type)
 388 {
 389         enum rte_eth_representor_type type = RTE_ETH_REPRESENTOR_VF;
 390         uint16_t repr = info->port_name;
 391
 392         if (info->representor == 0)
 393                 return UINT16_MAX;
 394         if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF)
 395                 type = RTE_ETH_REPRESENTOR_SF;
 396         if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFHPF) {
 397                 type = hpf_type;
 398                 repr = UINT16_MAX;
 399         }
 400         return MLX5_REPRESENTOR_ID(info->pf_num, type, repr);
 401 }
 402
 403 /**
 404  * DPDK callback to get information about representor.
 405  *
 406  * Representor ID bits definition:
 407  *   vf/sf: 12
 408  *   type: 2
 409  *   pf: 2
 410  *
 411  * @param dev
 412  *   Pointer to Ethernet device structure.
 413  * @param[out] info
 414  *   Nullable info structure output buffer.
 415  *
 416  * @return
 417  *   negative on error, or the number of representor ranges.
 418  */
 419 int
 420 mlx5_representor_info_get(struct rte_eth_dev *dev,
 421                           struct rte_eth_representor_info *info)
 422 {
 423         struct mlx5_priv *priv = dev->data->dev_private;
 424         int n_type = 4; /* Representor types, VF, HPF@VF, SF and HPF@SF. */
 425         int n_pf = 2; /* Number of PFs. */
 426         int i = 0, pf;
 427         int n_entries;
 428
 429         if (info == NULL)
 430                 goto out;
 431
 432         n_entries = n_type * n_pf;
 433         if ((uint32_t)n_entries > info->nb_ranges_alloc)
 434                 n_entries = info->nb_ranges_alloc;
 435
 436         info->controller = 0;
 437         info->pf = priv->pf_bond >= 0 ? priv->pf_bond : 0;
 438         for (pf = 0; pf < n_pf; ++pf) {
 439                 /* VF range. */
 440                 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF;
 441                 info->ranges[i].controller = 0;
 442                 info->ranges[i].pf = pf;
 443                 info->ranges[i].vf = 0;
 444                 info->ranges[i].id_base =
 445                         MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0);
 446                 info->ranges[i].id_end =
 447                         MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
 448                 snprintf(info->ranges[i].name,
 449                          sizeof(info->ranges[i].name), "pf%dvf", pf);
 450                 i++;
 451                 if (i == n_entries)
 452                         break;
 453                 /* HPF range of VF type. */
 454                 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF;
 455                 info->ranges[i].controller = 0;
 456                 info->ranges[i].pf = pf;
 457                 info->ranges[i].vf = UINT16_MAX;
 458                 info->ranges[i].id_base =
 459                         MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
 460                 info->ranges[i].id_end =
 461                         MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
 462                 snprintf(info->ranges[i].name,
 463                          sizeof(info->ranges[i].name), "pf%dvf", pf);
 464                 i++;
 465                 if (i == n_entries)
 466                         break;
 467                 /* SF range. */
 468                 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF;
 469                 info->ranges[i].controller = 0;
 470                 info->ranges[i].pf = pf;
 471                 info->ranges[i].vf = 0;
 472                 info->ranges[i].id_base =
 473                         MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0);
 474                 info->ranges[i].id_end =
 475                         MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
 476                 snprintf(info->ranges[i].name,
 477                          sizeof(info->ranges[i].name), "pf%dsf", pf);
 478                 i++;
 479                 if (i == n_entries)
 480                         break;
 481                 /* HPF range of SF type. */
 482                 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF;
 483                 info->ranges[i].controller = 0;
 484                 info->ranges[i].pf = pf;
 485                 info->ranges[i].vf = UINT16_MAX;
 486                 info->ranges[i].id_base =
 487                         MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
 488                 info->ranges[i].id_end =
 489                         MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
 490                 snprintf(info->ranges[i].name,
 491                          sizeof(info->ranges[i].name), "pf%dsf", pf);
 492                 i++;
 493                 if (i == n_entries)
 494                         break;
 495         }
 496         info->nb_ranges = i;
 497 out:
 498         return n_type * n_pf;
 499 }
 500
 501 /**
 502  * Get firmware version of a device.
 503  *
 504  * @param dev
 505  *   Ethernet device port.
 506  * @param fw_ver
 507  *   String output allocated by caller.
 508  * @param fw_size
 509  *   Size of the output string, including terminating null byte.
 510  *
 511  * @return
 512  *   0 on success, or the size of the non truncated string if too big.
 513  */
 514 int
 515 mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
 516 {
 517         struct mlx5_priv *priv = dev->data->dev_private;
 518         struct mlx5_dev_attr *attr = &priv->sh->device_attr;
 519         size_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1;
 520
 521         if (fw_size < size)
 522                 return size;
 523         if (fw_ver != NULL)
 524                 strlcpy(fw_ver, attr->fw_ver, fw_size);
 525         return 0;
 526 }
 527
 528 /**
 529  * Get supported packet types.
 530  *
 531  * @param dev
 532  *   Pointer to Ethernet device structure.
 533  *
 534  * @return
 535  *   A pointer to the supported Packet types array.
 536  */
 537 const uint32_t *
 538 mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 539 {
 540         static const uint32_t ptypes[] = {
 541                 /* refers to rxq_cq_to_pkt_type() */
 542                 RTE_PTYPE_L2_ETHER,
 543                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 544                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 545                 RTE_PTYPE_L4_NONFRAG,
 546                 RTE_PTYPE_L4_FRAG,
 547                 RTE_PTYPE_L4_TCP,
 548                 RTE_PTYPE_L4_UDP,
 549                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 550                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 551                 RTE_PTYPE_INNER_L4_NONFRAG,
 552                 RTE_PTYPE_INNER_L4_FRAG,
 553                 RTE_PTYPE_INNER_L4_TCP,
 554                 RTE_PTYPE_INNER_L4_UDP,
 555                 RTE_PTYPE_UNKNOWN
 556         };
 557
 558         if (dev->rx_pkt_burst == mlx5_rx_burst ||
 559             dev->rx_pkt_burst == mlx5_rx_burst_mprq ||
 560             dev->rx_pkt_burst == mlx5_rx_burst_vec ||
 561             dev->rx_pkt_burst == mlx5_rx_burst_mprq_vec)
 562                 return ptypes;
 563         return NULL;
 564 }
 565
 566 /**
 567  * DPDK callback to change the MTU.
 568  *
 569  * @param dev
 570  *   Pointer to Ethernet device structure.
 571  * @param in_mtu
 572  *   New MTU.
 573  *
 574  * @return
 575  *   0 on success, a negative errno value otherwise and rte_errno is set.
 576  */
 577 int
 578 mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 579 {
 580         struct mlx5_priv *priv = dev->data->dev_private;
 581         uint16_t kern_mtu = 0;
 582         int ret;
 583
 584         ret = mlx5_get_mtu(dev, &kern_mtu);
 585         if (ret)
 586                 return ret;
 587         /* Set kernel interface MTU first. */
 588         ret = mlx5_set_mtu(dev, mtu);
 589         if (ret)
 590                 return ret;
 591         ret = mlx5_get_mtu(dev, &kern_mtu);
 592         if (ret)
 593                 return ret;
 594         if (kern_mtu == mtu) {
 595                 priv->mtu = mtu;
 596                 DRV_LOG(DEBUG, "port %u adapter MTU set to %u",
 597                         dev->data->port_id, mtu);
 598                 return 0;
 599         }
 600         rte_errno = EAGAIN;
 601         return -rte_errno;
 602 }
 603
 604 /**
 605  * Configure the RX function to use.
 606  *
 607  * @param dev
 608  *   Pointer to private data structure.
 609  *
 610  * @return
 611  *   Pointer to selected Rx burst function.
 612  */
 613 eth_rx_burst_t
 614 mlx5_select_rx_function(struct rte_eth_dev *dev)
 615 {
 616         eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst;
 617
 618         MLX5_ASSERT(dev != NULL);
 619         if (mlx5_check_vec_rx_support(dev) > 0) {
 620                 if (mlx5_mprq_enabled(dev)) {
 621                         rx_pkt_burst = mlx5_rx_burst_mprq_vec;
 622                         DRV_LOG(DEBUG, "port %u selected vectorized"
 623                                 " MPRQ Rx function", dev->data->port_id);
 624                 } else {
 625                         rx_pkt_burst = mlx5_rx_burst_vec;
 626                         DRV_LOG(DEBUG, "port %u selected vectorized"
 627                                 " SPRQ Rx function", dev->data->port_id);
 628                 }
 629         } else if (mlx5_mprq_enabled(dev)) {
 630                 rx_pkt_burst = mlx5_rx_burst_mprq;
 631                 DRV_LOG(DEBUG, "port %u selected MPRQ Rx function",
 632                         dev->data->port_id);
 633         } else {
 634                 DRV_LOG(DEBUG, "port %u selected SPRQ Rx function",
 635                         dev->data->port_id);
 636         }
 637         return rx_pkt_burst;
 638 }
 639
 640 /**
 641  * Get the E-Switch parameters by port id.
 642  *
 643  * @param[in] port
 644  *   Device port id.
 645  * @param[in] valid
 646  *   Device port id is valid, skip check. This flag is useful
 647  *   when trials are performed from probing and device is not
 648  *   flagged as valid yet (in attaching process).
 649  * @param[out] es_domain_id
 650  *   E-Switch domain id.
 651  * @param[out] es_port_id
 652  *   The port id of the port in the E-Switch.
 653  *
 654  * @return
 655  *   pointer to device private data structure containing data needed
 656  *   on success, NULL otherwise and rte_errno is set.
 657  */
 658 struct mlx5_priv *
 659 mlx5_port_to_eswitch_info(uint16_t port, bool valid)
 660 {
 661         struct rte_eth_dev *dev;
 662         struct mlx5_priv *priv;
 663
 664         if (port >= RTE_MAX_ETHPORTS) {
 665                 rte_errno = EINVAL;
 666                 return NULL;
 667         }
 668         if (!valid && !rte_eth_dev_is_valid_port(port)) {
 669                 rte_errno = ENODEV;
 670                 return NULL;
 671         }
 672         dev = &rte_eth_devices[port];
 673         priv = dev->data->dev_private;
 674         if (!(priv->representor || priv->master)) {
 675                 rte_errno = EINVAL;
 676                 return NULL;
 677         }
 678         return priv;
 679 }
 680
 681 /**
 682  * Get the E-Switch parameters by device instance.
 683  *
 684  * @param[in] port
 685  *   Device port id.
 686  * @param[out] es_domain_id
 687  *   E-Switch domain id.
 688  * @param[out] es_port_id
 689  *   The port id of the port in the E-Switch.
 690  *
 691  * @return
 692  *   pointer to device private data structure containing data needed
 693  *   on success, NULL otherwise and rte_errno is set.
 694  */
 695 struct mlx5_priv *
 696 mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev)
 697 {
 698         struct mlx5_priv *priv;
 699
 700         priv = dev->data->dev_private;
 701         if (!(priv->representor || priv->master)) {
 702                 rte_errno = EINVAL;
 703                 return NULL;
 704         }
 705         return priv;
 706 }
 707
 708 /**
 709  * DPDK callback to retrieve hairpin capabilities.
 710  *
 711  * @param dev
 712  *   Pointer to Ethernet device structure.
 713  * @param[out] cap
 714  *   Storage for hairpin capability data.
 715  *
 716  * @return
 717  *   0 on success, a negative errno value otherwise and rte_errno is set.
 718  */
 719 int
 720 mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)
 721 {
 722         struct mlx5_priv *priv = dev->data->dev_private;
 723         struct mlx5_dev_config *config = &priv->config;
 724
 725         if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) {
 726                 rte_errno = ENOTSUP;
 727                 return -rte_errno;
 728         }
 729         cap->max_nb_queues = UINT16_MAX;
 730         cap->max_rx_2_tx = 1;
 731         cap->max_tx_2_rx = 1;
 732         cap->max_nb_desc = 8192;
 733         return 0;
 734 }