drivers/net/mlx5/mlx5_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <netinet/in.h>
   7 #include <sys/queue.h>
   8 #include <stdalign.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11
  12 /* Verbs header. */
  13 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  14 #ifdef PEDANTIC
  15 #pragma GCC diagnostic ignored "-Wpedantic"
  16 #endif
  17 #include <infiniband/verbs.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_common.h>
  23 #include <rte_ether.h>
  24 #include <rte_ethdev_driver.h>
  25 #include <rte_flow.h>
  26 #include <rte_flow_driver.h>
  27 #include <rte_malloc.h>
  28 #include <rte_ip.h>
  29
  30 #include "mlx5.h"
  31 #include "mlx5_defs.h"
  32 #include "mlx5_flow.h"
  33 #include "mlx5_glue.h"
  34 #include "mlx5_prm.h"
  35 #include "mlx5_rxtx.h"
  36
  37 /* Dev ops structure defined in mlx5.c */
  38 extern const struct eth_dev_ops mlx5_dev_ops;
  39 extern const struct eth_dev_ops mlx5_dev_ops_isolate;
  40
  41 /** Device flow drivers. */
  42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  43 extern const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops;
  44 #endif
  45 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops;
  46
  47 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops;
  48
  49 const struct mlx5_flow_driver_ops *flow_drv_ops[] = {
  50         [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops,
  51 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  52         [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops,
  53 #endif
  54         [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops,
  55         [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops
  56 };
  57
  58 enum mlx5_expansion {
  59         MLX5_EXPANSION_ROOT,
  60         MLX5_EXPANSION_ROOT_OUTER,
  61         MLX5_EXPANSION_ROOT_ETH_VLAN,
  62         MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN,
  63         MLX5_EXPANSION_OUTER_ETH,
  64         MLX5_EXPANSION_OUTER_ETH_VLAN,
  65         MLX5_EXPANSION_OUTER_VLAN,
  66         MLX5_EXPANSION_OUTER_IPV4,
  67         MLX5_EXPANSION_OUTER_IPV4_UDP,
  68         MLX5_EXPANSION_OUTER_IPV4_TCP,
  69         MLX5_EXPANSION_OUTER_IPV6,
  70         MLX5_EXPANSION_OUTER_IPV6_UDP,
  71         MLX5_EXPANSION_OUTER_IPV6_TCP,
  72         MLX5_EXPANSION_VXLAN,
  73         MLX5_EXPANSION_VXLAN_GPE,
  74         MLX5_EXPANSION_GRE,
  75         MLX5_EXPANSION_MPLS,
  76         MLX5_EXPANSION_ETH,
  77         MLX5_EXPANSION_ETH_VLAN,
  78         MLX5_EXPANSION_VLAN,
  79         MLX5_EXPANSION_IPV4,
  80         MLX5_EXPANSION_IPV4_UDP,
  81         MLX5_EXPANSION_IPV4_TCP,
  82         MLX5_EXPANSION_IPV6,
  83         MLX5_EXPANSION_IPV6_UDP,
  84         MLX5_EXPANSION_IPV6_TCP,
  85 };
  86
  87 /** Supported expansion of items. */
  88 static const struct rte_flow_expand_node mlx5_support_expansion[] = {
  89         [MLX5_EXPANSION_ROOT] = {
  90                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH,
  91                                                  MLX5_EXPANSION_IPV4,
  92                                                  MLX5_EXPANSION_IPV6),
  93                 .type = RTE_FLOW_ITEM_TYPE_END,
  94         },
  95         [MLX5_EXPANSION_ROOT_OUTER] = {
  96                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH,
  97                                                  MLX5_EXPANSION_OUTER_IPV4,
  98                                                  MLX5_EXPANSION_OUTER_IPV6),
  99                 .type = RTE_FLOW_ITEM_TYPE_END,
 100         },
 101         [MLX5_EXPANSION_ROOT_ETH_VLAN] = {
 102                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH_VLAN),
 103                 .type = RTE_FLOW_ITEM_TYPE_END,
 104         },
 105         [MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN] = {
 106                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH_VLAN),
 107                 .type = RTE_FLOW_ITEM_TYPE_END,
 108         },
 109         [MLX5_EXPANSION_OUTER_ETH] = {
 110                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4,
 111                                                  MLX5_EXPANSION_OUTER_IPV6,
 112                                                  MLX5_EXPANSION_MPLS),
 113                 .type = RTE_FLOW_ITEM_TYPE_ETH,
 114                 .rss_types = 0,
 115         },
 116         [MLX5_EXPANSION_OUTER_ETH_VLAN] = {
 117                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN),
 118                 .type = RTE_FLOW_ITEM_TYPE_ETH,
 119                 .rss_types = 0,
 120         },
 121         [MLX5_EXPANSION_OUTER_VLAN] = {
 122                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4,
 123                                                  MLX5_EXPANSION_OUTER_IPV6),
 124                 .type = RTE_FLOW_ITEM_TYPE_VLAN,
 125         },
 126         [MLX5_EXPANSION_OUTER_IPV4] = {
 127                 .next = RTE_FLOW_EXPAND_RSS_NEXT
 128                         (MLX5_EXPANSION_OUTER_IPV4_UDP,
 129                          MLX5_EXPANSION_OUTER_IPV4_TCP,
 130                          MLX5_EXPANSION_GRE,
 131                          MLX5_EXPANSION_IPV4,
 132                          MLX5_EXPANSION_IPV6),
 133                 .type = RTE_FLOW_ITEM_TYPE_IPV4,
 134                 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 |
 135                         ETH_RSS_NONFRAG_IPV4_OTHER,
 136         },
 137         [MLX5_EXPANSION_OUTER_IPV4_UDP] = {
 138                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN,
 139                                                  MLX5_EXPANSION_VXLAN_GPE),
 140                 .type = RTE_FLOW_ITEM_TYPE_UDP,
 141                 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP,
 142         },
 143         [MLX5_EXPANSION_OUTER_IPV4_TCP] = {
 144                 .type = RTE_FLOW_ITEM_TYPE_TCP,
 145                 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP,
 146         },
 147         [MLX5_EXPANSION_OUTER_IPV6] = {
 148                 .next = RTE_FLOW_EXPAND_RSS_NEXT
 149                         (MLX5_EXPANSION_OUTER_IPV6_UDP,
 150                          MLX5_EXPANSION_OUTER_IPV6_TCP,
 151                          MLX5_EXPANSION_IPV4,
 152                          MLX5_EXPANSION_IPV6),
 153                 .type = RTE_FLOW_ITEM_TYPE_IPV6,
 154                 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 |
 155                         ETH_RSS_NONFRAG_IPV6_OTHER,
 156         },
 157         [MLX5_EXPANSION_OUTER_IPV6_UDP] = {
 158                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN,
 159                                                  MLX5_EXPANSION_VXLAN_GPE),
 160                 .type = RTE_FLOW_ITEM_TYPE_UDP,
 161                 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP,
 162         },
 163         [MLX5_EXPANSION_OUTER_IPV6_TCP] = {
 164                 .type = RTE_FLOW_ITEM_TYPE_TCP,
 165                 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP,
 166         },
 167         [MLX5_EXPANSION_VXLAN] = {
 168                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH),
 169                 .type = RTE_FLOW_ITEM_TYPE_VXLAN,
 170         },
 171         [MLX5_EXPANSION_VXLAN_GPE] = {
 172                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH,
 173                                                  MLX5_EXPANSION_IPV4,
 174                                                  MLX5_EXPANSION_IPV6),
 175                 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE,
 176         },
 177         [MLX5_EXPANSION_GRE] = {
 178                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4),
 179                 .type = RTE_FLOW_ITEM_TYPE_GRE,
 180         },
 181         [MLX5_EXPANSION_MPLS] = {
 182                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4,
 183                                                  MLX5_EXPANSION_IPV6),
 184                 .type = RTE_FLOW_ITEM_TYPE_MPLS,
 185         },
 186         [MLX5_EXPANSION_ETH] = {
 187                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4,
 188                                                  MLX5_EXPANSION_IPV6),
 189                 .type = RTE_FLOW_ITEM_TYPE_ETH,
 190         },
 191         [MLX5_EXPANSION_ETH_VLAN] = {
 192                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN),
 193                 .type = RTE_FLOW_ITEM_TYPE_ETH,
 194         },
 195         [MLX5_EXPANSION_VLAN] = {
 196                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4,
 197                                                  MLX5_EXPANSION_IPV6),
 198                 .type = RTE_FLOW_ITEM_TYPE_VLAN,
 199         },
 200         [MLX5_EXPANSION_IPV4] = {
 201                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP,
 202                                                  MLX5_EXPANSION_IPV4_TCP),
 203                 .type = RTE_FLOW_ITEM_TYPE_IPV4,
 204                 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 |
 205                         ETH_RSS_NONFRAG_IPV4_OTHER,
 206         },
 207         [MLX5_EXPANSION_IPV4_UDP] = {
 208                 .type = RTE_FLOW_ITEM_TYPE_UDP,
 209                 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP,
 210         },
 211         [MLX5_EXPANSION_IPV4_TCP] = {
 212                 .type = RTE_FLOW_ITEM_TYPE_TCP,
 213                 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP,
 214         },
 215         [MLX5_EXPANSION_IPV6] = {
 216                 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP,
 217                                                  MLX5_EXPANSION_IPV6_TCP),
 218                 .type = RTE_FLOW_ITEM_TYPE_IPV6,
 219                 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 |
 220                         ETH_RSS_NONFRAG_IPV6_OTHER,
 221         },
 222         [MLX5_EXPANSION_IPV6_UDP] = {
 223                 .type = RTE_FLOW_ITEM_TYPE_UDP,
 224                 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP,
 225         },
 226         [MLX5_EXPANSION_IPV6_TCP] = {
 227                 .type = RTE_FLOW_ITEM_TYPE_TCP,
 228                 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP,
 229         },
 230 };
 231
 232 static const struct rte_flow_ops mlx5_flow_ops = {
 233         .validate = mlx5_flow_validate,
 234         .create = mlx5_flow_create,
 235         .destroy = mlx5_flow_destroy,
 236         .flush = mlx5_flow_flush,
 237         .isolate = mlx5_flow_isolate,
 238         .query = mlx5_flow_query,
 239 };
 240
 241 /* Convert FDIR request to Generic flow. */
 242 struct mlx5_fdir {
 243         struct rte_flow_attr attr;
 244         struct rte_flow_item items[4];
 245         struct rte_flow_item_eth l2;
 246         struct rte_flow_item_eth l2_mask;
 247         union {
 248                 struct rte_flow_item_ipv4 ipv4;
 249                 struct rte_flow_item_ipv6 ipv6;
 250         } l3;
 251         union {
 252                 struct rte_flow_item_ipv4 ipv4;
 253                 struct rte_flow_item_ipv6 ipv6;
 254         } l3_mask;
 255         union {
 256                 struct rte_flow_item_udp udp;
 257                 struct rte_flow_item_tcp tcp;
 258         } l4;
 259         union {
 260                 struct rte_flow_item_udp udp;
 261                 struct rte_flow_item_tcp tcp;
 262         } l4_mask;
 263         struct rte_flow_action actions[2];
 264         struct rte_flow_action_queue queue;
 265 };
 266
 267 /* Map of Verbs to Flow priority with 8 Verbs priorities. */
 268 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = {
 269         { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 },
 270 };
 271
 272 /* Map of Verbs to Flow priority with 16 Verbs priorities. */
 273 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = {
 274         { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 },
 275         { 9, 10, 11 }, { 12, 13, 14 },
 276 };
 277
 278 /* Tunnel information. */
 279 struct mlx5_flow_tunnel_info {
 280         uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */
 281         uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */
 282 };
 283
 284 static struct mlx5_flow_tunnel_info tunnels_info[] = {
 285         {
 286                 .tunnel = MLX5_FLOW_LAYER_VXLAN,
 287                 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP,
 288         },
 289         {
 290                 .tunnel = MLX5_FLOW_LAYER_GENEVE,
 291                 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP,
 292         },
 293         {
 294                 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE,
 295                 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP,
 296         },
 297         {
 298                 .tunnel = MLX5_FLOW_LAYER_GRE,
 299                 .ptype = RTE_PTYPE_TUNNEL_GRE,
 300         },
 301         {
 302                 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP,
 303                 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP,
 304         },
 305         {
 306                 .tunnel = MLX5_FLOW_LAYER_MPLS,
 307                 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE,
 308         },
 309         {
 310                 .tunnel = MLX5_FLOW_LAYER_NVGRE,
 311                 .ptype = RTE_PTYPE_TUNNEL_NVGRE,
 312         },
 313         {
 314                 .tunnel = MLX5_FLOW_LAYER_IPIP,
 315                 .ptype = RTE_PTYPE_TUNNEL_IP,
 316         },
 317         {
 318                 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP,
 319                 .ptype = RTE_PTYPE_TUNNEL_IP,
 320         },
 321 };
 322
 323 enum mlx5_feature_name {
 324         MLX5_HAIRPIN_RX,
 325         MLX5_HAIRPIN_TX,
 326         MLX5_APPLICATION,
 327 };
 328
 329 /**
 330  * Translate tag ID to register.
 331  *
 332  * @param[in] dev
 333  *   Pointer to the Ethernet device structure.
 334  * @param[in] feature
 335  *   The feature that request the register.
 336  * @param[in] id
 337  *   The request register ID.
 338  * @param[out] error
 339  *   Error description in case of any.
 340  *
 341  * @return
 342  *   The request register on success, a negative errno
 343  *   value otherwise and rte_errno is set.
 344  */
 345 __rte_unused
 346 static enum modify_reg flow_get_reg_id(struct rte_eth_dev *dev,
 347                                        enum mlx5_feature_name feature,
 348                                        uint32_t id,
 349                                        struct rte_flow_error *error)
 350 {
 351         static enum modify_reg id2reg[] = {
 352                 [0] = REG_A,
 353                 [1] = REG_C_2,
 354                 [2] = REG_C_3,
 355                 [3] = REG_C_4,
 356                 [4] = REG_B,};
 357
 358         dev = (void *)dev;
 359         switch (feature) {
 360         case MLX5_HAIRPIN_RX:
 361                 return REG_B;
 362         case MLX5_HAIRPIN_TX:
 363                 return REG_A;
 364         case MLX5_APPLICATION:
 365                 if (id > 4)
 366                         return rte_flow_error_set(error, EINVAL,
 367                                                   RTE_FLOW_ERROR_TYPE_ITEM,
 368                                                   NULL, "invalid tag id");
 369                 return id2reg[id];
 370         }
 371         return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
 372                                   NULL, "invalid feature name");
 373 }
 374
 375
 376 /**
 377  * Check extensive flow metadata register support.
 378  *
 379  * @param dev
 380  *   Pointer to rte_eth_dev structure.
 381  *
 382  * @return
 383  *   True if device supports extensive flow metadata register, otherwise false.
 384  */
 385 bool
 386 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev)
 387 {
 388         struct mlx5_priv *priv = dev->data->dev_private;
 389         struct mlx5_dev_config *config = &priv->config;
 390
 391         /*
 392          * Having available reg_c can be regarded inclusively as supporting
 393          * extensive flow metadata register, which could mean,
 394          * - metadata register copy action by modify header.
 395          * - 16 modify header actions is supported.
 396          * - reg_c's are preserved across different domain (FDB and NIC) on
 397          *   packet loopback by flow lookup miss.
 398          */
 399         return config->flow_mreg_c[2] != REG_NONE;
 400 }
 401
 402 /**
 403  * Discover the maximum number of priority available.
 404  *
 405  * @param[in] dev
 406  *   Pointer to the Ethernet device structure.
 407  *
 408  * @return
 409  *   number of supported flow priority on success, a negative errno
 410  *   value otherwise and rte_errno is set.
 411  */
 412 int
 413 mlx5_flow_discover_priorities(struct rte_eth_dev *dev)
 414 {
 415         struct mlx5_priv *priv = dev->data->dev_private;
 416         struct {
 417                 struct ibv_flow_attr attr;
 418                 struct ibv_flow_spec_eth eth;
 419                 struct ibv_flow_spec_action_drop drop;
 420         } flow_attr = {
 421                 .attr = {
 422                         .num_of_specs = 2,
 423                         .port = (uint8_t)priv->ibv_port,
 424                 },
 425                 .eth = {
 426                         .type = IBV_FLOW_SPEC_ETH,
 427                         .size = sizeof(struct ibv_flow_spec_eth),
 428                 },
 429                 .drop = {
 430                         .size = sizeof(struct ibv_flow_spec_action_drop),
 431                         .type = IBV_FLOW_SPEC_ACTION_DROP,
 432                 },
 433         };
 434         struct ibv_flow *flow;
 435         struct mlx5_hrxq *drop = mlx5_hrxq_drop_new(dev);
 436         uint16_t vprio[] = { 8, 16 };
 437         int i;
 438         int priority = 0;
 439
 440         if (!drop) {
 441                 rte_errno = ENOTSUP;
 442                 return -rte_errno;
 443         }
 444         for (i = 0; i != RTE_DIM(vprio); i++) {
 445                 flow_attr.attr.priority = vprio[i] - 1;
 446                 flow = mlx5_glue->create_flow(drop->qp, &flow_attr.attr);
 447                 if (!flow)
 448                         break;
 449                 claim_zero(mlx5_glue->destroy_flow(flow));
 450                 priority = vprio[i];
 451         }
 452         mlx5_hrxq_drop_release(dev);
 453         switch (priority) {
 454         case 8:
 455                 priority = RTE_DIM(priority_map_3);
 456                 break;
 457         case 16:
 458                 priority = RTE_DIM(priority_map_5);
 459                 break;
 460         default:
 461                 rte_errno = ENOTSUP;
 462                 DRV_LOG(ERR,
 463                         "port %u verbs maximum priority: %d expected 8/16",
 464                         dev->data->port_id, priority);
 465                 return -rte_errno;
 466         }
 467         DRV_LOG(INFO, "port %u flow maximum priority: %d",
 468                 dev->data->port_id, priority);
 469         return priority;
 470 }
 471
 472 /**
 473  * Adjust flow priority based on the highest layer and the request priority.
 474  *
 475  * @param[in] dev
 476  *   Pointer to the Ethernet device structure.
 477  * @param[in] priority
 478  *   The rule base priority.
 479  * @param[in] subpriority
 480  *   The priority based on the items.
 481  *
 482  * @return
 483  *   The new priority.
 484  */
 485 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
 486                                    uint32_t subpriority)
 487 {
 488         uint32_t res = 0;
 489         struct mlx5_priv *priv = dev->data->dev_private;
 490
 491         switch (priv->config.flow_prio) {
 492         case RTE_DIM(priority_map_3):
 493                 res = priority_map_3[priority][subpriority];
 494                 break;
 495         case RTE_DIM(priority_map_5):
 496                 res = priority_map_5[priority][subpriority];
 497                 break;
 498         }
 499         return  res;
 500 }
 501
 502 /**
 503  * Verify the @p item specifications (spec, last, mask) are compatible with the
 504  * NIC capabilities.
 505  *
 506  * @param[in] item
 507  *   Item specification.
 508  * @param[in] mask
 509  *   @p item->mask or flow default bit-masks.
 510  * @param[in] nic_mask
 511  *   Bit-masks covering supported fields by the NIC to compare with user mask.
 512  * @param[in] size
 513  *   Bit-masks size in bytes.
 514  * @param[out] error
 515  *   Pointer to error structure.
 516  *
 517  * @return
 518  *   0 on success, a negative errno value otherwise and rte_errno is set.
 519  */
 520 int
 521 mlx5_flow_item_acceptable(const struct rte_flow_item *item,
 522                           const uint8_t *mask,
 523                           const uint8_t *nic_mask,
 524                           unsigned int size,
 525                           struct rte_flow_error *error)
 526 {
 527         unsigned int i;
 528
 529         assert(nic_mask);
 530         for (i = 0; i < size; ++i)
 531                 if ((nic_mask[i] | mask[i]) != nic_mask[i])
 532                         return rte_flow_error_set(error, ENOTSUP,
 533                                                   RTE_FLOW_ERROR_TYPE_ITEM,
 534                                                   item,
 535                                                   "mask enables non supported"
 536                                                   " bits");
 537         if (!item->spec && (item->mask || item->last))
 538                 return rte_flow_error_set(error, EINVAL,
 539                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
 540                                           "mask/last without a spec is not"
 541                                           " supported");
 542         if (item->spec && item->last) {
 543                 uint8_t spec[size];
 544                 uint8_t last[size];
 545                 unsigned int i;
 546                 int ret;
 547
 548                 for (i = 0; i < size; ++i) {
 549                         spec[i] = ((const uint8_t *)item->spec)[i] & mask[i];
 550                         last[i] = ((const uint8_t *)item->last)[i] & mask[i];
 551                 }
 552                 ret = memcmp(spec, last, size);
 553                 if (ret != 0)
 554                         return rte_flow_error_set(error, EINVAL,
 555                                                   RTE_FLOW_ERROR_TYPE_ITEM,
 556                                                   item,
 557                                                   "range is not valid");
 558         }
 559         return 0;
 560 }
 561
 562 /**
 563  * Adjust the hash fields according to the @p flow information.
 564  *
 565  * @param[in] dev_flow.
 566  *   Pointer to the mlx5_flow.
 567  * @param[in] tunnel
 568  *   1 when the hash field is for a tunnel item.
 569  * @param[in] layer_types
 570  *   ETH_RSS_* types.
 571  * @param[in] hash_fields
 572  *   Item hash fields.
 573  *
 574  * @return
 575  *   The hash fields that should be used.
 576  */
 577 uint64_t
 578 mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow,
 579                             int tunnel __rte_unused, uint64_t layer_types,
 580                             uint64_t hash_fields)
 581 {
 582         struct rte_flow *flow = dev_flow->flow;
 583 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 584         int rss_request_inner = flow->rss.level >= 2;
 585
 586         /* Check RSS hash level for tunnel. */
 587         if (tunnel && rss_request_inner)
 588                 hash_fields |= IBV_RX_HASH_INNER;
 589         else if (tunnel || rss_request_inner)
 590                 return 0;
 591 #endif
 592         /* Check if requested layer matches RSS hash fields. */
 593         if (!(flow->rss.types & layer_types))
 594                 return 0;
 595         return hash_fields;
 596 }
 597
 598 /**
 599  * Lookup and set the ptype in the data Rx part.  A single Ptype can be used,
 600  * if several tunnel rules are used on this queue, the tunnel ptype will be
 601  * cleared.
 602  *
 603  * @param rxq_ctrl
 604  *   Rx queue to update.
 605  */
 606 static void
 607 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl)
 608 {
 609         unsigned int i;
 610         uint32_t tunnel_ptype = 0;
 611
 612         /* Look up for the ptype to use. */
 613         for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) {
 614                 if (!rxq_ctrl->flow_tunnels_n[i])
 615                         continue;
 616                 if (!tunnel_ptype) {
 617                         tunnel_ptype = tunnels_info[i].ptype;
 618                 } else {
 619                         tunnel_ptype = 0;
 620                         break;
 621                 }
 622         }
 623         rxq_ctrl->rxq.tunnel = tunnel_ptype;
 624 }
 625
 626 /**
 627  * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the devive
 628  * flow.
 629  *
 630  * @param[in] dev
 631  *   Pointer to the Ethernet device structure.
 632  * @param[in] dev_flow
 633  *   Pointer to device flow structure.
 634  */
 635 static void
 636 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow)
 637 {
 638         struct mlx5_priv *priv = dev->data->dev_private;
 639         struct rte_flow *flow = dev_flow->flow;
 640         const int mark = !!(dev_flow->actions &
 641                             (MLX5_FLOW_ACTION_FLAG | MLX5_FLOW_ACTION_MARK));
 642         const int tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL);
 643         unsigned int i;
 644
 645         for (i = 0; i != flow->rss.queue_num; ++i) {
 646                 int idx = (*flow->rss.queue)[i];
 647                 struct mlx5_rxq_ctrl *rxq_ctrl =
 648                         container_of((*priv->rxqs)[idx],
 649                                      struct mlx5_rxq_ctrl, rxq);
 650
 651                 if (mark) {
 652                         rxq_ctrl->rxq.mark = 1;
 653                         rxq_ctrl->flow_mark_n++;
 654                 }
 655                 if (tunnel) {
 656                         unsigned int j;
 657
 658                         /* Increase the counter matching the flow. */
 659                         for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) {
 660                                 if ((tunnels_info[j].tunnel &
 661                                      dev_flow->layers) ==
 662                                     tunnels_info[j].tunnel) {
 663                                         rxq_ctrl->flow_tunnels_n[j]++;
 664                                         break;
 665                                 }
 666                         }
 667                         flow_rxq_tunnel_ptype_update(rxq_ctrl);
 668                 }
 669         }
 670 }
 671
 672 /**
 673  * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow
 674  *
 675  * @param[in] dev
 676  *   Pointer to the Ethernet device structure.
 677  * @param[in] flow
 678  *   Pointer to flow structure.
 679  */
 680 static void
 681 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow)
 682 {
 683         struct mlx5_flow *dev_flow;
 684
 685         LIST_FOREACH(dev_flow, &flow->dev_flows, next)
 686                 flow_drv_rxq_flags_set(dev, dev_flow);
 687 }
 688
 689 /**
 690  * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the
 691  * device flow if no other flow uses it with the same kind of request.
 692  *
 693  * @param dev
 694  *   Pointer to Ethernet device.
 695  * @param[in] dev_flow
 696  *   Pointer to the device flow.
 697  */
 698 static void
 699 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow)
 700 {
 701         struct mlx5_priv *priv = dev->data->dev_private;
 702         struct rte_flow *flow = dev_flow->flow;
 703         const int mark = !!(dev_flow->actions &
 704                             (MLX5_FLOW_ACTION_FLAG | MLX5_FLOW_ACTION_MARK));
 705         const int tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL);
 706         unsigned int i;
 707
 708         assert(dev->data->dev_started);
 709         for (i = 0; i != flow->rss.queue_num; ++i) {
 710                 int idx = (*flow->rss.queue)[i];
 711                 struct mlx5_rxq_ctrl *rxq_ctrl =
 712                         container_of((*priv->rxqs)[idx],
 713                                      struct mlx5_rxq_ctrl, rxq);
 714
 715                 if (mark) {
 716                         rxq_ctrl->flow_mark_n--;
 717                         rxq_ctrl->rxq.mark = !!rxq_ctrl->flow_mark_n;
 718                 }
 719                 if (tunnel) {
 720                         unsigned int j;
 721
 722                         /* Decrease the counter matching the flow. */
 723                         for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) {
 724                                 if ((tunnels_info[j].tunnel &
 725                                      dev_flow->layers) ==
 726                                     tunnels_info[j].tunnel) {
 727                                         rxq_ctrl->flow_tunnels_n[j]--;
 728                                         break;
 729                                 }
 730                         }
 731                         flow_rxq_tunnel_ptype_update(rxq_ctrl);
 732                 }
 733         }
 734 }
 735
 736 /**
 737  * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the
 738  * @p flow if no other flow uses it with the same kind of request.
 739  *
 740  * @param dev
 741  *   Pointer to Ethernet device.
 742  * @param[in] flow
 743  *   Pointer to the flow.
 744  */
 745 static void
 746 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow)
 747 {
 748         struct mlx5_flow *dev_flow;
 749
 750         LIST_FOREACH(dev_flow, &flow->dev_flows, next)
 751                 flow_drv_rxq_flags_trim(dev, dev_flow);
 752 }
 753
 754 /**
 755  * Clear the Mark/Flag and Tunnel ptype information in all Rx queues.
 756  *
 757  * @param dev
 758  *   Pointer to Ethernet device.
 759  */
 760 static void
 761 flow_rxq_flags_clear(struct rte_eth_dev *dev)
 762 {
 763         struct mlx5_priv *priv = dev->data->dev_private;
 764         unsigned int i;
 765
 766         for (i = 0; i != priv->rxqs_n; ++i) {
 767                 struct mlx5_rxq_ctrl *rxq_ctrl;
 768                 unsigned int j;
 769
 770                 if (!(*priv->rxqs)[i])
 771                         continue;
 772                 rxq_ctrl = container_of((*priv->rxqs)[i],
 773                                         struct mlx5_rxq_ctrl, rxq);
 774                 rxq_ctrl->flow_mark_n = 0;
 775                 rxq_ctrl->rxq.mark = 0;
 776                 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j)
 777                         rxq_ctrl->flow_tunnels_n[j] = 0;
 778                 rxq_ctrl->rxq.tunnel = 0;
 779         }
 780 }
 781
 782 /*
 783  * return a pointer to the desired action in the list of actions.
 784  *
 785  * @param[in] actions
 786  *   The list of actions to search the action in.
 787  * @param[in] action
 788  *   The action to find.
 789  *
 790  * @return
 791  *   Pointer to the action in the list, if found. NULL otherwise.
 792  */
 793 const struct rte_flow_action *
 794 mlx5_flow_find_action(const struct rte_flow_action *actions,
 795                       enum rte_flow_action_type action)
 796 {
 797         if (actions == NULL)
 798                 return NULL;
 799         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++)
 800                 if (actions->type == action)
 801                         return actions;
 802         return NULL;
 803 }
 804
 805 /*
 806  * Validate the flag action.
 807  *
 808  * @param[in] action_flags
 809  *   Bit-fields that holds the actions detected until now.
 810  * @param[in] attr
 811  *   Attributes of flow that includes this action.
 812  * @param[out] error
 813  *   Pointer to error structure.
 814  *
 815  * @return
 816  *   0 on success, a negative errno value otherwise and rte_errno is set.
 817  */
 818 int
 819 mlx5_flow_validate_action_flag(uint64_t action_flags,
 820                                const struct rte_flow_attr *attr,
 821                                struct rte_flow_error *error)
 822 {
 823
 824         if (action_flags & MLX5_FLOW_ACTION_DROP)
 825                 return rte_flow_error_set(error, EINVAL,
 826                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 827                                           "can't drop and flag in same flow");
 828         if (action_flags & MLX5_FLOW_ACTION_MARK)
 829                 return rte_flow_error_set(error, EINVAL,
 830                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 831                                           "can't mark and flag in same flow");
 832         if (action_flags & MLX5_FLOW_ACTION_FLAG)
 833                 return rte_flow_error_set(error, EINVAL,
 834                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 835                                           "can't have 2 flag"
 836                                           " actions in same flow");
 837         if (attr->egress)
 838                 return rte_flow_error_set(error, ENOTSUP,
 839                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,
 840                                           "flag action not supported for "
 841                                           "egress");
 842         return 0;
 843 }
 844
 845 /*
 846  * Validate the mark action.
 847  *
 848  * @param[in] action
 849  *   Pointer to the queue action.
 850  * @param[in] action_flags
 851  *   Bit-fields that holds the actions detected until now.
 852  * @param[in] attr
 853  *   Attributes of flow that includes this action.
 854  * @param[out] error
 855  *   Pointer to error structure.
 856  *
 857  * @return
 858  *   0 on success, a negative errno value otherwise and rte_errno is set.
 859  */
 860 int
 861 mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
 862                                uint64_t action_flags,
 863                                const struct rte_flow_attr *attr,
 864                                struct rte_flow_error *error)
 865 {
 866         const struct rte_flow_action_mark *mark = action->conf;
 867
 868         if (!mark)
 869                 return rte_flow_error_set(error, EINVAL,
 870                                           RTE_FLOW_ERROR_TYPE_ACTION,
 871                                           action,
 872                                           "configuration cannot be null");
 873         if (mark->id >= MLX5_FLOW_MARK_MAX)
 874                 return rte_flow_error_set(error, EINVAL,
 875                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
 876                                           &mark->id,
 877                                           "mark id must in 0 <= id < "
 878                                           RTE_STR(MLX5_FLOW_MARK_MAX));
 879         if (action_flags & MLX5_FLOW_ACTION_DROP)
 880                 return rte_flow_error_set(error, EINVAL,
 881                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 882                                           "can't drop and mark in same flow");
 883         if (action_flags & MLX5_FLOW_ACTION_FLAG)
 884                 return rte_flow_error_set(error, EINVAL,
 885                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 886                                           "can't flag and mark in same flow");
 887         if (action_flags & MLX5_FLOW_ACTION_MARK)
 888                 return rte_flow_error_set(error, EINVAL,
 889                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 890                                           "can't have 2 mark actions in same"
 891                                           " flow");
 892         if (attr->egress)
 893                 return rte_flow_error_set(error, ENOTSUP,
 894                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,
 895                                           "mark action not supported for "
 896                                           "egress");
 897         return 0;
 898 }
 899
 900 /*
 901  * Validate the drop action.
 902  *
 903  * @param[in] action_flags
 904  *   Bit-fields that holds the actions detected until now.
 905  * @param[in] attr
 906  *   Attributes of flow that includes this action.
 907  * @param[out] error
 908  *   Pointer to error structure.
 909  *
 910  * @return
 911  *   0 on success, a negative errno value otherwise and rte_errno is set.
 912  */
 913 int
 914 mlx5_flow_validate_action_drop(uint64_t action_flags,
 915                                const struct rte_flow_attr *attr,
 916                                struct rte_flow_error *error)
 917 {
 918         if (action_flags & MLX5_FLOW_ACTION_FLAG)
 919                 return rte_flow_error_set(error, EINVAL,
 920                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 921                                           "can't drop and flag in same flow");
 922         if (action_flags & MLX5_FLOW_ACTION_MARK)
 923                 return rte_flow_error_set(error, EINVAL,
 924                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 925                                           "can't drop and mark in same flow");
 926         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
 927                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
 928                 return rte_flow_error_set(error, EINVAL,
 929                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 930                                           "can't have 2 fate actions in"
 931                                           " same flow");
 932         if (attr->egress)
 933                 return rte_flow_error_set(error, ENOTSUP,
 934                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,
 935                                           "drop action not supported for "
 936                                           "egress");
 937         return 0;
 938 }
 939
 940 /*
 941  * Validate the queue action.
 942  *
 943  * @param[in] action
 944  *   Pointer to the queue action.
 945  * @param[in] action_flags
 946  *   Bit-fields that holds the actions detected until now.
 947  * @param[in] dev
 948  *   Pointer to the Ethernet device structure.
 949  * @param[in] attr
 950  *   Attributes of flow that includes this action.
 951  * @param[out] error
 952  *   Pointer to error structure.
 953  *
 954  * @return
 955  *   0 on success, a negative errno value otherwise and rte_errno is set.
 956  */
 957 int
 958 mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
 959                                 uint64_t action_flags,
 960                                 struct rte_eth_dev *dev,
 961                                 const struct rte_flow_attr *attr,
 962                                 struct rte_flow_error *error)
 963 {
 964         struct mlx5_priv *priv = dev->data->dev_private;
 965         const struct rte_flow_action_queue *queue = action->conf;
 966
 967         if (action_flags & MLX5_FLOW_FATE_ACTIONS)
 968                 return rte_flow_error_set(error, EINVAL,
 969                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 970                                           "can't have 2 fate actions in"
 971                                           " same flow");
 972         if (!priv->rxqs_n)
 973                 return rte_flow_error_set(error, EINVAL,
 974                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
 975                                           NULL, "No Rx queues configured");
 976         if (queue->index >= priv->rxqs_n)
 977                 return rte_flow_error_set(error, EINVAL,
 978                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
 979                                           &queue->index,
 980                                           "queue index out of range");
 981         if (!(*priv->rxqs)[queue->index])
 982                 return rte_flow_error_set(error, EINVAL,
 983                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
 984                                           &queue->index,
 985                                           "queue is not configured");
 986         if (attr->egress)
 987                 return rte_flow_error_set(error, ENOTSUP,
 988                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,
 989                                           "queue action not supported for "
 990                                           "egress");
 991         return 0;
 992 }
 993
 994 /*
 995  * Validate the rss action.
 996  *
 997  * @param[in] action
 998  *   Pointer to the queue action.
 999  * @param[in] action_flags
1000  *   Bit-fields that holds the actions detected until now.
1001  * @param[in] dev
1002  *   Pointer to the Ethernet device structure.
1003  * @param[in] attr
1004  *   Attributes of flow that includes this action.
1005  * @param[in] item_flags
1006  *   Items that were detected.
1007  * @param[out] error
1008  *   Pointer to error structure.
1009  *
1010  * @return
1011  *   0 on success, a negative errno value otherwise and rte_errno is set.
1012  */
1013 int
1014 mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1015                               uint64_t action_flags,
1016                               struct rte_eth_dev *dev,
1017                               const struct rte_flow_attr *attr,
1018                               uint64_t item_flags,
1019                               struct rte_flow_error *error)
1020 {
1021         struct mlx5_priv *priv = dev->data->dev_private;
1022         const struct rte_flow_action_rss *rss = action->conf;
1023         int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1024         unsigned int i;
1025
1026         if (action_flags & MLX5_FLOW_FATE_ACTIONS)
1027                 return rte_flow_error_set(error, EINVAL,
1028                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1029                                           "can't have 2 fate actions"
1030                                           " in same flow");
1031         if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT &&
1032             rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ)
1033                 return rte_flow_error_set(error, ENOTSUP,
1034                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1035                                           &rss->func,
1036                                           "RSS hash function not supported");
1037 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1038         if (rss->level > 2)
1039 #else
1040         if (rss->level > 1)
1041 #endif
1042                 return rte_flow_error_set(error, ENOTSUP,
1043                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1044                                           &rss->level,
1045                                           "tunnel RSS is not supported");
1046         /* allow RSS key_len 0 in case of NULL (default) RSS key. */
1047         if (rss->key_len == 0 && rss->key != NULL)
1048                 return rte_flow_error_set(error, ENOTSUP,
1049                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1050                                           &rss->key_len,
1051                                           "RSS hash key length 0");
1052         if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN)
1053                 return rte_flow_error_set(error, ENOTSUP,
1054                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1055                                           &rss->key_len,
1056                                           "RSS hash key too small");
1057         if (rss->key_len > MLX5_RSS_HASH_KEY_LEN)
1058                 return rte_flow_error_set(error, ENOTSUP,
1059                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1060                                           &rss->key_len,
1061                                           "RSS hash key too large");
1062         if (rss->queue_num > priv->config.ind_table_max_size)
1063                 return rte_flow_error_set(error, ENOTSUP,
1064                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1065                                           &rss->queue_num,
1066                                           "number of queues too large");
1067         if (rss->types & MLX5_RSS_HF_MASK)
1068                 return rte_flow_error_set(error, ENOTSUP,
1069                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1070                                           &rss->types,
1071                                           "some RSS protocols are not"
1072                                           " supported");
1073         if (!priv->rxqs_n)
1074                 return rte_flow_error_set(error, EINVAL,
1075                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1076                                           NULL, "No Rx queues configured");
1077         if (!rss->queue_num)
1078                 return rte_flow_error_set(error, EINVAL,
1079                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1080                                           NULL, "No queues configured");
1081         for (i = 0; i != rss->queue_num; ++i) {
1082                 if (!(*priv->rxqs)[rss->queue[i]])
1083                         return rte_flow_error_set
1084                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1085                                  &rss->queue[i], "queue is not configured");
1086         }
1087         if (attr->egress)
1088                 return rte_flow_error_set(error, ENOTSUP,
1089                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,
1090                                           "rss action not supported for "
1091                                           "egress");
1092         if (rss->level > 1 &&  !tunnel)
1093                 return rte_flow_error_set(error, EINVAL,
1094                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL,
1095                                           "inner RSS is not supported for "
1096                                           "non-tunnel flows");
1097         return 0;
1098 }
1099
1100 /*
1101  * Validate the count action.
1102  *
1103  * @param[in] dev
1104  *   Pointer to the Ethernet device structure.
1105  * @param[in] attr
1106  *   Attributes of flow that includes this action.
1107  * @param[out] error
1108  *   Pointer to error structure.
1109  *
1110  * @return
1111  *   0 on success, a negative errno value otherwise and rte_errno is set.
1112  */
1113 int
1114 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused,
1115                                 const struct rte_flow_attr *attr,
1116                                 struct rte_flow_error *error)
1117 {
1118         if (attr->egress)
1119                 return rte_flow_error_set(error, ENOTSUP,
1120                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,
1121                                           "count action not supported for "
1122                                           "egress");
1123         return 0;
1124 }
1125
1126 /**
1127  * Verify the @p attributes will be correctly understood by the NIC and store
1128  * them in the @p flow if everything is correct.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the Ethernet device structure.
1132  * @param[in] attributes
1133  *   Pointer to flow attributes
1134  * @param[out] error
1135  *   Pointer to error structure.
1136  *
1137  * @return
1138  *   0 on success, a negative errno value otherwise and rte_errno is set.
1139  */
1140 int
1141 mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1142                               const struct rte_flow_attr *attributes,
1143                               struct rte_flow_error *error)
1144 {
1145         struct mlx5_priv *priv = dev->data->dev_private;
1146         uint32_t priority_max = priv->config.flow_prio - 1;
1147
1148         if (attributes->group)
1149                 return rte_flow_error_set(error, ENOTSUP,
1150                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1151                                           NULL, "groups is not supported");
1152         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
1153             attributes->priority >= priority_max)
1154                 return rte_flow_error_set(error, ENOTSUP,
1155                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1156                                           NULL, "priority out of range");
1157         if (attributes->egress)
1158                 return rte_flow_error_set(error, ENOTSUP,
1159                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,
1160                                           "egress is not supported");
1161         if (attributes->transfer && !priv->config.dv_esw_en)
1162                 return rte_flow_error_set(error, ENOTSUP,
1163                                           RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
1164                                           NULL, "transfer is not supported");
1165         if (!attributes->ingress)
1166                 return rte_flow_error_set(error, EINVAL,
1167                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1168                                           NULL,
1169                                           "ingress attribute is mandatory");
1170         return 0;
1171 }
1172
1173 /**
1174  * Validate ICMP6 item.
1175  *
1176  * @param[in] item
1177  *   Item specification.
1178  * @param[in] item_flags
1179  *   Bit-fields that holds the items detected until now.
1180  * @param[out] error
1181  *   Pointer to error structure.
1182  *
1183  * @return
1184  *   0 on success, a negative errno value otherwise and rte_errno is set.
1185  */
1186 int
1187 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1188                                uint64_t item_flags,
1189                                uint8_t target_protocol,
1190                                struct rte_flow_error *error)
1191 {
1192         const struct rte_flow_item_icmp6 *mask = item->mask;
1193         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1194         const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
1195                                       MLX5_FLOW_LAYER_OUTER_L3_IPV6;
1196         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1197                                       MLX5_FLOW_LAYER_OUTER_L4;
1198         int ret;
1199
1200         if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6)
1201                 return rte_flow_error_set(error, EINVAL,
1202                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1203                                           "protocol filtering not compatible"
1204                                           " with ICMP6 layer");
1205         if (!(item_flags & l3m))
1206                 return rte_flow_error_set(error, EINVAL,
1207                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1208                                           "IPv6 is mandatory to filter on"
1209                                           " ICMP6");
1210         if (item_flags & l4m)
1211                 return rte_flow_error_set(error, EINVAL,
1212                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1213                                           "multiple L4 layers not supported");
1214         if (!mask)
1215                 mask = &rte_flow_item_icmp6_mask;
1216         ret = mlx5_flow_item_acceptable
1217                 (item, (const uint8_t *)mask,
1218                  (const uint8_t *)&rte_flow_item_icmp6_mask,
1219                  sizeof(struct rte_flow_item_icmp6), error);
1220         if (ret < 0)
1221                 return ret;
1222         return 0;
1223 }
1224
1225 /**
1226  * Validate ICMP item.
1227  *
1228  * @param[in] item
1229  *   Item specification.
1230  * @param[in] item_flags
1231  *   Bit-fields that holds the items detected until now.
1232  * @param[out] error
1233  *   Pointer to error structure.
1234  *
1235  * @return
1236  *   0 on success, a negative errno value otherwise and rte_errno is set.
1237  */
1238 int
1239 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1240                              uint64_t item_flags,
1241                              uint8_t target_protocol,
1242                              struct rte_flow_error *error)
1243 {
1244         const struct rte_flow_item_icmp *mask = item->mask;
1245         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1246         const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
1247                                       MLX5_FLOW_LAYER_OUTER_L3_IPV4;
1248         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1249                                       MLX5_FLOW_LAYER_OUTER_L4;
1250         int ret;
1251
1252         if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP)
1253                 return rte_flow_error_set(error, EINVAL,
1254                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1255                                           "protocol filtering not compatible"
1256                                           " with ICMP layer");
1257         if (!(item_flags & l3m))
1258                 return rte_flow_error_set(error, EINVAL,
1259                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1260                                           "IPv4 is mandatory to filter"
1261                                           " on ICMP");
1262         if (item_flags & l4m)
1263                 return rte_flow_error_set(error, EINVAL,
1264                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1265                                           "multiple L4 layers not supported");
1266         if (!mask)
1267                 mask = &rte_flow_item_icmp_mask;
1268         ret = mlx5_flow_item_acceptable
1269                 (item, (const uint8_t *)mask,
1270                  (const uint8_t *)&rte_flow_item_icmp_mask,
1271                  sizeof(struct rte_flow_item_icmp), error);
1272         if (ret < 0)
1273                 return ret;
1274         return 0;
1275 }
1276
1277 /**
1278  * Validate Ethernet item.
1279  *
1280  * @param[in] item
1281  *   Item specification.
1282  * @param[in] item_flags
1283  *   Bit-fields that holds the items detected until now.
1284  * @param[out] error
1285  *   Pointer to error structure.
1286  *
1287  * @return
1288  *   0 on success, a negative errno value otherwise and rte_errno is set.
1289  */
1290 int
1291 mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1292                             uint64_t item_flags,
1293                             struct rte_flow_error *error)
1294 {
1295         const struct rte_flow_item_eth *mask = item->mask;
1296         const struct rte_flow_item_eth nic_mask = {
1297                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1298                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1299                 .type = RTE_BE16(0xffff),
1300         };
1301         int ret;
1302         int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1303         const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
1304                                        MLX5_FLOW_LAYER_OUTER_L2;
1305
1306         if (item_flags & ethm)
1307                 return rte_flow_error_set(error, ENOTSUP,
1308                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1309                                           "multiple L2 layers not supported");
1310         if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) ||
1311             (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3)))
1312                 return rte_flow_error_set(error, EINVAL,
1313                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1314                                           "L2 layer should not follow "
1315                                           "L3 layers");
1316         if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) ||
1317             (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN)))
1318                 return rte_flow_error_set(error, EINVAL,
1319                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1320                                           "L2 layer should not follow VLAN");
1321         if (!mask)
1322                 mask = &rte_flow_item_eth_mask;
1323         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1324                                         (const uint8_t *)&nic_mask,
1325                                         sizeof(struct rte_flow_item_eth),
1326                                         error);
1327         return ret;
1328 }
1329
1330 /**
1331  * Validate VLAN item.
1332  *
1333  * @param[in] item
1334  *   Item specification.
1335  * @param[in] item_flags
1336  *   Bit-fields that holds the items detected until now.
1337  * @param[in] dev
1338  *   Ethernet device flow is being created on.
1339  * @param[out] error
1340  *   Pointer to error structure.
1341  *
1342  * @return
1343  *   0 on success, a negative errno value otherwise and rte_errno is set.
1344  */
1345 int
1346 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1347                              uint64_t item_flags,
1348                              struct rte_eth_dev *dev,
1349                              struct rte_flow_error *error)
1350 {
1351         const struct rte_flow_item_vlan *spec = item->spec;
1352         const struct rte_flow_item_vlan *mask = item->mask;
1353         const struct rte_flow_item_vlan nic_mask = {
1354                 .tci = RTE_BE16(UINT16_MAX),
1355                 .inner_type = RTE_BE16(UINT16_MAX),
1356         };
1357         uint16_t vlan_tag = 0;
1358         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1359         int ret;
1360         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1361                                         MLX5_FLOW_LAYER_INNER_L4) :
1362                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1363                                         MLX5_FLOW_LAYER_OUTER_L4);
1364         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1365                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1366
1367         if (item_flags & vlanm)
1368                 return rte_flow_error_set(error, EINVAL,
1369                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1370                                           "multiple VLAN layers not supported");
1371         else if ((item_flags & l34m) != 0)
1372                 return rte_flow_error_set(error, EINVAL,
1373                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1374                                           "VLAN cannot follow L3/L4 layer");
1375         if (!mask)
1376                 mask = &rte_flow_item_vlan_mask;
1377         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1378                                         (const uint8_t *)&nic_mask,
1379                                         sizeof(struct rte_flow_item_vlan),
1380                                         error);
1381         if (ret)
1382                 return ret;
1383         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1384                 struct mlx5_priv *priv = dev->data->dev_private;
1385
1386                 if (priv->vmwa_context) {
1387                         /*
1388                          * Non-NULL context means we have a virtual machine
1389                          * and SR-IOV enabled, we have to create VLAN interface
1390                          * to make hypervisor to setup E-Switch vport
1391                          * context correctly. We avoid creating the multiple
1392                          * VLAN interfaces, so we cannot support VLAN tag mask.
1393                          */
1394                         return rte_flow_error_set(error, EINVAL,
1395                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1396                                                   item,
1397                                                   "VLAN tag mask is not"
1398                                                   " supported in virtual"
1399                                                   " environment");
1400                 }
1401         }
1402         if (spec) {
1403                 vlan_tag = spec->tci;
1404                 vlan_tag &= mask->tci;
1405         }
1406         /*
1407          * From verbs perspective an empty VLAN is equivalent
1408          * to a packet without VLAN layer.
1409          */
1410         if (!vlan_tag)
1411                 return rte_flow_error_set(error, EINVAL,
1412                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1413                                           item->spec,
1414                                           "VLAN cannot be empty");
1415         return 0;
1416 }
1417
1418 /**
1419  * Validate IPV4 item.
1420  *
1421  * @param[in] item
1422  *   Item specification.
1423  * @param[in] item_flags
1424  *   Bit-fields that holds the items detected until now.
1425  * @param[in] acc_mask
1426  *   Acceptable mask, if NULL default internal default mask
1427  *   will be used to check whether item fields are supported.
1428  * @param[out] error
1429  *   Pointer to error structure.
1430  *
1431  * @return
1432  *   0 on success, a negative errno value otherwise and rte_errno is set.
1433  */
1434 int
1435 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1436                              uint64_t item_flags,
1437                              uint64_t last_item,
1438                              uint16_t ether_type,
1439                              const struct rte_flow_item_ipv4 *acc_mask,
1440                              struct rte_flow_error *error)
1441 {
1442         const struct rte_flow_item_ipv4 *mask = item->mask;
1443         const struct rte_flow_item_ipv4 *spec = item->spec;
1444         const struct rte_flow_item_ipv4 nic_mask = {
1445                 .hdr = {
1446                         .src_addr = RTE_BE32(0xffffffff),
1447                         .dst_addr = RTE_BE32(0xffffffff),
1448                         .type_of_service = 0xff,
1449                         .next_proto_id = 0xff,
1450                 },
1451         };
1452         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1453         const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 :
1454                                       MLX5_FLOW_LAYER_OUTER_L3;
1455         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1456                                       MLX5_FLOW_LAYER_OUTER_L4;
1457         int ret;
1458         uint8_t next_proto = 0xFF;
1459         const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 |
1460                                   MLX5_FLOW_LAYER_OUTER_VLAN |
1461                                   MLX5_FLOW_LAYER_INNER_VLAN);
1462
1463         if ((last_item & l2_vlan) && ether_type &&
1464             ether_type != RTE_ETHER_TYPE_IPV4)
1465                 return rte_flow_error_set(error, EINVAL,
1466                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1467                                           "IPv4 cannot follow L2/VLAN layer "
1468                                           "which ether type is not IPv4");
1469         if (item_flags & MLX5_FLOW_LAYER_IPIP) {
1470                 if (mask && spec)
1471                         next_proto = mask->hdr.next_proto_id &
1472                                      spec->hdr.next_proto_id;
1473                 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6)
1474                         return rte_flow_error_set(error, EINVAL,
1475                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1476                                                   item,
1477                                                   "multiple tunnel "
1478                                                   "not supported");
1479         }
1480         if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP)
1481                 return rte_flow_error_set(error, EINVAL,
1482                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1483                                           "wrong tunnel type - IPv6 specified "
1484                                           "but IPv4 item provided");
1485         if (item_flags & l3m)
1486                 return rte_flow_error_set(error, ENOTSUP,
1487                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1488                                           "multiple L3 layers not supported");
1489         else if (item_flags & l4m)
1490                 return rte_flow_error_set(error, EINVAL,
1491                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1492                                           "L3 cannot follow an L4 layer.");
1493         else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) &&
1494                   !(item_flags & MLX5_FLOW_LAYER_INNER_L2))
1495                 return rte_flow_error_set(error, EINVAL,
1496                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1497                                           "L3 cannot follow an NVGRE layer.");
1498         if (!mask)
1499                 mask = &rte_flow_item_ipv4_mask;
1500         else if (mask->hdr.next_proto_id != 0 &&
1501                  mask->hdr.next_proto_id != 0xff)
1502                 return rte_flow_error_set(error, EINVAL,
1503                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask,
1504                                           "partial mask is not supported"
1505                                           " for protocol");
1506         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1507                                         acc_mask ? (const uint8_t *)acc_mask
1508                                                  : (const uint8_t *)&nic_mask,
1509                                         sizeof(struct rte_flow_item_ipv4),
1510                                         error);
1511         if (ret < 0)
1512                 return ret;
1513         return 0;
1514 }
1515
1516 /**
1517  * Validate IPV6 item.
1518  *
1519  * @param[in] item
1520  *   Item specification.
1521  * @param[in] item_flags
1522  *   Bit-fields that holds the items detected until now.
1523  * @param[in] acc_mask
1524  *   Acceptable mask, if NULL default internal default mask
1525  *   will be used to check whether item fields are supported.
1526  * @param[out] error
1527  *   Pointer to error structure.
1528  *
1529  * @return
1530  *   0 on success, a negative errno value otherwise and rte_errno is set.
1531  */
1532 int
1533 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1534                              uint64_t item_flags,
1535                              uint64_t last_item,
1536                              uint16_t ether_type,
1537                              const struct rte_flow_item_ipv6 *acc_mask,
1538                              struct rte_flow_error *error)
1539 {
1540         const struct rte_flow_item_ipv6 *mask = item->mask;
1541         const struct rte_flow_item_ipv6 *spec = item->spec;
1542         const struct rte_flow_item_ipv6 nic_mask = {
1543                 .hdr = {
1544                         .src_addr =
1545                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
1546                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
1547                         .dst_addr =
1548                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
1549                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
1550                         .vtc_flow = RTE_BE32(0xffffffff),
1551                         .proto = 0xff,
1552                         .hop_limits = 0xff,
1553                 },
1554         };
1555         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1556         const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 :
1557                                       MLX5_FLOW_LAYER_OUTER_L3;
1558         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1559                                       MLX5_FLOW_LAYER_OUTER_L4;
1560         int ret;
1561         uint8_t next_proto = 0xFF;
1562         const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 |
1563                                   MLX5_FLOW_LAYER_OUTER_VLAN |
1564                                   MLX5_FLOW_LAYER_INNER_VLAN);
1565
1566         if ((last_item & l2_vlan) && ether_type &&
1567             ether_type != RTE_ETHER_TYPE_IPV6)
1568                 return rte_flow_error_set(error, EINVAL,
1569                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1570                                           "IPv6 cannot follow L2/VLAN layer "
1571                                           "which ether type is not IPv6");
1572         if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) {
1573                 if (mask && spec)
1574                         next_proto = mask->hdr.proto & spec->hdr.proto;
1575                 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6)
1576                         return rte_flow_error_set(error, EINVAL,
1577                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1578                                                   item,
1579                                                   "multiple tunnel "
1580                                                   "not supported");
1581         }
1582         if (item_flags & MLX5_FLOW_LAYER_IPIP)
1583                 return rte_flow_error_set(error, EINVAL,
1584                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1585                                           "wrong tunnel type - IPv4 specified "
1586                                           "but IPv6 item provided");
1587         if (item_flags & l3m)
1588                 return rte_flow_error_set(error, ENOTSUP,
1589                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1590                                           "multiple L3 layers not supported");
1591         else if (item_flags & l4m)
1592                 return rte_flow_error_set(error, EINVAL,
1593                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1594                                           "L3 cannot follow an L4 layer.");
1595         else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) &&
1596                   !(item_flags & MLX5_FLOW_LAYER_INNER_L2))
1597                 return rte_flow_error_set(error, EINVAL,
1598                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1599                                           "L3 cannot follow an NVGRE layer.");
1600         if (!mask)
1601                 mask = &rte_flow_item_ipv6_mask;
1602         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1603                                         acc_mask ? (const uint8_t *)acc_mask
1604                                                  : (const uint8_t *)&nic_mask,
1605                                         sizeof(struct rte_flow_item_ipv6),
1606                                         error);
1607         if (ret < 0)
1608                 return ret;
1609         return 0;
1610 }
1611
1612 /**
1613  * Validate UDP item.
1614  *
1615  * @param[in] item
1616  *   Item specification.
1617  * @param[in] item_flags
1618  *   Bit-fields that holds the items detected until now.
1619  * @param[in] target_protocol
1620  *   The next protocol in the previous item.
1621  * @param[in] flow_mask
1622  *   mlx5 flow-specific (DV, verbs, etc.) supported header fields mask.
1623  * @param[out] error
1624  *   Pointer to error structure.
1625  *
1626  * @return
1627  *   0 on success, a negative errno value otherwise and rte_errno is set.
1628  */
1629 int
1630 mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1631                             uint64_t item_flags,
1632                             uint8_t target_protocol,
1633                             struct rte_flow_error *error)
1634 {
1635         const struct rte_flow_item_udp *mask = item->mask;
1636         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1637         const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 :
1638                                       MLX5_FLOW_LAYER_OUTER_L3;
1639         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1640                                       MLX5_FLOW_LAYER_OUTER_L4;
1641         int ret;
1642
1643         if (target_protocol != 0xff && target_protocol != IPPROTO_UDP)
1644                 return rte_flow_error_set(error, EINVAL,
1645                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1646                                           "protocol filtering not compatible"
1647                                           " with UDP layer");
1648         if (!(item_flags & l3m))
1649                 return rte_flow_error_set(error, EINVAL,
1650                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1651                                           "L3 is mandatory to filter on L4");
1652         if (item_flags & l4m)
1653                 return rte_flow_error_set(error, EINVAL,
1654                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1655                                           "multiple L4 layers not supported");
1656         if (!mask)
1657                 mask = &rte_flow_item_udp_mask;
1658         ret = mlx5_flow_item_acceptable
1659                 (item, (const uint8_t *)mask,
1660                  (const uint8_t *)&rte_flow_item_udp_mask,
1661                  sizeof(struct rte_flow_item_udp), error);
1662         if (ret < 0)
1663                 return ret;
1664         return 0;
1665 }
1666
1667 /**
1668  * Validate TCP item.
1669  *
1670  * @param[in] item
1671  *   Item specification.
1672  * @param[in] item_flags
1673  *   Bit-fields that holds the items detected until now.
1674  * @param[in] target_protocol
1675  *   The next protocol in the previous item.
1676  * @param[out] error
1677  *   Pointer to error structure.
1678  *
1679  * @return
1680  *   0 on success, a negative errno value otherwise and rte_errno is set.
1681  */
1682 int
1683 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1684                             uint64_t item_flags,
1685                             uint8_t target_protocol,
1686                             const struct rte_flow_item_tcp *flow_mask,
1687                             struct rte_flow_error *error)
1688 {
1689         const struct rte_flow_item_tcp *mask = item->mask;
1690         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1691         const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 :
1692                                       MLX5_FLOW_LAYER_OUTER_L3;
1693         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1694                                       MLX5_FLOW_LAYER_OUTER_L4;
1695         int ret;
1696
1697         assert(flow_mask);
1698         if (target_protocol != 0xff && target_protocol != IPPROTO_TCP)
1699                 return rte_flow_error_set(error, EINVAL,
1700                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1701                                           "protocol filtering not compatible"
1702                                           " with TCP layer");
1703         if (!(item_flags & l3m))
1704                 return rte_flow_error_set(error, EINVAL,
1705                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1706                                           "L3 is mandatory to filter on L4");
1707         if (item_flags & l4m)
1708                 return rte_flow_error_set(error, EINVAL,
1709                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1710                                           "multiple L4 layers not supported");
1711         if (!mask)
1712                 mask = &rte_flow_item_tcp_mask;
1713         ret = mlx5_flow_item_acceptable
1714                 (item, (const uint8_t *)mask,
1715                  (const uint8_t *)flow_mask,
1716                  sizeof(struct rte_flow_item_tcp), error);
1717         if (ret < 0)
1718                 return ret;
1719         return 0;
1720 }
1721
1722 /**
1723  * Validate VXLAN item.
1724  *
1725  * @param[in] item
1726  *   Item specification.
1727  * @param[in] item_flags
1728  *   Bit-fields that holds the items detected until now.
1729  * @param[in] target_protocol
1730  *   The next protocol in the previous item.
1731  * @param[out] error
1732  *   Pointer to error structure.
1733  *
1734  * @return
1735  *   0 on success, a negative errno value otherwise and rte_errno is set.
1736  */
1737 int
1738 mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1739                               uint64_t item_flags,
1740                               struct rte_flow_error *error)
1741 {
1742         const struct rte_flow_item_vxlan *spec = item->spec;
1743         const struct rte_flow_item_vxlan *mask = item->mask;
1744         int ret;
1745         union vni {
1746                 uint32_t vlan_id;
1747                 uint8_t vni[4];
1748         } id = { .vlan_id = 0, };
1749         uint32_t vlan_id = 0;
1750
1751
1752         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1753                 return rte_flow_error_set(error, ENOTSUP,
1754                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1755                                           "multiple tunnel layers not"
1756                                           " supported");
1757         /*
1758          * Verify only UDPv4 is present as defined in
1759          * https://tools.ietf.org/html/rfc7348
1760          */
1761         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1762                 return rte_flow_error_set(error, EINVAL,
1763                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1764                                           "no outer UDP layer found");
1765         if (!mask)
1766                 mask = &rte_flow_item_vxlan_mask;
1767         ret = mlx5_flow_item_acceptable
1768                 (item, (const uint8_t *)mask,
1769                  (const uint8_t *)&rte_flow_item_vxlan_mask,
1770                  sizeof(struct rte_flow_item_vxlan),
1771                  error);
1772         if (ret < 0)
1773                 return ret;
1774         if (spec) {
1775                 memcpy(&id.vni[1], spec->vni, 3);
1776                 vlan_id = id.vlan_id;
1777                 memcpy(&id.vni[1], mask->vni, 3);
1778                 vlan_id &= id.vlan_id;
1779         }
1780         /*
1781          * Tunnel id 0 is equivalent as not adding a VXLAN layer, if
1782          * only this layer is defined in the Verbs specification it is
1783          * interpreted as wildcard and all packets will match this
1784          * rule, if it follows a full stack layer (ex: eth / ipv4 /
1785          * udp), all packets matching the layers before will also
1786          * match this rule.  To avoid such situation, VNI 0 is
1787          * currently refused.
1788          */
1789         if (!vlan_id)
1790                 return rte_flow_error_set(error, ENOTSUP,
1791                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1792                                           "VXLAN vni cannot be 0");
1793         if (!(item_flags & MLX5_FLOW_LAYER_OUTER))
1794                 return rte_flow_error_set(error, ENOTSUP,
1795                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1796                                           "VXLAN tunnel must be fully defined");
1797         return 0;
1798 }
1799
1800 /**
1801  * Validate VXLAN_GPE item.
1802  *
1803  * @param[in] item
1804  *   Item specification.
1805  * @param[in] item_flags
1806  *   Bit-fields that holds the items detected until now.
1807  * @param[in] priv
1808  *   Pointer to the private data structure.
1809  * @param[in] target_protocol
1810  *   The next protocol in the previous item.
1811  * @param[out] error
1812  *   Pointer to error structure.
1813  *
1814  * @return
1815  *   0 on success, a negative errno value otherwise and rte_errno is set.
1816  */
1817 int
1818 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1819                                   uint64_t item_flags,
1820                                   struct rte_eth_dev *dev,
1821                                   struct rte_flow_error *error)
1822 {
1823         struct mlx5_priv *priv = dev->data->dev_private;
1824         const struct rte_flow_item_vxlan_gpe *spec = item->spec;
1825         const struct rte_flow_item_vxlan_gpe *mask = item->mask;
1826         int ret;
1827         union vni {
1828                 uint32_t vlan_id;
1829                 uint8_t vni[4];
1830         } id = { .vlan_id = 0, };
1831         uint32_t vlan_id = 0;
1832
1833         if (!priv->config.l3_vxlan_en)
1834                 return rte_flow_error_set(error, ENOTSUP,
1835                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1836                                           "L3 VXLAN is not enabled by device"
1837                                           " parameter and/or not configured in"
1838                                           " firmware");
1839         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1840                 return rte_flow_error_set(error, ENOTSUP,
1841                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1842                                           "multiple tunnel layers not"
1843                                           " supported");
1844         /*
1845          * Verify only UDPv4 is present as defined in
1846          * https://tools.ietf.org/html/rfc7348
1847          */
1848         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1849                 return rte_flow_error_set(error, EINVAL,
1850                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1851                                           "no outer UDP layer found");
1852         if (!mask)
1853                 mask = &rte_flow_item_vxlan_gpe_mask;
1854         ret = mlx5_flow_item_acceptable
1855                 (item, (const uint8_t *)mask,
1856                  (const uint8_t *)&rte_flow_item_vxlan_gpe_mask,
1857                  sizeof(struct rte_flow_item_vxlan_gpe),
1858                  error);
1859         if (ret < 0)
1860                 return ret;
1861         if (spec) {
1862                 if (spec->protocol)
1863                         return rte_flow_error_set(error, ENOTSUP,
1864                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1865                                                   item,
1866                                                   "VxLAN-GPE protocol"
1867                                                   " not supported");
1868                 memcpy(&id.vni[1], spec->vni, 3);
1869                 vlan_id = id.vlan_id;
1870                 memcpy(&id.vni[1], mask->vni, 3);
1871                 vlan_id &= id.vlan_id;
1872         }
1873         /*
1874          * Tunnel id 0 is equivalent as not adding a VXLAN layer, if only this
1875          * layer is defined in the Verbs specification it is interpreted as
1876          * wildcard and all packets will match this rule, if it follows a full
1877          * stack layer (ex: eth / ipv4 / udp), all packets matching the layers
1878          * before will also match this rule.  To avoid such situation, VNI 0
1879          * is currently refused.
1880          */
1881         if (!vlan_id)
1882                 return rte_flow_error_set(error, ENOTSUP,
1883                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1884                                           "VXLAN-GPE vni cannot be 0");
1885         if (!(item_flags & MLX5_FLOW_LAYER_OUTER))
1886                 return rte_flow_error_set(error, ENOTSUP,
1887                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1888                                           "VXLAN-GPE tunnel must be fully"
1889                                           " defined");
1890         return 0;
1891 }
1892 /**
1893  * Validate GRE Key item.
1894  *
1895  * @param[in] item
1896  *   Item specification.
1897  * @param[in] item_flags
1898  *   Bit flags to mark detected items.
1899  * @param[in] gre_item
1900  *   Pointer to gre_item
1901  * @param[out] error
1902  *   Pointer to error structure.
1903  *
1904  * @return
1905  *   0 on success, a negative errno value otherwise and rte_errno is set.
1906  */
1907 int
1908 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1909                                 uint64_t item_flags,
1910                                 const struct rte_flow_item *gre_item,
1911                                 struct rte_flow_error *error)
1912 {
1913         const rte_be32_t *mask = item->mask;
1914         int ret = 0;
1915         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
1916         const struct rte_flow_item_gre *gre_spec = gre_item->spec;
1917         const struct rte_flow_item_gre *gre_mask = gre_item->mask;
1918
1919         if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
1920                 return rte_flow_error_set(error, ENOTSUP,
1921                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1922                                           "Multiple GRE key not support");
1923         if (!(item_flags & MLX5_FLOW_LAYER_GRE))
1924                 return rte_flow_error_set(error, ENOTSUP,
1925                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1926                                           "No preceding GRE header");
1927         if (item_flags & MLX5_FLOW_LAYER_INNER)
1928                 return rte_flow_error_set(error, ENOTSUP,
1929                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1930                                           "GRE key following a wrong item");
1931         if (!gre_mask)
1932                 gre_mask = &rte_flow_item_gre_mask;
1933         if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
1934                          !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
1935                 return rte_flow_error_set(error, EINVAL,
1936                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1937                                           "Key bit must be on");
1938
1939         if (!mask)
1940                 mask = &gre_key_default_mask;
1941         ret = mlx5_flow_item_acceptable
1942                 (item, (const uint8_t *)mask,
1943                  (const uint8_t *)&gre_key_default_mask,
1944                  sizeof(rte_be32_t), error);
1945         return ret;
1946 }
1947
1948 /**
1949  * Validate GRE item.
1950  *
1951  * @param[in] item
1952  *   Item specification.
1953  * @param[in] item_flags
1954  *   Bit flags to mark detected items.
1955  * @param[in] target_protocol
1956  *   The next protocol in the previous item.
1957  * @param[out] error
1958  *   Pointer to error structure.
1959  *
1960  * @return
1961  *   0 on success, a negative errno value otherwise and rte_errno is set.
1962  */
1963 int
1964 mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1965                             uint64_t item_flags,
1966                             uint8_t target_protocol,
1967                             struct rte_flow_error *error)
1968 {
1969         const struct rte_flow_item_gre *spec __rte_unused = item->spec;
1970         const struct rte_flow_item_gre *mask = item->mask;
1971         int ret;
1972         const struct rte_flow_item_gre nic_mask = {
1973                 .c_rsvd0_ver = RTE_BE16(0xB000),
1974                 .protocol = RTE_BE16(UINT16_MAX),
1975         };
1976
1977         if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
1978                 return rte_flow_error_set(error, EINVAL,
1979                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1980                                           "protocol filtering not compatible"
1981                                           " with this GRE layer");
1982         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1983                 return rte_flow_error_set(error, ENOTSUP,
1984                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1985                                           "multiple tunnel layers not"
1986                                           " supported");
1987         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3))
1988                 return rte_flow_error_set(error, ENOTSUP,
1989                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1990                                           "L3 Layer is missing");
1991         if (!mask)
1992                 mask = &rte_flow_item_gre_mask;
1993         ret = mlx5_flow_item_acceptable
1994                 (item, (const uint8_t *)mask,
1995                  (const uint8_t *)&nic_mask,
1996                  sizeof(struct rte_flow_item_gre), error);
1997         if (ret < 0)
1998                 return ret;
1999 #ifndef HAVE_MLX5DV_DR
2000 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
2001         if (spec && (spec->protocol & mask->protocol))
2002                 return rte_flow_error_set(error, ENOTSUP,
2003                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2004                                           "without MPLS support the"
2005                                           " specification cannot be used for"
2006                                           " filtering");
2007 #endif
2008 #endif
2009         return 0;
2010 }
2011
2012 /**
2013  * Validate Geneve item.
2014  *
2015  * @param[in] item
2016  *   Item specification.
2017  * @param[in] itemFlags
2018  *   Bit-fields that holds the items detected until now.
2019  * @param[in] enPriv
2020  *   Pointer to the private data structure.
2021  * @param[out] error
2022  *   Pointer to error structure.
2023  *
2024  * @return
2025  *   0 on success, a negative errno value otherwise and rte_errno is set.
2026  */
2027
2028 int
2029 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
2030                                uint64_t item_flags,
2031                                struct rte_eth_dev *dev,
2032                                struct rte_flow_error *error)
2033 {
2034         struct mlx5_priv *priv = dev->data->dev_private;
2035         const struct rte_flow_item_geneve *spec = item->spec;
2036         const struct rte_flow_item_geneve *mask = item->mask;
2037         int ret;
2038         uint16_t gbhdr;
2039         uint8_t opt_len = priv->config.hca_attr.geneve_max_opt_len ?
2040                           MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0;
2041         const struct rte_flow_item_geneve nic_mask = {
2042                 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80),
2043                 .vni = "\xff\xff\xff",
2044                 .protocol = RTE_BE16(UINT16_MAX),
2045         };
2046
2047         if (!(priv->config.hca_attr.flex_parser_protocols &
2048               MLX5_HCA_FLEX_GENEVE_ENABLED) ||
2049             !priv->config.hca_attr.tunnel_stateless_geneve_rx)
2050                 return rte_flow_error_set(error, ENOTSUP,
2051                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2052                                           "L3 Geneve is not enabled by device"
2053                                           " parameter and/or not configured in"
2054                                           " firmware");
2055         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2056                 return rte_flow_error_set(error, ENOTSUP,
2057                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2058                                           "multiple tunnel layers not"
2059                                           " supported");
2060         /*
2061          * Verify only UDPv4 is present as defined in
2062          * https://tools.ietf.org/html/rfc7348
2063          */
2064         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2065                 return rte_flow_error_set(error, EINVAL,
2066                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2067                                           "no outer UDP layer found");
2068         if (!mask)
2069                 mask = &rte_flow_item_geneve_mask;
2070         ret = mlx5_flow_item_acceptable
2071                                   (item, (const uint8_t *)mask,
2072                                    (const uint8_t *)&nic_mask,
2073                                    sizeof(struct rte_flow_item_geneve), error);
2074         if (ret)
2075                 return ret;
2076         if (spec) {
2077                 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0);
2078                 if (MLX5_GENEVE_VER_VAL(gbhdr) ||
2079                      MLX5_GENEVE_CRITO_VAL(gbhdr) ||
2080                      MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1)
2081                         return rte_flow_error_set(error, ENOTSUP,
2082                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2083                                                   item,
2084                                                   "Geneve protocol unsupported"
2085                                                   " fields are being used");
2086                 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len)
2087                         return rte_flow_error_set
2088                                         (error, ENOTSUP,
2089                                          RTE_FLOW_ERROR_TYPE_ITEM,
2090                                          item,
2091                                          "Unsupported Geneve options length");
2092         }
2093         if (!(item_flags & MLX5_FLOW_LAYER_OUTER))
2094                 return rte_flow_error_set
2095                                     (error, ENOTSUP,
2096                                      RTE_FLOW_ERROR_TYPE_ITEM, item,
2097                                      "Geneve tunnel must be fully defined");
2098         return 0;
2099 }
2100
2101 /**
2102  * Validate MPLS item.
2103  *
2104  * @param[in] dev
2105  *   Pointer to the rte_eth_dev structure.
2106  * @param[in] item
2107  *   Item specification.
2108  * @param[in] item_flags
2109  *   Bit-fields that holds the items detected until now.
2110  * @param[in] prev_layer
2111  *   The protocol layer indicated in previous item.
2112  * @param[out] error
2113  *   Pointer to error structure.
2114  *
2115  * @return
2116  *   0 on success, a negative errno value otherwise and rte_errno is set.
2117  */
2118 int
2119 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused,
2120                              const struct rte_flow_item *item __rte_unused,
2121                              uint64_t item_flags __rte_unused,
2122                              uint64_t prev_layer __rte_unused,
2123                              struct rte_flow_error *error)
2124 {
2125 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2126         const struct rte_flow_item_mpls *mask = item->mask;
2127         struct mlx5_priv *priv = dev->data->dev_private;
2128         int ret;
2129
2130         if (!priv->config.mpls_en)
2131                 return rte_flow_error_set(error, ENOTSUP,
2132                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2133                                           "MPLS not supported or"
2134                                           " disabled in firmware"
2135                                           " configuration.");
2136         /* MPLS over IP, UDP, GRE is allowed */
2137         if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L3 |
2138                             MLX5_FLOW_LAYER_OUTER_L4_UDP |
2139                             MLX5_FLOW_LAYER_GRE)))
2140                 return rte_flow_error_set(error, EINVAL,
2141                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2142                                           "protocol filtering not compatible"
2143                                           " with MPLS layer");
2144         /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */
2145         if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) &&
2146             !(item_flags & MLX5_FLOW_LAYER_GRE))
2147                 return rte_flow_error_set(error, ENOTSUP,
2148                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2149                                           "multiple tunnel layers not"
2150                                           " supported");
2151         if (!mask)
2152                 mask = &rte_flow_item_mpls_mask;
2153         ret = mlx5_flow_item_acceptable
2154                 (item, (const uint8_t *)mask,
2155                  (const uint8_t *)&rte_flow_item_mpls_mask,
2156                  sizeof(struct rte_flow_item_mpls), error);
2157         if (ret < 0)
2158                 return ret;
2159         return 0;
2160 #endif
2161         return rte_flow_error_set(error, ENOTSUP,
2162                                   RTE_FLOW_ERROR_TYPE_ITEM, item,
2163                                   "MPLS is not supported by Verbs, please"
2164                                   " update.");
2165 }
2166
2167 /**
2168  * Validate NVGRE item.
2169  *
2170  * @param[in] item
2171  *   Item specification.
2172  * @param[in] item_flags
2173  *   Bit flags to mark detected items.
2174  * @param[in] target_protocol
2175  *   The next protocol in the previous item.
2176  * @param[out] error
2177  *   Pointer to error structure.
2178  *
2179  * @return
2180  *   0 on success, a negative errno value otherwise and rte_errno is set.
2181  */
2182 int
2183 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
2184                               uint64_t item_flags,
2185                               uint8_t target_protocol,
2186                               struct rte_flow_error *error)
2187 {
2188         const struct rte_flow_item_nvgre *mask = item->mask;
2189         int ret;
2190
2191         if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
2192                 return rte_flow_error_set(error, EINVAL,
2193                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2194                                           "protocol filtering not compatible"
2195                                           " with this GRE layer");
2196         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2197                 return rte_flow_error_set(error, ENOTSUP,
2198                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2199                                           "multiple tunnel layers not"
2200                                           " supported");
2201         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3))
2202                 return rte_flow_error_set(error, ENOTSUP,
2203                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2204                                           "L3 Layer is missing");
2205         if (!mask)
2206                 mask = &rte_flow_item_nvgre_mask;
2207         ret = mlx5_flow_item_acceptable
2208                 (item, (const uint8_t *)mask,
2209                  (const uint8_t *)&rte_flow_item_nvgre_mask,
2210                  sizeof(struct rte_flow_item_nvgre), error);
2211         if (ret < 0)
2212                 return ret;
2213         return 0;
2214 }
2215
2216 static int
2217 flow_null_validate(struct rte_eth_dev *dev __rte_unused,
2218                    const struct rte_flow_attr *attr __rte_unused,
2219                    const struct rte_flow_item items[] __rte_unused,
2220                    const struct rte_flow_action actions[] __rte_unused,
2221                    bool external __rte_unused,
2222                    struct rte_flow_error *error)
2223 {
2224         return rte_flow_error_set(error, ENOTSUP,
2225                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL);
2226 }
2227
2228 static struct mlx5_flow *
2229 flow_null_prepare(const struct rte_flow_attr *attr __rte_unused,
2230                   const struct rte_flow_item items[] __rte_unused,
2231                   const struct rte_flow_action actions[] __rte_unused,
2232                   struct rte_flow_error *error)
2233 {
2234         rte_flow_error_set(error, ENOTSUP,
2235                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL);
2236         return NULL;
2237 }
2238
2239 static int
2240 flow_null_translate(struct rte_eth_dev *dev __rte_unused,
2241                     struct mlx5_flow *dev_flow __rte_unused,
2242                     const struct rte_flow_attr *attr __rte_unused,
2243                     const struct rte_flow_item items[] __rte_unused,
2244                     const struct rte_flow_action actions[] __rte_unused,
2245                     struct rte_flow_error *error)
2246 {
2247         return rte_flow_error_set(error, ENOTSUP,
2248                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL);
2249 }
2250
2251 static int
2252 flow_null_apply(struct rte_eth_dev *dev __rte_unused,
2253                 struct rte_flow *flow __rte_unused,
2254                 struct rte_flow_error *error)
2255 {
2256         return rte_flow_error_set(error, ENOTSUP,
2257                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL);
2258 }
2259
2260 static void
2261 flow_null_remove(struct rte_eth_dev *dev __rte_unused,
2262                  struct rte_flow *flow __rte_unused)
2263 {
2264 }
2265
2266 static void
2267 flow_null_destroy(struct rte_eth_dev *dev __rte_unused,
2268                   struct rte_flow *flow __rte_unused)
2269 {
2270 }
2271
2272 static int
2273 flow_null_query(struct rte_eth_dev *dev __rte_unused,
2274                 struct rte_flow *flow __rte_unused,
2275                 const struct rte_flow_action *actions __rte_unused,
2276                 void *data __rte_unused,
2277                 struct rte_flow_error *error)
2278 {
2279         return rte_flow_error_set(error, ENOTSUP,
2280                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL);
2281 }
2282
2283 /* Void driver to protect from null pointer reference. */
2284 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = {
2285         .validate = flow_null_validate,
2286         .prepare = flow_null_prepare,
2287         .translate = flow_null_translate,
2288         .apply = flow_null_apply,
2289         .remove = flow_null_remove,
2290         .destroy = flow_null_destroy,
2291         .query = flow_null_query,
2292 };
2293
2294 /**
2295  * Select flow driver type according to flow attributes and device
2296  * configuration.
2297  *
2298  * @param[in] dev
2299  *   Pointer to the dev structure.
2300  * @param[in] attr
2301  *   Pointer to the flow attributes.
2302  *
2303  * @return
2304  *   flow driver type, MLX5_FLOW_TYPE_MAX otherwise.
2305  */
2306 static enum mlx5_flow_drv_type
2307 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr)
2308 {
2309         struct mlx5_priv *priv = dev->data->dev_private;
2310         enum mlx5_flow_drv_type type = MLX5_FLOW_TYPE_MAX;
2311
2312         if (attr->transfer && priv->config.dv_esw_en)
2313                 type = MLX5_FLOW_TYPE_DV;
2314         if (!attr->transfer)
2315                 type = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV :
2316                                                  MLX5_FLOW_TYPE_VERBS;
2317         return type;
2318 }
2319
2320 #define flow_get_drv_ops(type) flow_drv_ops[type]
2321
2322 /**
2323  * Flow driver validation API. This abstracts calling driver specific functions.
2324  * The type of flow driver is determined according to flow attributes.
2325  *
2326  * @param[in] dev
2327  *   Pointer to the dev structure.
2328  * @param[in] attr
2329  *   Pointer to the flow attributes.
2330  * @param[in] items
2331  *   Pointer to the list of items.
2332  * @param[in] actions
2333  *   Pointer to the list of actions.
2334  * @param[in] external
2335  *   This flow rule is created by request external to PMD.
2336  * @param[out] error
2337  *   Pointer to the error structure.
2338  *
2339  * @return
2340  *   0 on success, a negative errno value otherwise and rte_errno is set.
2341  */
2342 static inline int
2343 flow_drv_validate(struct rte_eth_dev *dev,
2344                   const struct rte_flow_attr *attr,
2345                   const struct rte_flow_item items[],
2346                   const struct rte_flow_action actions[],
2347                   bool external, struct rte_flow_error *error)
2348 {
2349         const struct mlx5_flow_driver_ops *fops;
2350         enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr);
2351
2352         fops = flow_get_drv_ops(type);
2353         return fops->validate(dev, attr, items, actions, external, error);
2354 }
2355
2356 /**
2357  * Flow driver preparation API. This abstracts calling driver specific
2358  * functions. Parent flow (rte_flow) should have driver type (drv_type). It
2359  * calculates the size of memory required for device flow, allocates the memory,
2360  * initializes the device flow and returns the pointer.
2361  *
2362  * @note
2363  *   This function initializes device flow structure such as dv or verbs in
2364  *   struct mlx5_flow. However, it is caller's responsibility to initialize the
2365  *   rest. For example, adding returning device flow to flow->dev_flow list and
2366  *   setting backward reference to the flow should be done out of this function.
2367  *   layers field is not filled either.
2368  *
2369  * @param[in] attr
2370  *   Pointer to the flow attributes.
2371  * @param[in] items
2372  *   Pointer to the list of items.
2373  * @param[in] actions
2374  *   Pointer to the list of actions.
2375  * @param[out] error
2376  *   Pointer to the error structure.
2377  *
2378  * @return
2379  *   Pointer to device flow on success, otherwise NULL and rte_errno is set.
2380  */
2381 static inline struct mlx5_flow *
2382 flow_drv_prepare(const struct rte_flow *flow,
2383                  const struct rte_flow_attr *attr,
2384                  const struct rte_flow_item items[],
2385                  const struct rte_flow_action actions[],
2386                  struct rte_flow_error *error)
2387 {
2388         const struct mlx5_flow_driver_ops *fops;
2389         enum mlx5_flow_drv_type type = flow->drv_type;
2390
2391         assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);
2392         fops = flow_get_drv_ops(type);
2393         return fops->prepare(attr, items, actions, error);
2394 }
2395
2396 /**
2397  * Flow driver translation API. This abstracts calling driver specific
2398  * functions. Parent flow (rte_flow) should have driver type (drv_type). It
2399  * translates a generic flow into a driver flow. flow_drv_prepare() must
2400  * precede.
2401  *
2402  * @note
2403  *   dev_flow->layers could be filled as a result of parsing during translation
2404  *   if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled
2405  *   if necessary. As a flow can have multiple dev_flows by RSS flow expansion,
2406  *   flow->actions could be overwritten even though all the expanded dev_flows
2407  *   have the same actions.
2408  *
2409  * @param[in] dev
2410  *   Pointer to the rte dev structure.
2411  * @param[in, out] dev_flow
2412  *   Pointer to the mlx5 flow.
2413  * @param[in] attr
2414  *   Pointer to the flow attributes.
2415  * @param[in] items
2416  *   Pointer to the list of items.
2417  * @param[in] actions
2418  *   Pointer to the list of actions.
2419  * @param[out] error
2420  *   Pointer to the error structure.
2421  *
2422  * @return
2423  *   0 on success, a negative errno value otherwise and rte_errno is set.
2424  */
2425 static inline int
2426 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow,
2427                    const struct rte_flow_attr *attr,
2428                    const struct rte_flow_item items[],
2429                    const struct rte_flow_action actions[],
2430                    struct rte_flow_error *error)
2431 {
2432         const struct mlx5_flow_driver_ops *fops;
2433         enum mlx5_flow_drv_type type = dev_flow->flow->drv_type;
2434
2435         assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);
2436         fops = flow_get_drv_ops(type);
2437         return fops->translate(dev, dev_flow, attr, items, actions, error);
2438 }
2439
2440 /**
2441  * Flow driver apply API. This abstracts calling driver specific functions.
2442  * Parent flow (rte_flow) should have driver type (drv_type). It applies
2443  * translated driver flows on to device. flow_drv_translate() must precede.
2444  *
2445  * @param[in] dev
2446  *   Pointer to Ethernet device structure.
2447  * @param[in, out] flow
2448  *   Pointer to flow structure.
2449  * @param[out] error
2450  *   Pointer to error structure.
2451  *
2452  * @return
2453  *   0 on success, a negative errno value otherwise and rte_errno is set.
2454  */
2455 static inline int
2456 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
2457                struct rte_flow_error *error)
2458 {
2459         const struct mlx5_flow_driver_ops *fops;
2460         enum mlx5_flow_drv_type type = flow->drv_type;
2461
2462         assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);
2463         fops = flow_get_drv_ops(type);
2464         return fops->apply(dev, flow, error);
2465 }
2466
2467 /**
2468  * Flow driver remove API. This abstracts calling driver specific functions.
2469  * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow
2470  * on device. All the resources of the flow should be freed by calling
2471  * flow_drv_destroy().
2472  *
2473  * @param[in] dev
2474  *   Pointer to Ethernet device.
2475  * @param[in, out] flow
2476  *   Pointer to flow structure.
2477  */
2478 static inline void
2479 flow_drv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
2480 {
2481         const struct mlx5_flow_driver_ops *fops;
2482         enum mlx5_flow_drv_type type = flow->drv_type;
2483
2484         assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);
2485         fops = flow_get_drv_ops(type);
2486         fops->remove(dev, flow);
2487 }
2488
2489 /**
2490  * Flow driver destroy API. This abstracts calling driver specific functions.
2491  * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow
2492  * on device and releases resources of the flow.
2493  *
2494  * @param[in] dev
2495  *   Pointer to Ethernet device.
2496  * @param[in, out] flow
2497  *   Pointer to flow structure.
2498  */
2499 static inline void
2500 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
2501 {
2502         const struct mlx5_flow_driver_ops *fops;
2503         enum mlx5_flow_drv_type type = flow->drv_type;
2504
2505         assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);
2506         fops = flow_get_drv_ops(type);
2507         fops->destroy(dev, flow);
2508 }
2509
2510 /**
2511  * Validate a flow supported by the NIC.
2512  *
2513  * @see rte_flow_validate()
2514  * @see rte_flow_ops
2515  */
2516 int
2517 mlx5_flow_validate(struct rte_eth_dev *dev,
2518                    const struct rte_flow_attr *attr,
2519                    const struct rte_flow_item items[],
2520                    const struct rte_flow_action actions[],
2521                    struct rte_flow_error *error)
2522 {
2523         int ret;
2524
2525         ret = flow_drv_validate(dev, attr, items, actions, true, error);
2526         if (ret < 0)
2527                 return ret;
2528         return 0;
2529 }
2530
2531 /**
2532  * Get RSS action from the action list.
2533  *
2534  * @param[in] actions
2535  *   Pointer to the list of actions.
2536  *
2537  * @return
2538  *   Pointer to the RSS action if exist, else return NULL.
2539  */
2540 static const struct rte_flow_action_rss*
2541 flow_get_rss_action(const struct rte_flow_action actions[])
2542 {
2543         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
2544                 switch (actions->type) {
2545                 case RTE_FLOW_ACTION_TYPE_RSS:
2546                         return (const struct rte_flow_action_rss *)
2547                                actions->conf;
2548                 default:
2549                         break;
2550                 }
2551         }
2552         return NULL;
2553 }
2554
2555 static unsigned int
2556 find_graph_root(const struct rte_flow_item pattern[], uint32_t rss_level)
2557 {
2558         const struct rte_flow_item *item;
2559         unsigned int has_vlan = 0;
2560
2561         for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2562                 if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) {
2563                         has_vlan = 1;
2564                         break;
2565                 }
2566         }
2567         if (has_vlan)
2568                 return rss_level < 2 ? MLX5_EXPANSION_ROOT_ETH_VLAN :
2569                                        MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN;
2570         return rss_level < 2 ? MLX5_EXPANSION_ROOT :
2571                                MLX5_EXPANSION_ROOT_OUTER;
2572 }
2573
2574 /**
2575  * Check if the flow should be splited due to hairpin.
2576  * The reason for the split is that in current HW we can't
2577  * support encap on Rx, so if a flow have encap we move it
2578  * to Tx.
2579  *
2580  * @param dev
2581  *   Pointer to Ethernet device.
2582  * @param[in] attr
2583  *   Flow rule attributes.
2584  * @param[in] actions
2585  *   Associated actions (list terminated by the END action).
2586  *
2587  * @return
2588  *   > 0 the number of actions and the flow should be split,
2589  *   0 when no split required.
2590  */
2591 static int
2592 flow_check_hairpin_split(struct rte_eth_dev *dev,
2593                          const struct rte_flow_attr *attr,
2594                          const struct rte_flow_action actions[])
2595 {
2596         int queue_action = 0;
2597         int action_n = 0;
2598         int encap = 0;
2599         const struct rte_flow_action_queue *queue;
2600         const struct rte_flow_action_rss *rss;
2601         const struct rte_flow_action_raw_encap *raw_encap;
2602
2603         if (!attr->ingress)
2604                 return 0;
2605         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
2606                 switch (actions->type) {
2607                 case RTE_FLOW_ACTION_TYPE_QUEUE:
2608                         queue = actions->conf;
2609                         if (mlx5_rxq_get_type(dev, queue->index) !=
2610                             MLX5_RXQ_TYPE_HAIRPIN)
2611                                 return 0;
2612                         queue_action = 1;
2613                         action_n++;
2614                         break;
2615                 case RTE_FLOW_ACTION_TYPE_RSS:
2616                         rss = actions->conf;
2617                         if (mlx5_rxq_get_type(dev, rss->queue[0]) !=
2618                             MLX5_RXQ_TYPE_HAIRPIN)
2619                                 return 0;
2620                         queue_action = 1;
2621                         action_n++;
2622                         break;
2623                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
2624                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
2625                         encap = 1;
2626                         action_n++;
2627                         break;
2628                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
2629                         raw_encap = actions->conf;
2630                         if (raw_encap->size >
2631                             (sizeof(struct rte_flow_item_eth) +
2632                              sizeof(struct rte_flow_item_ipv4)))
2633                                 encap = 1;
2634                         action_n++;
2635                         break;
2636                 default:
2637                         action_n++;
2638                         break;
2639                 }
2640         }
2641         if (encap == 1 && queue_action)
2642                 return action_n;
2643         return 0;
2644 }
2645
2646 #define MLX5_MAX_SPLIT_ACTIONS 24
2647 #define MLX5_MAX_SPLIT_ITEMS 24
2648
2649 /**
2650  * Split the hairpin flow.
2651  * Since HW can't support encap on Rx we move the encap to Tx.
2652  * If the count action is after the encap then we also
2653  * move the count action. in this case the count will also measure
2654  * the outer bytes.
2655  *
2656  * @param dev
2657  *   Pointer to Ethernet device.
2658  * @param[in] actions
2659  *   Associated actions (list terminated by the END action).
2660  * @param[out] actions_rx
2661  *   Rx flow actions.
2662  * @param[out] actions_tx
2663  *   Tx flow actions..
2664  * @param[out] pattern_tx
2665  *   The pattern items for the Tx flow.
2666  * @param[out] flow_id
2667  *   The flow ID connected to this flow.
2668  *
2669  * @return
2670  *   0 on success.
2671  */
2672 static int
2673 flow_hairpin_split(struct rte_eth_dev *dev,
2674                    const struct rte_flow_action actions[],
2675                    struct rte_flow_action actions_rx[],
2676                    struct rte_flow_action actions_tx[],
2677                    struct rte_flow_item pattern_tx[],
2678                    uint32_t *flow_id)
2679 {
2680         struct mlx5_priv *priv = dev->data->dev_private;
2681         const struct rte_flow_action_raw_encap *raw_encap;
2682         const struct rte_flow_action_raw_decap *raw_decap;
2683         struct mlx5_rte_flow_action_set_tag *set_tag;
2684         struct rte_flow_action *tag_action;
2685         struct mlx5_rte_flow_item_tag *tag_item;
2686         struct rte_flow_item *item;
2687         char *addr;
2688         struct rte_flow_error error;
2689         int encap = 0;
2690
2691         mlx5_flow_id_get(priv->sh->flow_id_pool, flow_id);
2692         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
2693                 switch (actions->type) {
2694                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
2695                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
2696                         rte_memcpy(actions_tx, actions,
2697                                sizeof(struct rte_flow_action));
2698                         actions_tx++;
2699                         break;
2700                 case RTE_FLOW_ACTION_TYPE_COUNT:
2701                         if (encap) {
2702                                 rte_memcpy(actions_tx, actions,
2703                                            sizeof(struct rte_flow_action));
2704                                 actions_tx++;
2705                         } else {
2706                                 rte_memcpy(actions_rx, actions,
2707                                            sizeof(struct rte_flow_action));
2708                                 actions_rx++;
2709                         }
2710                         break;
2711                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
2712                         raw_encap = actions->conf;
2713                         if (raw_encap->size >
2714                             (sizeof(struct rte_flow_item_eth) +
2715                              sizeof(struct rte_flow_item_ipv4))) {
2716                                 memcpy(actions_tx, actions,
2717                                        sizeof(struct rte_flow_action));
2718                                 actions_tx++;
2719                                 encap = 1;
2720                         } else {
2721                                 rte_memcpy(actions_rx, actions,
2722                                            sizeof(struct rte_flow_action));
2723                                 actions_rx++;
2724                         }
2725                         break;
2726                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
2727                         raw_decap = actions->conf;
2728                         if (raw_decap->size <
2729                             (sizeof(struct rte_flow_item_eth) +
2730                              sizeof(struct rte_flow_item_ipv4))) {
2731                                 memcpy(actions_tx, actions,
2732                                        sizeof(struct rte_flow_action));
2733                                 actions_tx++;
2734                         } else {
2735                                 rte_memcpy(actions_rx, actions,
2736                                            sizeof(struct rte_flow_action));
2737                                 actions_rx++;
2738                         }
2739                         break;
2740                 default:
2741                         rte_memcpy(actions_rx, actions,
2742                                    sizeof(struct rte_flow_action));
2743                         actions_rx++;
2744                         break;
2745                 }
2746         }
2747         /* Add set meta action and end action for the Rx flow. */
2748         tag_action = actions_rx;
2749         tag_action->type = MLX5_RTE_FLOW_ACTION_TYPE_TAG;
2750         actions_rx++;
2751         rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action));
2752         actions_rx++;
2753         set_tag = (void *)actions_rx;
2754         set_tag->id = flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, &error);
2755         set_tag->data = *flow_id;
2756         tag_action->conf = set_tag;
2757         /* Create Tx item list. */
2758         rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action));
2759         addr = (void *)&pattern_tx[2];
2760         item = pattern_tx;
2761         item->type = MLX5_RTE_FLOW_ITEM_TYPE_TAG;
2762         tag_item = (void *)addr;
2763         tag_item->data = *flow_id;
2764         tag_item->id = flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL);
2765         item->spec = tag_item;
2766         addr += sizeof(struct mlx5_rte_flow_item_tag);
2767         tag_item = (void *)addr;
2768         tag_item->data = UINT32_MAX;
2769         tag_item->id = UINT16_MAX;
2770         item->mask = tag_item;
2771         addr += sizeof(struct mlx5_rte_flow_item_tag);
2772         item->last = NULL;
2773         item++;
2774         item->type = RTE_FLOW_ITEM_TYPE_END;
2775         return 0;
2776 }
2777
2778 /**
2779  * Create a flow and add it to @p list.
2780  *
2781  * @param dev
2782  *   Pointer to Ethernet device.
2783  * @param list
2784  *   Pointer to a TAILQ flow list. If this parameter NULL,
2785  *   no list insertion occurred, flow is just created,
2786  *   this is caller's responsibility to track the
2787  *   created flow.
2788  * @param[in] attr
2789  *   Flow rule attributes.
2790  * @param[in] items
2791  *   Pattern specification (list terminated by the END pattern item).
2792  * @param[in] actions
2793  *   Associated actions (list terminated by the END action).
2794  * @param[in] external
2795  *   This flow rule is created by request external to PMD.
2796  * @param[out] error
2797  *   Perform verbose error reporting if not NULL.
2798  *
2799  * @return
2800  *   A flow on success, NULL otherwise and rte_errno is set.
2801  */
2802 static struct rte_flow *
2803 flow_list_create(struct rte_eth_dev *dev, struct mlx5_flows *list,
2804                  const struct rte_flow_attr *attr,
2805                  const struct rte_flow_item items[],
2806                  const struct rte_flow_action actions[],
2807                  bool external, struct rte_flow_error *error)
2808 {
2809         struct mlx5_priv *priv = dev->data->dev_private;
2810         struct rte_flow *flow = NULL;
2811         struct mlx5_flow *dev_flow;
2812         const struct rte_flow_action_rss *rss;
2813         union {
2814                 struct rte_flow_expand_rss buf;
2815                 uint8_t buffer[2048];
2816         } expand_buffer;
2817         union {
2818                 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS];
2819                 uint8_t buffer[2048];
2820         } actions_rx;
2821         union {
2822                 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS];
2823                 uint8_t buffer[2048];
2824         } actions_hairpin_tx;
2825         union {
2826                 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS];
2827                 uint8_t buffer[2048];
2828         } items_tx;
2829         struct rte_flow_expand_rss *buf = &expand_buffer.buf;
2830         const struct rte_flow_action *p_actions_rx = actions;
2831         int ret;
2832         uint32_t i;
2833         uint32_t flow_size;
2834         int hairpin_flow = 0;
2835         uint32_t hairpin_id = 0;
2836         struct rte_flow_attr attr_tx = { .priority = 0 };
2837
2838         hairpin_flow = flow_check_hairpin_split(dev, attr, actions);
2839         if (hairpin_flow > 0) {
2840                 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) {
2841                         rte_errno = EINVAL;
2842                         return NULL;
2843                 }
2844                 flow_hairpin_split(dev, actions, actions_rx.actions,
2845                                    actions_hairpin_tx.actions, items_tx.items,
2846                                    &hairpin_id);
2847                 p_actions_rx = actions_rx.actions;
2848         }
2849         ret = flow_drv_validate(dev, attr, items, p_actions_rx, external,
2850                                 error);
2851         if (ret < 0)
2852                 goto error_before_flow;
2853         flow_size = sizeof(struct rte_flow);
2854         rss = flow_get_rss_action(p_actions_rx);
2855         if (rss)
2856                 flow_size += RTE_ALIGN_CEIL(rss->queue_num * sizeof(uint16_t),
2857                                             sizeof(void *));
2858         else
2859                 flow_size += RTE_ALIGN_CEIL(sizeof(uint16_t), sizeof(void *));
2860         flow = rte_calloc(__func__, 1, flow_size, 0);
2861         if (!flow) {
2862                 rte_errno = ENOMEM;
2863                 goto error_before_flow;
2864         }
2865         flow->drv_type = flow_get_drv_type(dev, attr);
2866         if (hairpin_id != 0)
2867                 flow->hairpin_flow_id = hairpin_id;
2868         assert(flow->drv_type > MLX5_FLOW_TYPE_MIN &&
2869                flow->drv_type < MLX5_FLOW_TYPE_MAX);
2870         flow->rss.queue = (void *)(flow + 1);
2871         if (rss) {
2872                 /*
2873                  * The following information is required by
2874                  * mlx5_flow_hashfields_adjust() in advance.
2875                  */
2876                 flow->rss.level = rss->level;
2877                 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
2878                 flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
2879         }
2880         LIST_INIT(&flow->dev_flows);
2881         if (rss && rss->types) {
2882                 unsigned int graph_root;
2883
2884                 graph_root = find_graph_root(items, rss->level);
2885                 ret = rte_flow_expand_rss(buf, sizeof(expand_buffer.buffer),
2886                                           items, rss->types,
2887                                           mlx5_support_expansion,
2888                                           graph_root);
2889                 assert(ret > 0 &&
2890                        (unsigned int)ret < sizeof(expand_buffer.buffer));
2891         } else {
2892                 buf->entries = 1;
2893                 buf->entry[0].pattern = (void *)(uintptr_t)items;
2894         }
2895         for (i = 0; i < buf->entries; ++i) {
2896                 dev_flow = flow_drv_prepare(flow, attr, buf->entry[i].pattern,
2897                                             p_actions_rx, error);
2898                 if (!dev_flow)
2899                         goto error;
2900                 dev_flow->flow = flow;
2901                 dev_flow->external = external;
2902                 LIST_INSERT_HEAD(&flow->dev_flows, dev_flow, next);
2903                 ret = flow_drv_translate(dev, dev_flow, attr,
2904                                          buf->entry[i].pattern,
2905                                          p_actions_rx, error);
2906                 if (ret < 0)
2907                         goto error;
2908         }
2909         /* Create the tx flow. */
2910         if (hairpin_flow) {
2911                 attr_tx.group = MLX5_HAIRPIN_TX_TABLE;
2912                 attr_tx.ingress = 0;
2913                 attr_tx.egress = 1;
2914                 dev_flow = flow_drv_prepare(flow, &attr_tx, items_tx.items,
2915                                             actions_hairpin_tx.actions, error);
2916                 if (!dev_flow)
2917                         goto error;
2918                 dev_flow->flow = flow;
2919                 dev_flow->external = 0;
2920                 LIST_INSERT_HEAD(&flow->dev_flows, dev_flow, next);
2921                 ret = flow_drv_translate(dev, dev_flow, &attr_tx,
2922                                          items_tx.items,
2923                                          actions_hairpin_tx.actions, error);
2924                 if (ret < 0)
2925                         goto error;
2926         }
2927         if (dev->data->dev_started) {
2928                 ret = flow_drv_apply(dev, flow, error);
2929                 if (ret < 0)
2930                         goto error;
2931         }
2932         if (list)
2933                 TAILQ_INSERT_TAIL(list, flow, next);
2934         flow_rxq_flags_set(dev, flow);
2935         return flow;
2936 error_before_flow:
2937         if (hairpin_id)
2938                 mlx5_flow_id_release(priv->sh->flow_id_pool,
2939                                      hairpin_id);
2940         return NULL;
2941 error:
2942         ret = rte_errno; /* Save rte_errno before cleanup. */
2943         if (flow->hairpin_flow_id)
2944                 mlx5_flow_id_release(priv->sh->flow_id_pool,
2945                                      flow->hairpin_flow_id);
2946         assert(flow);
2947         flow_drv_destroy(dev, flow);
2948         rte_free(flow);
2949         rte_errno = ret; /* Restore rte_errno. */
2950         return NULL;
2951 }
2952
2953 /**
2954  * Create a dedicated flow rule on e-switch table 0 (root table), to direct all
2955  * incoming packets to table 1.
2956  *
2957  * Other flow rules, requested for group n, will be created in
2958  * e-switch table n+1.
2959  * Jump action to e-switch group n will be created to group n+1.
2960  *
2961  * Used when working in switchdev mode, to utilise advantages of table 1
2962  * and above.
2963  *
2964  * @param dev
2965  *   Pointer to Ethernet device.
2966  *
2967  * @return
2968  *   Pointer to flow on success, NULL otherwise and rte_errno is set.
2969  */
2970 struct rte_flow *
2971 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev)
2972 {
2973         const struct rte_flow_attr attr = {
2974                 .group = 0,
2975                 .priority = 0,
2976                 .ingress = 1,
2977                 .egress = 0,
2978                 .transfer = 1,
2979         };
2980         const struct rte_flow_item pattern = {
2981                 .type = RTE_FLOW_ITEM_TYPE_END,
2982         };
2983         struct rte_flow_action_jump jump = {
2984                 .group = 1,
2985         };
2986         const struct rte_flow_action actions[] = {
2987                 {
2988                         .type = RTE_FLOW_ACTION_TYPE_JUMP,
2989                         .conf = &jump,
2990                 },
2991                 {
2992                         .type = RTE_FLOW_ACTION_TYPE_END,
2993                 },
2994         };
2995         struct mlx5_priv *priv = dev->data->dev_private;
2996         struct rte_flow_error error;
2997
2998         return flow_list_create(dev, &priv->ctrl_flows, &attr, &pattern,
2999                                 actions, false, &error);
3000 }
3001
3002 /**
3003  * Create a flow.
3004  *
3005  * @see rte_flow_create()
3006  * @see rte_flow_ops
3007  */
3008 struct rte_flow *
3009 mlx5_flow_create(struct rte_eth_dev *dev,
3010                  const struct rte_flow_attr *attr,
3011                  const struct rte_flow_item items[],
3012                  const struct rte_flow_action actions[],
3013                  struct rte_flow_error *error)
3014 {
3015         struct mlx5_priv *priv = dev->data->dev_private;
3016
3017         return flow_list_create(dev, &priv->flows,
3018                                 attr, items, actions, true, error);
3019 }
3020
3021 /**
3022  * Destroy a flow in a list.
3023  *
3024  * @param dev
3025  *   Pointer to Ethernet device.
3026  * @param list
3027  *   Pointer to a TAILQ flow list. If this parameter NULL,
3028  *   there is no flow removal from the list.
3029  * @param[in] flow
3030  *   Flow to destroy.
3031  */
3032 static void
3033 flow_list_destroy(struct rte_eth_dev *dev, struct mlx5_flows *list,
3034                   struct rte_flow *flow)
3035 {
3036         struct mlx5_priv *priv = dev->data->dev_private;
3037
3038         /*
3039          * Update RX queue flags only if port is started, otherwise it is
3040          * already clean.
3041          */
3042         if (dev->data->dev_started)
3043                 flow_rxq_flags_trim(dev, flow);
3044         if (flow->hairpin_flow_id)
3045                 mlx5_flow_id_release(priv->sh->flow_id_pool,
3046                                      flow->hairpin_flow_id);
3047         flow_drv_destroy(dev, flow);
3048         if (list)
3049                 TAILQ_REMOVE(list, flow, next);
3050         rte_free(flow->fdir);
3051         rte_free(flow);
3052 }
3053
3054 /**
3055  * Destroy all flows.
3056  *
3057  * @param dev
3058  *   Pointer to Ethernet device.
3059  * @param list
3060  *   Pointer to a TAILQ flow list.
3061  */
3062 void
3063 mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list)
3064 {
3065         while (!TAILQ_EMPTY(list)) {
3066                 struct rte_flow *flow;
3067
3068                 flow = TAILQ_FIRST(list);
3069                 flow_list_destroy(dev, list, flow);
3070         }
3071 }
3072
3073 /**
3074  * Remove all flows.
3075  *
3076  * @param dev
3077  *   Pointer to Ethernet device.
3078  * @param list
3079  *   Pointer to a TAILQ flow list.
3080  */
3081 void
3082 mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list)
3083 {
3084         struct rte_flow *flow;
3085
3086         TAILQ_FOREACH_REVERSE(flow, list, mlx5_flows, next)
3087                 flow_drv_remove(dev, flow);
3088         flow_rxq_flags_clear(dev);
3089 }
3090
3091 /**
3092  * Add all flows.
3093  *
3094  * @param dev
3095  *   Pointer to Ethernet device.
3096  * @param list
3097  *   Pointer to a TAILQ flow list.
3098  *
3099  * @return
3100  *   0 on success, a negative errno value otherwise and rte_errno is set.
3101  */
3102 int
3103 mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list)
3104 {
3105         struct rte_flow *flow;
3106         struct rte_flow_error error;
3107         int ret = 0;
3108
3109         TAILQ_FOREACH(flow, list, next) {
3110                 ret = flow_drv_apply(dev, flow, &error);
3111                 if (ret < 0)
3112                         goto error;
3113                 flow_rxq_flags_set(dev, flow);
3114         }
3115         return 0;
3116 error:
3117         ret = rte_errno; /* Save rte_errno before cleanup. */
3118         mlx5_flow_stop(dev, list);
3119         rte_errno = ret; /* Restore rte_errno. */
3120         return -rte_errno;
3121 }
3122
3123 /**
3124  * Verify the flow list is empty
3125  *
3126  * @param dev
3127  *  Pointer to Ethernet device.
3128  *
3129  * @return the number of flows not released.
3130  */
3131 int
3132 mlx5_flow_verify(struct rte_eth_dev *dev)
3133 {
3134         struct mlx5_priv *priv = dev->data->dev_private;
3135         struct rte_flow *flow;
3136         int ret = 0;
3137
3138         TAILQ_FOREACH(flow, &priv->flows, next) {
3139                 DRV_LOG(DEBUG, "port %u flow %p still referenced",
3140                         dev->data->port_id, (void *)flow);
3141                 ++ret;
3142         }
3143         return ret;
3144 }
3145
3146 /**
3147  * Enable default hairpin egress flow.
3148  *
3149  * @param dev
3150  *   Pointer to Ethernet device.
3151  * @param queue
3152  *   The queue index.
3153  *
3154  * @return
3155  *   0 on success, a negative errno value otherwise and rte_errno is set.
3156  */
3157 int
3158 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev,
3159                             uint32_t queue)
3160 {
3161         struct mlx5_priv *priv = dev->data->dev_private;
3162         const struct rte_flow_attr attr = {
3163                 .egress = 1,
3164                 .priority = 0,
3165         };
3166         struct mlx5_rte_flow_item_tx_queue queue_spec = {
3167                 .queue = queue,
3168         };
3169         struct mlx5_rte_flow_item_tx_queue queue_mask = {
3170                 .queue = UINT32_MAX,
3171         };
3172         struct rte_flow_item items[] = {
3173                 {
3174                         .type = MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
3175                         .spec = &queue_spec,
3176                         .last = NULL,
3177                         .mask = &queue_mask,
3178                 },
3179                 {
3180                         .type = RTE_FLOW_ITEM_TYPE_END,
3181                 },
3182         };
3183         struct rte_flow_action_jump jump = {
3184                 .group = MLX5_HAIRPIN_TX_TABLE,
3185         };
3186         struct rte_flow_action actions[2];
3187         struct rte_flow *flow;
3188         struct rte_flow_error error;
3189
3190         actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP;
3191         actions[0].conf = &jump;
3192         actions[1].type = RTE_FLOW_ACTION_TYPE_END;
3193         flow = flow_list_create(dev, &priv->ctrl_flows,
3194                                 &attr, items, actions, false, &error);
3195         if (!flow) {
3196                 DRV_LOG(DEBUG,
3197                         "Failed to create ctrl flow: rte_errno(%d),"
3198                         " type(%d), message(%s)",
3199                         rte_errno, error.type,
3200                         error.message ? error.message : " (no stated reason)");
3201                 return -rte_errno;
3202         }
3203         return 0;
3204 }
3205
3206 /**
3207  * Enable a control flow configured from the control plane.
3208  *
3209  * @param dev
3210  *   Pointer to Ethernet device.
3211  * @param eth_spec
3212  *   An Ethernet flow spec to apply.
3213  * @param eth_mask
3214  *   An Ethernet flow mask to apply.
3215  * @param vlan_spec
3216  *   A VLAN flow spec to apply.
3217  * @param vlan_mask
3218  *   A VLAN flow mask to apply.
3219  *
3220  * @return
3221  *   0 on success, a negative errno value otherwise and rte_errno is set.
3222  */
3223 int
3224 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
3225                     struct rte_flow_item_eth *eth_spec,
3226                     struct rte_flow_item_eth *eth_mask,
3227                     struct rte_flow_item_vlan *vlan_spec,
3228                     struct rte_flow_item_vlan *vlan_mask)
3229 {
3230         struct mlx5_priv *priv = dev->data->dev_private;
3231         const struct rte_flow_attr attr = {
3232                 .ingress = 1,
3233                 .priority = MLX5_FLOW_PRIO_RSVD,
3234         };
3235         struct rte_flow_item items[] = {
3236                 {
3237                         .type = RTE_FLOW_ITEM_TYPE_ETH,
3238                         .spec = eth_spec,
3239                         .last = NULL,
3240                         .mask = eth_mask,
3241                 },
3242                 {
3243                         .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN :
3244                                               RTE_FLOW_ITEM_TYPE_END,
3245                         .spec = vlan_spec,
3246                         .last = NULL,
3247                         .mask = vlan_mask,
3248                 },
3249                 {
3250                         .type = RTE_FLOW_ITEM_TYPE_END,
3251                 },
3252         };
3253         uint16_t queue[priv->reta_idx_n];
3254         struct rte_flow_action_rss action_rss = {
3255                 .func = RTE_ETH_HASH_FUNCTION_DEFAULT,
3256                 .level = 0,
3257                 .types = priv->rss_conf.rss_hf,
3258                 .key_len = priv->rss_conf.rss_key_len,
3259                 .queue_num = priv->reta_idx_n,
3260                 .key = priv->rss_conf.rss_key,
3261                 .queue = queue,
3262         };
3263         struct rte_flow_action actions[] = {
3264                 {
3265                         .type = RTE_FLOW_ACTION_TYPE_RSS,
3266                         .conf = &action_rss,
3267                 },
3268                 {
3269                         .type = RTE_FLOW_ACTION_TYPE_END,
3270                 },
3271         };
3272         struct rte_flow *flow;
3273         struct rte_flow_error error;
3274         unsigned int i;
3275
3276         if (!priv->reta_idx_n || !priv->rxqs_n) {
3277                 return 0;
3278         }
3279         for (i = 0; i != priv->reta_idx_n; ++i)
3280                 queue[i] = (*priv->reta_idx)[i];
3281         flow = flow_list_create(dev, &priv->ctrl_flows,
3282                                 &attr, items, actions, false, &error);
3283         if (!flow)
3284                 return -rte_errno;
3285         return 0;
3286 }
3287
3288 /**
3289  * Enable a flow control configured from the control plane.
3290  *
3291  * @param dev
3292  *   Pointer to Ethernet device.
3293  * @param eth_spec
3294  *   An Ethernet flow spec to apply.
3295  * @param eth_mask
3296  *   An Ethernet flow mask to apply.
3297  *
3298  * @return
3299  *   0 on success, a negative errno value otherwise and rte_errno is set.
3300  */
3301 int
3302 mlx5_ctrl_flow(struct rte_eth_dev *dev,
3303                struct rte_flow_item_eth *eth_spec,
3304                struct rte_flow_item_eth *eth_mask)
3305 {
3306         return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL);
3307 }
3308
3309 /**
3310  * Destroy a flow.
3311  *
3312  * @see rte_flow_destroy()
3313  * @see rte_flow_ops
3314  */
3315 int
3316 mlx5_flow_destroy(struct rte_eth_dev *dev,
3317                   struct rte_flow *flow,
3318                   struct rte_flow_error *error __rte_unused)
3319 {
3320         struct mlx5_priv *priv = dev->data->dev_private;
3321
3322         flow_list_destroy(dev, &priv->flows, flow);
3323         return 0;
3324 }
3325
3326 /**
3327  * Destroy all flows.
3328  *
3329  * @see rte_flow_flush()
3330  * @see rte_flow_ops
3331  */
3332 int
3333 mlx5_flow_flush(struct rte_eth_dev *dev,
3334                 struct rte_flow_error *error __rte_unused)
3335 {
3336         struct mlx5_priv *priv = dev->data->dev_private;
3337
3338         mlx5_flow_list_flush(dev, &priv->flows);
3339         return 0;
3340 }
3341
3342 /**
3343  * Isolated mode.
3344  *
3345  * @see rte_flow_isolate()
3346  * @see rte_flow_ops
3347  */
3348 int
3349 mlx5_flow_isolate(struct rte_eth_dev *dev,
3350                   int enable,
3351                   struct rte_flow_error *error)
3352 {
3353         struct mlx5_priv *priv = dev->data->dev_private;
3354
3355         if (dev->data->dev_started) {
3356                 rte_flow_error_set(error, EBUSY,
3357                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3358                                    NULL,
3359                                    "port must be stopped first");
3360                 return -rte_errno;
3361         }
3362         priv->isolated = !!enable;
3363         if (enable)
3364                 dev->dev_ops = &mlx5_dev_ops_isolate;
3365         else
3366                 dev->dev_ops = &mlx5_dev_ops;
3367         return 0;
3368 }
3369
3370 /**
3371  * Query a flow.
3372  *
3373  * @see rte_flow_query()
3374  * @see rte_flow_ops
3375  */
3376 static int
3377 flow_drv_query(struct rte_eth_dev *dev,
3378                struct rte_flow *flow,
3379                const struct rte_flow_action *actions,
3380                void *data,
3381                struct rte_flow_error *error)
3382 {
3383         const struct mlx5_flow_driver_ops *fops;
3384         enum mlx5_flow_drv_type ftype = flow->drv_type;
3385
3386         assert(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX);
3387         fops = flow_get_drv_ops(ftype);
3388
3389         return fops->query(dev, flow, actions, data, error);
3390 }
3391
3392 /**
3393  * Query a flow.
3394  *
3395  * @see rte_flow_query()
3396  * @see rte_flow_ops
3397  */
3398 int
3399 mlx5_flow_query(struct rte_eth_dev *dev,
3400                 struct rte_flow *flow,
3401                 const struct rte_flow_action *actions,
3402                 void *data,
3403                 struct rte_flow_error *error)
3404 {
3405         int ret;
3406
3407         ret = flow_drv_query(dev, flow, actions, data, error);
3408         if (ret < 0)
3409                 return ret;
3410         return 0;
3411 }
3412
3413 /**
3414  * Convert a flow director filter to a generic flow.
3415  *
3416  * @param dev
3417  *   Pointer to Ethernet device.
3418  * @param fdir_filter
3419  *   Flow director filter to add.
3420  * @param attributes
3421  *   Generic flow parameters structure.
3422  *
3423  * @return
3424  *   0 on success, a negative errno value otherwise and rte_errno is set.
3425  */
3426 static int
3427 flow_fdir_filter_convert(struct rte_eth_dev *dev,
3428                          const struct rte_eth_fdir_filter *fdir_filter,
3429                          struct mlx5_fdir *attributes)
3430 {
3431         struct mlx5_priv *priv = dev->data->dev_private;
3432         const struct rte_eth_fdir_input *input = &fdir_filter->input;
3433         const struct rte_eth_fdir_masks *mask =
3434                 &dev->data->dev_conf.fdir_conf.mask;
3435
3436         /* Validate queue number. */
3437         if (fdir_filter->action.rx_queue >= priv->rxqs_n) {
3438                 DRV_LOG(ERR, "port %u invalid queue number %d",
3439                         dev->data->port_id, fdir_filter->action.rx_queue);
3440                 rte_errno = EINVAL;
3441                 return -rte_errno;
3442         }
3443         attributes->attr.ingress = 1;
3444         attributes->items[0] = (struct rte_flow_item) {
3445                 .type = RTE_FLOW_ITEM_TYPE_ETH,
3446                 .spec = &attributes->l2,
3447                 .mask = &attributes->l2_mask,
3448         };
3449         switch (fdir_filter->action.behavior) {
3450         case RTE_ETH_FDIR_ACCEPT:
3451                 attributes->actions[0] = (struct rte_flow_action){
3452                         .type = RTE_FLOW_ACTION_TYPE_QUEUE,
3453                         .conf = &attributes->queue,
3454                 };
3455                 break;
3456         case RTE_ETH_FDIR_REJECT:
3457                 attributes->actions[0] = (struct rte_flow_action){
3458                         .type = RTE_FLOW_ACTION_TYPE_DROP,
3459                 };
3460                 break;
3461         default:
3462                 DRV_LOG(ERR, "port %u invalid behavior %d",
3463                         dev->data->port_id,
3464                         fdir_filter->action.behavior);
3465                 rte_errno = ENOTSUP;
3466                 return -rte_errno;
3467         }
3468         attributes->queue.index = fdir_filter->action.rx_queue;
3469         /* Handle L3. */
3470         switch (fdir_filter->input.flow_type) {
3471         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3472         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3473         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3474                 attributes->l3.ipv4.hdr = (struct rte_ipv4_hdr){
3475                         .src_addr = input->flow.ip4_flow.src_ip,
3476                         .dst_addr = input->flow.ip4_flow.dst_ip,
3477                         .time_to_live = input->flow.ip4_flow.ttl,
3478                         .type_of_service = input->flow.ip4_flow.tos,
3479                 };
3480                 attributes->l3_mask.ipv4.hdr = (struct rte_ipv4_hdr){
3481                         .src_addr = mask->ipv4_mask.src_ip,
3482                         .dst_addr = mask->ipv4_mask.dst_ip,
3483                         .time_to_live = mask->ipv4_mask.ttl,
3484                         .type_of_service = mask->ipv4_mask.tos,
3485                         .next_proto_id = mask->ipv4_mask.proto,
3486                 };
3487                 attributes->items[1] = (struct rte_flow_item){
3488                         .type = RTE_FLOW_ITEM_TYPE_IPV4,
3489                         .spec = &attributes->l3,
3490                         .mask = &attributes->l3_mask,
3491                 };
3492                 break;
3493         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3494         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3495         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3496                 attributes->l3.ipv6.hdr = (struct rte_ipv6_hdr){
3497                         .hop_limits = input->flow.ipv6_flow.hop_limits,
3498                         .proto = input->flow.ipv6_flow.proto,
3499                 };
3500
3501                 memcpy(attributes->l3.ipv6.hdr.src_addr,
3502                        input->flow.ipv6_flow.src_ip,
3503                        RTE_DIM(attributes->l3.ipv6.hdr.src_addr));
3504                 memcpy(attributes->l3.ipv6.hdr.dst_addr,
3505                        input->flow.ipv6_flow.dst_ip,
3506                        RTE_DIM(attributes->l3.ipv6.hdr.src_addr));
3507                 memcpy(attributes->l3_mask.ipv6.hdr.src_addr,
3508                        mask->ipv6_mask.src_ip,
3509                        RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr));
3510                 memcpy(attributes->l3_mask.ipv6.hdr.dst_addr,
3511                        mask->ipv6_mask.dst_ip,
3512                        RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr));
3513                 attributes->items[1] = (struct rte_flow_item){
3514                         .type = RTE_FLOW_ITEM_TYPE_IPV6,
3515                         .spec = &attributes->l3,
3516                         .mask = &attributes->l3_mask,
3517                 };
3518                 break;
3519         default:
3520                 DRV_LOG(ERR, "port %u invalid flow type%d",
3521                         dev->data->port_id, fdir_filter->input.flow_type);
3522                 rte_errno = ENOTSUP;
3523                 return -rte_errno;
3524         }
3525         /* Handle L4. */
3526         switch (fdir_filter->input.flow_type) {
3527         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3528                 attributes->l4.udp.hdr = (struct rte_udp_hdr){
3529                         .src_port = input->flow.udp4_flow.src_port,
3530                         .dst_port = input->flow.udp4_flow.dst_port,
3531                 };
3532                 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){
3533                         .src_port = mask->src_port_mask,
3534                         .dst_port = mask->dst_port_mask,
3535                 };
3536                 attributes->items[2] = (struct rte_flow_item){
3537                         .type = RTE_FLOW_ITEM_TYPE_UDP,
3538                         .spec = &attributes->l4,
3539                         .mask = &attributes->l4_mask,
3540                 };
3541                 break;
3542         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3543                 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){
3544                         .src_port = input->flow.tcp4_flow.src_port,
3545                         .dst_port = input->flow.tcp4_flow.dst_port,
3546                 };
3547                 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){
3548                         .src_port = mask->src_port_mask,
3549                         .dst_port = mask->dst_port_mask,
3550                 };
3551                 attributes->items[2] = (struct rte_flow_item){
3552                         .type = RTE_FLOW_ITEM_TYPE_TCP,
3553                         .spec = &attributes->l4,
3554                         .mask = &attributes->l4_mask,
3555                 };
3556                 break;
3557         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3558                 attributes->l4.udp.hdr = (struct rte_udp_hdr){
3559                         .src_port = input->flow.udp6_flow.src_port,
3560                         .dst_port = input->flow.udp6_flow.dst_port,
3561                 };
3562                 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){
3563                         .src_port = mask->src_port_mask,
3564                         .dst_port = mask->dst_port_mask,
3565                 };
3566                 attributes->items[2] = (struct rte_flow_item){
3567                         .type = RTE_FLOW_ITEM_TYPE_UDP,
3568                         .spec = &attributes->l4,
3569                         .mask = &attributes->l4_mask,
3570                 };
3571                 break;
3572         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3573                 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){
3574                         .src_port = input->flow.tcp6_flow.src_port,
3575                         .dst_port = input->flow.tcp6_flow.dst_port,
3576                 };
3577                 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){
3578                         .src_port = mask->src_port_mask,
3579                         .dst_port = mask->dst_port_mask,
3580                 };
3581                 attributes->items[2] = (struct rte_flow_item){
3582                         .type = RTE_FLOW_ITEM_TYPE_TCP,
3583                         .spec = &attributes->l4,
3584                         .mask = &attributes->l4_mask,
3585                 };
3586                 break;
3587         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3588         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3589                 break;
3590         default:
3591                 DRV_LOG(ERR, "port %u invalid flow type%d",
3592                         dev->data->port_id, fdir_filter->input.flow_type);
3593                 rte_errno = ENOTSUP;
3594                 return -rte_errno;
3595         }
3596         return 0;
3597 }
3598
3599 #define FLOW_FDIR_CMP(f1, f2, fld) \
3600         memcmp(&(f1)->fld, &(f2)->fld, sizeof(f1->fld))
3601
3602 /**
3603  * Compare two FDIR flows. If items and actions are identical, the two flows are
3604  * regarded as same.
3605  *
3606  * @param dev
3607  *   Pointer to Ethernet device.
3608  * @param f1
3609  *   FDIR flow to compare.
3610  * @param f2
3611  *   FDIR flow to compare.
3612  *
3613  * @return
3614  *   Zero on match, 1 otherwise.
3615  */
3616 static int
3617 flow_fdir_cmp(const struct mlx5_fdir *f1, const struct mlx5_fdir *f2)
3618 {
3619         if (FLOW_FDIR_CMP(f1, f2, attr) ||
3620             FLOW_FDIR_CMP(f1, f2, l2) ||
3621             FLOW_FDIR_CMP(f1, f2, l2_mask) ||
3622             FLOW_FDIR_CMP(f1, f2, l3) ||
3623             FLOW_FDIR_CMP(f1, f2, l3_mask) ||
3624             FLOW_FDIR_CMP(f1, f2, l4) ||
3625             FLOW_FDIR_CMP(f1, f2, l4_mask) ||
3626             FLOW_FDIR_CMP(f1, f2, actions[0].type))
3627                 return 1;
3628         if (f1->actions[0].type == RTE_FLOW_ACTION_TYPE_QUEUE &&
3629             FLOW_FDIR_CMP(f1, f2, queue))
3630                 return 1;
3631         return 0;
3632 }
3633
3634 /**
3635  * Search device flow list to find out a matched FDIR flow.
3636  *
3637  * @param dev
3638  *   Pointer to Ethernet device.
3639  * @param fdir_flow
3640  *   FDIR flow to lookup.
3641  *
3642  * @return
3643  *   Pointer of flow if found, NULL otherwise.
3644  */
3645 static struct rte_flow *
3646 flow_fdir_filter_lookup(struct rte_eth_dev *dev, struct mlx5_fdir *fdir_flow)
3647 {
3648         struct mlx5_priv *priv = dev->data->dev_private;
3649         struct rte_flow *flow = NULL;
3650
3651         assert(fdir_flow);
3652         TAILQ_FOREACH(flow, &priv->flows, next) {
3653                 if (flow->fdir && !flow_fdir_cmp(flow->fdir, fdir_flow)) {
3654                         DRV_LOG(DEBUG, "port %u found FDIR flow %p",
3655                                 dev->data->port_id, (void *)flow);
3656                         break;
3657                 }
3658         }
3659         return flow;
3660 }
3661
3662 /**
3663  * Add new flow director filter and store it in list.
3664  *
3665  * @param dev
3666  *   Pointer to Ethernet device.
3667  * @param fdir_filter
3668  *   Flow director filter to add.
3669  *
3670  * @return
3671  *   0 on success, a negative errno value otherwise and rte_errno is set.
3672  */
3673 static int
3674 flow_fdir_filter_add(struct rte_eth_dev *dev,
3675                      const struct rte_eth_fdir_filter *fdir_filter)
3676 {
3677         struct mlx5_priv *priv = dev->data->dev_private;
3678         struct mlx5_fdir *fdir_flow;
3679         struct rte_flow *flow;
3680         int ret;
3681
3682         fdir_flow = rte_zmalloc(__func__, sizeof(*fdir_flow), 0);
3683         if (!fdir_flow) {
3684                 rte_errno = ENOMEM;
3685                 return -rte_errno;
3686         }
3687         ret = flow_fdir_filter_convert(dev, fdir_filter, fdir_flow);
3688         if (ret)
3689                 goto error;
3690         flow = flow_fdir_filter_lookup(dev, fdir_flow);
3691         if (flow) {
3692                 rte_errno = EEXIST;
3693                 goto error;
3694         }
3695         flow = flow_list_create(dev, &priv->flows, &fdir_flow->attr,
3696                                 fdir_flow->items, fdir_flow->actions, true,
3697                                 NULL);
3698         if (!flow)
3699                 goto error;
3700         assert(!flow->fdir);
3701         flow->fdir = fdir_flow;
3702         DRV_LOG(DEBUG, "port %u created FDIR flow %p",
3703                 dev->data->port_id, (void *)flow);
3704         return 0;
3705 error:
3706         rte_free(fdir_flow);
3707         return -rte_errno;
3708 }
3709
3710 /**
3711  * Delete specific filter.
3712  *
3713  * @param dev
3714  *   Pointer to Ethernet device.
3715  * @param fdir_filter
3716  *   Filter to be deleted.
3717  *
3718  * @return
3719  *   0 on success, a negative errno value otherwise and rte_errno is set.
3720  */
3721 static int
3722 flow_fdir_filter_delete(struct rte_eth_dev *dev,
3723                         const struct rte_eth_fdir_filter *fdir_filter)
3724 {
3725         struct mlx5_priv *priv = dev->data->dev_private;
3726         struct rte_flow *flow;
3727         struct mlx5_fdir fdir_flow = {
3728                 .attr.group = 0,
3729         };
3730         int ret;
3731
3732         ret = flow_fdir_filter_convert(dev, fdir_filter, &fdir_flow);
3733         if (ret)
3734                 return -rte_errno;
3735         flow = flow_fdir_filter_lookup(dev, &fdir_flow);
3736         if (!flow) {
3737                 rte_errno = ENOENT;
3738                 return -rte_errno;
3739         }
3740         flow_list_destroy(dev, &priv->flows, flow);
3741         DRV_LOG(DEBUG, "port %u deleted FDIR flow %p",
3742                 dev->data->port_id, (void *)flow);
3743         return 0;
3744 }
3745
3746 /**
3747  * Update queue for specific filter.
3748  *
3749  * @param dev
3750  *   Pointer to Ethernet device.
3751  * @param fdir_filter
3752  *   Filter to be updated.
3753  *
3754  * @return
3755  *   0 on success, a negative errno value otherwise and rte_errno is set.
3756  */
3757 static int
3758 flow_fdir_filter_update(struct rte_eth_dev *dev,
3759                         const struct rte_eth_fdir_filter *fdir_filter)
3760 {
3761         int ret;
3762
3763         ret = flow_fdir_filter_delete(dev, fdir_filter);
3764         if (ret)
3765                 return ret;
3766         return flow_fdir_filter_add(dev, fdir_filter);
3767 }
3768
3769 /**
3770  * Flush all filters.
3771  *
3772  * @param dev
3773  *   Pointer to Ethernet device.
3774  */
3775 static void
3776 flow_fdir_filter_flush(struct rte_eth_dev *dev)
3777 {
3778         struct mlx5_priv *priv = dev->data->dev_private;
3779
3780         mlx5_flow_list_flush(dev, &priv->flows);
3781 }
3782
3783 /**
3784  * Get flow director information.
3785  *
3786  * @param dev
3787  *   Pointer to Ethernet device.
3788  * @param[out] fdir_info
3789  *   Resulting flow director information.
3790  */
3791 static void
3792 flow_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
3793 {
3794         struct rte_eth_fdir_masks *mask =
3795                 &dev->data->dev_conf.fdir_conf.mask;
3796
3797         fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
3798         fdir_info->guarant_spc = 0;
3799         rte_memcpy(&fdir_info->mask, mask, sizeof(fdir_info->mask));
3800         fdir_info->max_flexpayload = 0;
3801         fdir_info->flow_types_mask[0] = 0;
3802         fdir_info->flex_payload_unit = 0;
3803         fdir_info->max_flex_payload_segment_num = 0;
3804         fdir_info->flex_payload_limit = 0;
3805         memset(&fdir_info->flex_conf, 0, sizeof(fdir_info->flex_conf));
3806 }
3807
3808 /**
3809  * Deal with flow director operations.
3810  *
3811  * @param dev
3812  *   Pointer to Ethernet device.
3813  * @param filter_op
3814  *   Operation to perform.
3815  * @param arg
3816  *   Pointer to operation-specific structure.
3817  *
3818  * @return
3819  *   0 on success, a negative errno value otherwise and rte_errno is set.
3820  */
3821 static int
3822 flow_fdir_ctrl_func(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3823                     void *arg)
3824 {
3825         enum rte_fdir_mode fdir_mode =
3826                 dev->data->dev_conf.fdir_conf.mode;
3827
3828         if (filter_op == RTE_ETH_FILTER_NOP)
3829                 return 0;
3830         if (fdir_mode != RTE_FDIR_MODE_PERFECT &&
3831             fdir_mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3832                 DRV_LOG(ERR, "port %u flow director mode %d not supported",
3833                         dev->data->port_id, fdir_mode);
3834                 rte_errno = EINVAL;
3835                 return -rte_errno;
3836         }
3837         switch (filter_op) {
3838         case RTE_ETH_FILTER_ADD:
3839                 return flow_fdir_filter_add(dev, arg);
3840         case RTE_ETH_FILTER_UPDATE:
3841                 return flow_fdir_filter_update(dev, arg);
3842         case RTE_ETH_FILTER_DELETE:
3843                 return flow_fdir_filter_delete(dev, arg);
3844         case RTE_ETH_FILTER_FLUSH:
3845                 flow_fdir_filter_flush(dev);
3846                 break;
3847         case RTE_ETH_FILTER_INFO:
3848                 flow_fdir_info_get(dev, arg);
3849                 break;
3850         default:
3851                 DRV_LOG(DEBUG, "port %u unknown operation %u",
3852                         dev->data->port_id, filter_op);
3853                 rte_errno = EINVAL;
3854                 return -rte_errno;
3855         }
3856         return 0;
3857 }
3858
3859 /**
3860  * Manage filter operations.
3861  *
3862  * @param dev
3863  *   Pointer to Ethernet device structure.
3864  * @param filter_type
3865  *   Filter type.
3866  * @param filter_op
3867  *   Operation to perform.
3868  * @param arg
3869  *   Pointer to operation-specific structure.
3870  *
3871  * @return
3872  *   0 on success, a negative errno value otherwise and rte_errno is set.
3873  */
3874 int
3875 mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
3876                      enum rte_filter_type filter_type,
3877                      enum rte_filter_op filter_op,
3878                      void *arg)
3879 {
3880         switch (filter_type) {
3881         case RTE_ETH_FILTER_GENERIC:
3882                 if (filter_op != RTE_ETH_FILTER_GET) {
3883                         rte_errno = EINVAL;
3884                         return -rte_errno;
3885                 }
3886                 *(const void **)arg = &mlx5_flow_ops;
3887                 return 0;
3888         case RTE_ETH_FILTER_FDIR:
3889                 return flow_fdir_ctrl_func(dev, filter_op, arg);
3890         default:
3891                 DRV_LOG(ERR, "port %u filter type (%d) not supported",
3892                         dev->data->port_id, filter_type);
3893                 rte_errno = ENOTSUP;
3894                 return -rte_errno;
3895         }
3896         return 0;
3897 }
3898
3899 #define MLX5_POOL_QUERY_FREQ_US 1000000
3900
3901 /**
3902  * Set the periodic procedure for triggering asynchronous batch queries for all
3903  * the counter pools.
3904  *
3905  * @param[in] sh
3906  *   Pointer to mlx5_ibv_shared object.
3907  */
3908 void
3909 mlx5_set_query_alarm(struct mlx5_ibv_shared *sh)
3910 {
3911         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(sh, 0, 0);
3912         uint32_t pools_n = rte_atomic16_read(&cont->n_valid);
3913         uint32_t us;
3914
3915         cont = MLX5_CNT_CONTAINER(sh, 1, 0);
3916         pools_n += rte_atomic16_read(&cont->n_valid);
3917         us = MLX5_POOL_QUERY_FREQ_US / pools_n;
3918         DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us);
3919         if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) {
3920                 sh->cmng.query_thread_on = 0;
3921                 DRV_LOG(ERR, "Cannot reinitialize query alarm");
3922         } else {
3923                 sh->cmng.query_thread_on = 1;
3924         }
3925 }
3926
3927 /**
3928  * The periodic procedure for triggering asynchronous batch queries for all the
3929  * counter pools. This function is probably called by the host thread.
3930  *
3931  * @param[in] arg
3932  *   The parameter for the alarm process.
3933  */
3934 void
3935 mlx5_flow_query_alarm(void *arg)
3936 {
3937         struct mlx5_ibv_shared *sh = arg;
3938         struct mlx5_devx_obj *dcs;
3939         uint16_t offset;
3940         int ret;
3941         uint8_t batch = sh->cmng.batch;
3942         uint16_t pool_index = sh->cmng.pool_index;
3943         struct mlx5_pools_container *cont;
3944         struct mlx5_pools_container *mcont;
3945         struct mlx5_flow_counter_pool *pool;
3946
3947         if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES)
3948                 goto set_alarm;
3949 next_container:
3950         cont = MLX5_CNT_CONTAINER(sh, batch, 1);
3951         mcont = MLX5_CNT_CONTAINER(sh, batch, 0);
3952         /* Check if resize was done and need to flip a container. */
3953         if (cont != mcont) {
3954                 if (cont->pools) {
3955                         /* Clean the old container. */
3956                         rte_free(cont->pools);
3957                         memset(cont, 0, sizeof(*cont));
3958                 }
3959                 rte_cio_wmb();
3960                  /* Flip the host container. */
3961                 sh->cmng.mhi[batch] ^= (uint8_t)2;
3962                 cont = mcont;
3963         }
3964         if (!cont->pools) {
3965                 /* 2 empty containers case is unexpected. */
3966                 if (unlikely(batch != sh->cmng.batch))
3967                         goto set_alarm;
3968                 batch ^= 0x1;
3969                 pool_index = 0;
3970                 goto next_container;
3971         }
3972         pool = cont->pools[pool_index];
3973         if (pool->raw_hw)
3974                 /* There is a pool query in progress. */
3975                 goto set_alarm;
3976         pool->raw_hw =
3977                 LIST_FIRST(&sh->cmng.free_stat_raws);
3978         if (!pool->raw_hw)
3979                 /* No free counter statistics raw memory. */
3980                 goto set_alarm;
3981         dcs = (struct mlx5_devx_obj *)(uintptr_t)rte_atomic64_read
3982                                                               (&pool->a64_dcs);
3983         offset = batch ? 0 : dcs->id % MLX5_COUNTERS_PER_POOL;
3984         ret = mlx5_devx_cmd_flow_counter_query(dcs, 0, MLX5_COUNTERS_PER_POOL -
3985                                                offset, NULL, NULL,
3986                                                pool->raw_hw->mem_mng->dm->id,
3987                                                (void *)(uintptr_t)
3988                                                (pool->raw_hw->data + offset),
3989                                                sh->devx_comp,
3990                                                (uint64_t)(uintptr_t)pool);
3991         if (ret) {
3992                 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID"
3993                         " %d", pool->min_dcs->id);
3994                 pool->raw_hw = NULL;
3995                 goto set_alarm;
3996         }
3997         pool->raw_hw->min_dcs_id = dcs->id;
3998         LIST_REMOVE(pool->raw_hw, next);
3999         sh->cmng.pending_queries++;
4000         pool_index++;
4001         if (pool_index >= rte_atomic16_read(&cont->n_valid)) {
4002                 batch ^= 0x1;
4003                 pool_index = 0;
4004         }
4005 set_alarm:
4006         sh->cmng.batch = batch;
4007         sh->cmng.pool_index = pool_index;
4008         mlx5_set_query_alarm(sh);
4009 }
4010
4011 /**
4012  * Handler for the HW respond about ready values from an asynchronous batch
4013  * query. This function is probably called by the host thread.
4014  *
4015  * @param[in] sh
4016  *   The pointer to the shared IB device context.
4017  * @param[in] async_id
4018  *   The Devx async ID.
4019  * @param[in] status
4020  *   The status of the completion.
4021  */
4022 void
4023 mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
4024                                   uint64_t async_id, int status)
4025 {
4026         struct mlx5_flow_counter_pool *pool =
4027                 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id;
4028         struct mlx5_counter_stats_raw *raw_to_free;
4029
4030         if (unlikely(status)) {
4031                 raw_to_free = pool->raw_hw;
4032         } else {
4033                 raw_to_free = pool->raw;
4034                 rte_spinlock_lock(&pool->sl);
4035                 pool->raw = pool->raw_hw;
4036                 rte_spinlock_unlock(&pool->sl);
4037                 rte_atomic64_add(&pool->query_gen, 1);
4038                 /* Be sure the new raw counters data is updated in memory. */
4039                 rte_cio_wmb();
4040         }
4041         LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next);
4042         pool->raw_hw = NULL;
4043         sh->cmng.pending_queries--;
4044 }
4045
4046 /**
4047  * Translate the rte_flow group index to HW table value.
4048  *
4049  * @param[in] attributes
4050  *   Pointer to flow attributes
4051  * @param[in] external
4052  *   Value is part of flow rule created by request external to PMD.
4053  * @param[in] group
4054  *   rte_flow group index value.
4055  * @param[out] table
4056  *   HW table value.
4057  * @param[out] error
4058  *   Pointer to error structure.
4059  *
4060  * @return
4061  *   0 on success, a negative errno value otherwise and rte_errno is set.
4062  */
4063 int
4064 mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, bool external,
4065                          uint32_t group, uint32_t *table,
4066                          struct rte_flow_error *error)
4067 {
4068         if (attributes->transfer && external) {
4069                 if (group == UINT32_MAX)
4070                         return rte_flow_error_set
4071                                                 (error, EINVAL,
4072                                                  RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4073                                                  NULL,
4074                                                  "group index not supported");
4075                 *table = group + 1;
4076         } else {
4077                 *table = group;
4078         }
4079         return 0;
4080 }
4081
4082 /**
4083  * Discover availability of metadata reg_c's.
4084  *
4085  * Iteratively use test flows to check availability.
4086  *
4087  * @param[in] dev
4088  *   Pointer to the Ethernet device structure.
4089  *
4090  * @return
4091  *   0 on success, a negative errno value otherwise and rte_errno is set.
4092  */
4093 int
4094 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev)
4095 {
4096         struct mlx5_priv *priv = dev->data->dev_private;
4097         struct mlx5_dev_config *config = &priv->config;
4098         enum modify_reg idx;
4099         int n = 0;
4100
4101         /* reg_c[0] and reg_c[1] are reserved. */
4102         config->flow_mreg_c[n++] = REG_C_0;
4103         config->flow_mreg_c[n++] = REG_C_1;
4104         /* Discover availability of other reg_c's. */
4105         for (idx = REG_C_2; idx <= REG_C_7; ++idx) {
4106                 struct rte_flow_attr attr = {
4107                         .group = MLX5_FLOW_MREG_CP_TABLE_GROUP,
4108                         .priority = MLX5_FLOW_PRIO_RSVD,
4109                         .ingress = 1,
4110                 };
4111                 struct rte_flow_item items[] = {
4112                         [0] = {
4113                                 .type = RTE_FLOW_ITEM_TYPE_END,
4114                         },
4115                 };
4116                 struct rte_flow_action actions[] = {
4117                         [0] = {
4118                                 .type = MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
4119                                 .conf = &(struct mlx5_flow_action_copy_mreg){
4120                                         .src = REG_C_1,
4121                                         .dst = idx,
4122                                 },
4123                         },
4124                         [1] = {
4125                                 .type = RTE_FLOW_ACTION_TYPE_JUMP,
4126                                 .conf = &(struct rte_flow_action_jump){
4127                                         .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP,
4128                                 },
4129                         },
4130                         [2] = {
4131                                 .type = RTE_FLOW_ACTION_TYPE_END,
4132                         },
4133                 };
4134                 struct rte_flow *flow;
4135                 struct rte_flow_error error;
4136
4137                 if (!config->dv_flow_en)
4138                         break;
4139                 /* Create internal flow, validation skips copy action. */
4140                 flow = flow_list_create(dev, NULL, &attr, items,
4141                                         actions, false, &error);
4142                 if (!flow)
4143                         continue;
4144                 if (dev->data->dev_started || !flow_drv_apply(dev, flow, NULL))
4145                         config->flow_mreg_c[n++] = idx;
4146                 flow_list_destroy(dev, NULL, flow);
4147         }
4148         for (; n < MLX5_MREG_C_NUM; ++n)
4149                 config->flow_mreg_c[n] = REG_NONE;
4150         return 0;
4151 }