1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Private rte flow items. */
31 enum mlx5_rte_flow_item_type {
32 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
34 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
37 /* Private (internal) rte flow actions. */
38 enum mlx5_rte_flow_action_type {
39 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
40 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
41 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
44 /* Matches on selected register. */
45 struct mlx5_rte_flow_item_tag {
50 /* Modify selected register. */
51 struct mlx5_rte_flow_action_set_tag {
56 struct mlx5_flow_action_copy_mreg {
61 /* Matches on source queue. */
62 struct mlx5_rte_flow_item_tx_queue {
66 /* Feature name to allocate metadata register. */
67 enum mlx5_feature_name {
78 /* Pattern outer Layer bits. */
79 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
80 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
81 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
82 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
83 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
84 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
86 /* Pattern inner Layer bits. */
87 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
88 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
89 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
90 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
91 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
92 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
94 /* Pattern tunnel Layer bits. */
95 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
96 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
97 #define MLX5_FLOW_LAYER_GRE (1u << 14)
98 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
99 /* List of tunnel Layer bits continued below. */
101 /* General pattern items bits. */
102 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
103 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
104 #define MLX5_FLOW_ITEM_TAG (1u << 18)
105 #define MLX5_FLOW_ITEM_MARK (1u << 19)
107 /* Pattern MISC bits. */
108 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
109 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
110 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
112 /* Pattern tunnel Layer bits (continued). */
113 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
114 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
115 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
116 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
119 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
122 #define MLX5_FLOW_LAYER_OUTER_L3 \
123 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
124 #define MLX5_FLOW_LAYER_OUTER_L4 \
125 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
126 #define MLX5_FLOW_LAYER_OUTER \
127 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
128 MLX5_FLOW_LAYER_OUTER_L4)
130 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
131 #define MLX5_FLOW_LAYER_IPV4_LRO \
132 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
133 #define MLX5_FLOW_LAYER_IPV6_LRO \
134 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
137 #define MLX5_FLOW_LAYER_TUNNEL \
138 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
139 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
140 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
141 MLX5_FLOW_LAYER_GENEVE)
144 #define MLX5_FLOW_LAYER_INNER_L3 \
145 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
146 #define MLX5_FLOW_LAYER_INNER_L4 \
147 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
148 #define MLX5_FLOW_LAYER_INNER \
149 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
150 MLX5_FLOW_LAYER_INNER_L4)
153 #define MLX5_FLOW_LAYER_L2 \
154 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
155 #define MLX5_FLOW_LAYER_L3_IPV4 \
156 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
157 #define MLX5_FLOW_LAYER_L3_IPV6 \
158 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
159 #define MLX5_FLOW_LAYER_L3 \
160 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
161 #define MLX5_FLOW_LAYER_L4 \
162 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
165 #define MLX5_FLOW_ACTION_DROP (1u << 0)
166 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
167 #define MLX5_FLOW_ACTION_RSS (1u << 2)
168 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
169 #define MLX5_FLOW_ACTION_MARK (1u << 4)
170 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
171 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
172 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
173 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
174 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
175 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
176 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
177 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
178 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
179 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
180 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
181 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
182 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
183 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
184 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
185 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
186 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
187 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
188 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
189 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
190 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
191 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
192 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
193 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
194 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
195 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
196 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
197 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
198 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33)
200 #define MLX5_FLOW_FATE_ACTIONS \
201 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
202 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
204 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
205 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
206 MLX5_FLOW_ACTION_JUMP)
208 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
209 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
210 MLX5_FLOW_ACTION_RAW_ENCAP | \
211 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
213 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
214 MLX5_FLOW_ACTION_NVGRE_DECAP | \
215 MLX5_FLOW_ACTION_RAW_DECAP | \
216 MLX5_FLOW_ACTION_OF_POP_VLAN)
218 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
219 MLX5_FLOW_ACTION_SET_IPV4_DST | \
220 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
221 MLX5_FLOW_ACTION_SET_IPV6_DST | \
222 MLX5_FLOW_ACTION_SET_TP_SRC | \
223 MLX5_FLOW_ACTION_SET_TP_DST | \
224 MLX5_FLOW_ACTION_SET_TTL | \
225 MLX5_FLOW_ACTION_DEC_TTL | \
226 MLX5_FLOW_ACTION_SET_MAC_SRC | \
227 MLX5_FLOW_ACTION_SET_MAC_DST | \
228 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
229 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
230 MLX5_FLOW_ACTION_INC_TCP_ACK | \
231 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
232 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
233 MLX5_FLOW_ACTION_SET_TAG | \
234 MLX5_FLOW_ACTION_MARK_EXT)
236 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
237 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
239 #define IPPROTO_MPLS 137
242 /* UDP port number for MPLS */
243 #define MLX5_UDP_PORT_MPLS 6635
245 /* UDP port numbers for VxLAN. */
246 #define MLX5_UDP_PORT_VXLAN 4789
247 #define MLX5_UDP_PORT_VXLAN_GPE 4790
249 /* UDP port numbers for GENEVE. */
250 #define MLX5_UDP_PORT_GENEVE 6081
252 /* Priority reserved for default flows. */
253 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
256 * Number of sub priorities.
257 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
258 * matching on the NIC (firmware dependent) L4 most have the higher priority
259 * followed by L3 and ending with L2.
261 #define MLX5_PRIORITY_MAP_L2 2
262 #define MLX5_PRIORITY_MAP_L3 1
263 #define MLX5_PRIORITY_MAP_L4 0
264 #define MLX5_PRIORITY_MAP_MAX 3
266 /* Valid layer type for IPV4 RSS. */
267 #define MLX5_IPV4_LAYER_TYPES \
268 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
269 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
270 ETH_RSS_NONFRAG_IPV4_OTHER)
272 /* IBV hash source bits for IPV4. */
273 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
275 /* Valid layer type for IPV6 RSS. */
276 #define MLX5_IPV6_LAYER_TYPES \
277 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
278 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
279 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
281 /* IBV hash source bits for IPV6. */
282 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
285 /* Geneve header first 16Bit */
286 #define MLX5_GENEVE_VER_MASK 0x3
287 #define MLX5_GENEVE_VER_SHIFT 14
288 #define MLX5_GENEVE_VER_VAL(a) \
289 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
290 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
291 #define MLX5_GENEVE_OPTLEN_SHIFT 7
292 #define MLX5_GENEVE_OPTLEN_VAL(a) \
293 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
294 #define MLX5_GENEVE_OAMF_MASK 0x1
295 #define MLX5_GENEVE_OAMF_SHIFT 7
296 #define MLX5_GENEVE_OAMF_VAL(a) \
297 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
298 #define MLX5_GENEVE_CRITO_MASK 0x1
299 #define MLX5_GENEVE_CRITO_SHIFT 6
300 #define MLX5_GENEVE_CRITO_VAL(a) \
301 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
302 #define MLX5_GENEVE_RSVD_MASK 0x3F
303 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
305 * The length of the Geneve options fields, expressed in four byte multiples,
306 * not including the eight byte fixed tunnel.
308 #define MLX5_GENEVE_OPT_LEN_0 14
309 #define MLX5_GENEVE_OPT_LEN_1 63
311 enum mlx5_flow_drv_type {
314 MLX5_FLOW_TYPE_VERBS,
318 /* Matcher PRM representation */
319 struct mlx5_flow_dv_match_params {
321 /**< Size of match value. Do NOT split size and key! */
322 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
323 /**< Matcher value. This value is used as the mask or as a key. */
326 /* Matcher structure. */
327 struct mlx5_flow_dv_matcher {
328 LIST_ENTRY(mlx5_flow_dv_matcher) next;
329 /* Pointer to the next element. */
330 rte_atomic32_t refcnt; /**< Reference counter. */
331 void *matcher_object; /**< Pointer to DV matcher */
332 uint16_t crc; /**< CRC of key. */
333 uint16_t priority; /**< Priority of matcher. */
334 uint8_t egress; /**< Egress matcher. */
335 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
336 uint32_t group; /**< The matcher group. */
337 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
340 #define MLX5_ENCAP_MAX_LEN 132
342 /* Encap/decap resource structure. */
343 struct mlx5_flow_dv_encap_decap_resource {
344 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
345 /* Pointer to next element. */
346 rte_atomic32_t refcnt; /**< Reference counter. */
348 /**< Verbs encap/decap action object. */
349 uint8_t buf[MLX5_ENCAP_MAX_LEN];
351 uint8_t reformat_type;
353 uint64_t flags; /**< Flags for RDMA API. */
356 /* Tag resource structure. */
357 struct mlx5_flow_dv_tag_resource {
358 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
359 /* Pointer to next element. */
360 rte_atomic32_t refcnt; /**< Reference counter. */
362 /**< Verbs tag action object. */
363 uint32_t tag; /**< the tag value. */
367 * Number of modification commands.
368 * If extensive metadata registers are supported
369 * the maximal actions amount is 16 and 8 otherwise.
371 #define MLX5_MODIFY_NUM 16
372 #define MLX5_MODIFY_NUM_NO_MREG 8
374 /* Modify resource structure */
375 struct mlx5_flow_dv_modify_hdr_resource {
376 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
377 /* Pointer to next element. */
378 rte_atomic32_t refcnt; /**< Reference counter. */
379 struct ibv_flow_action *verbs_action;
380 /**< Verbs modify header action object. */
381 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
382 uint32_t actions_num; /**< Number of modification actions. */
383 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
384 /**< Modification actions. */
385 uint64_t flags; /**< Flags for RDMA API. */
388 /* Jump action resource structure. */
389 struct mlx5_flow_dv_jump_tbl_resource {
390 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
391 /* Pointer to next element. */
392 rte_atomic32_t refcnt; /**< Reference counter. */
393 void *action; /**< Pointer to the rdma core action. */
394 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
395 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
398 /* Port ID resource structure. */
399 struct mlx5_flow_dv_port_id_action_resource {
400 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
401 /* Pointer to next element. */
402 rte_atomic32_t refcnt; /**< Reference counter. */
404 /**< Verbs tag action object. */
405 uint32_t port_id; /**< Port ID value. */
408 /* Push VLAN action resource structure */
409 struct mlx5_flow_dv_push_vlan_action_resource {
410 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
411 /* Pointer to next element. */
412 rte_atomic32_t refcnt; /**< Reference counter. */
413 void *action; /**< Direct verbs action object. */
414 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
415 rte_be32_t vlan_tag; /**< VLAN tag value. */
419 * Max number of actions per DV flow.
420 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
421 * In rdma-core file providers/mlx5/verbs.c
423 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
425 /* DV flows structure. */
426 struct mlx5_flow_dv {
427 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
429 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
430 struct mlx5_flow_dv_match_params value;
431 /**< Holds the value that the packet is compared to. */
432 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
433 /**< Pointer to encap/decap resource in cache. */
434 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
435 /**< Pointer to modify header resource in cache. */
436 struct ibv_flow *flow; /**< Installed flow. */
437 struct mlx5_flow_dv_jump_tbl_resource *jump;
438 /**< Pointer to the jump action resource. */
439 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
440 /**< Pointer to port ID action resource. */
441 struct mlx5_vf_vlan vf_vlan;
442 /**< Structure for VF VLAN workaround. */
443 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
444 /**< Pointer to push VLAN action resource in cache. */
445 struct mlx5_flow_dv_tag_resource *tag_resource;
446 /**< pointer to the tag action. */
447 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
448 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
451 int actions_n; /**< number of actions. */
454 /* Verbs specification header. */
455 struct ibv_spec_header {
456 enum ibv_flow_spec_type type;
460 /** Handles information leading to a drop fate. */
461 struct mlx5_flow_verbs {
462 LIST_ENTRY(mlx5_flow_verbs) next;
463 unsigned int size; /**< Size of the attribute. */
465 struct ibv_flow_attr *attr;
466 /**< Pointer to the Specification buffer. */
467 uint8_t *specs; /**< Pointer to the specifications. */
469 struct ibv_flow *flow; /**< Verbs flow pointer. */
470 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
471 struct mlx5_vf_vlan vf_vlan;
472 /**< Structure for VF VLAN workaround. */
475 struct mlx5_flow_rss {
477 uint32_t queue_num; /**< Number of entries in @p queue. */
478 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
479 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
480 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
483 /** Device flow structure. */
485 LIST_ENTRY(mlx5_flow) next;
486 struct rte_flow *flow; /**< Pointer to the main flow. */
488 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
490 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
491 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
492 uint8_t ingress; /**< 1 if the flow is ingress. */
493 uint32_t group; /**< The group index. */
494 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
496 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
497 struct mlx5_flow_dv dv;
499 struct mlx5_flow_verbs verbs;
501 bool external; /**< true if the flow is created external to PMD. */
504 /* Flow structure. */
506 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
507 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
508 struct mlx5_flow_rss rss; /**< RSS context. */
509 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
510 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
511 /**< Device flows that are part of the flow. */
512 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
513 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
516 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
517 const struct rte_flow_attr *attr,
518 const struct rte_flow_item items[],
519 const struct rte_flow_action actions[],
521 struct rte_flow_error *error);
522 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
523 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
524 const struct rte_flow_action actions[], struct rte_flow_error *error);
525 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
526 struct mlx5_flow *dev_flow,
527 const struct rte_flow_attr *attr,
528 const struct rte_flow_item items[],
529 const struct rte_flow_action actions[],
530 struct rte_flow_error *error);
531 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
532 struct rte_flow_error *error);
533 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
534 struct rte_flow *flow);
535 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
536 struct rte_flow *flow);
537 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
538 struct rte_flow *flow,
539 const struct rte_flow_action *actions,
541 struct rte_flow_error *error);
542 struct mlx5_flow_driver_ops {
543 mlx5_flow_validate_t validate;
544 mlx5_flow_prepare_t prepare;
545 mlx5_flow_translate_t translate;
546 mlx5_flow_apply_t apply;
547 mlx5_flow_remove_t remove;
548 mlx5_flow_destroy_t destroy;
549 mlx5_flow_query_t query;
553 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
554 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
555 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
556 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
560 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
561 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
562 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
563 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
565 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
566 bool external, uint32_t group, uint32_t *table,
567 struct rte_flow_error *error);
568 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
569 uint64_t layer_types,
570 uint64_t hash_fields);
571 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
572 uint32_t subpriority);
573 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
574 enum mlx5_feature_name feature,
576 struct rte_flow_error *error);
577 const struct rte_flow_action *mlx5_flow_find_action
578 (const struct rte_flow_action *actions,
579 enum rte_flow_action_type action);
580 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
581 const struct rte_flow_attr *attr,
582 struct rte_flow_error *error);
583 int mlx5_flow_validate_action_drop(uint64_t action_flags,
584 const struct rte_flow_attr *attr,
585 struct rte_flow_error *error);
586 int mlx5_flow_validate_action_flag(uint64_t action_flags,
587 const struct rte_flow_attr *attr,
588 struct rte_flow_error *error);
589 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
590 uint64_t action_flags,
591 const struct rte_flow_attr *attr,
592 struct rte_flow_error *error);
593 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
594 uint64_t action_flags,
595 struct rte_eth_dev *dev,
596 const struct rte_flow_attr *attr,
597 struct rte_flow_error *error);
598 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
599 uint64_t action_flags,
600 struct rte_eth_dev *dev,
601 const struct rte_flow_attr *attr,
603 struct rte_flow_error *error);
604 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
605 const struct rte_flow_attr *attributes,
606 struct rte_flow_error *error);
607 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
609 const uint8_t *nic_mask,
611 struct rte_flow_error *error);
612 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
614 struct rte_flow_error *error);
615 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
617 uint8_t target_protocol,
618 struct rte_flow_error *error);
619 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
621 const struct rte_flow_item *gre_item,
622 struct rte_flow_error *error);
623 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
627 const struct rte_flow_item_ipv4 *acc_mask,
628 struct rte_flow_error *error);
629 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
633 const struct rte_flow_item_ipv6 *acc_mask,
634 struct rte_flow_error *error);
635 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
636 const struct rte_flow_item *item,
639 struct rte_flow_error *error);
640 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
642 uint8_t target_protocol,
643 const struct rte_flow_item_tcp *flow_mask,
644 struct rte_flow_error *error);
645 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
647 uint8_t target_protocol,
648 struct rte_flow_error *error);
649 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
651 struct rte_eth_dev *dev,
652 struct rte_flow_error *error);
653 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
655 struct rte_flow_error *error);
656 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
658 struct rte_eth_dev *dev,
659 struct rte_flow_error *error);
660 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
662 uint8_t target_protocol,
663 struct rte_flow_error *error);
664 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
666 uint8_t target_protocol,
667 struct rte_flow_error *error);
668 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
670 uint8_t target_protocol,
671 struct rte_flow_error *error);
672 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
674 struct rte_eth_dev *dev,
675 struct rte_flow_error *error);
676 #endif /* RTE_PMD_MLX5_FLOW_H_ */