1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* Private rte flow items. */
22 enum mlx5_rte_flow_item_type {
23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
24 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
30 /* Private (internal) rte flow actions. */
31 enum mlx5_rte_flow_action_type {
32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
34 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
38 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
39 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
40 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
43 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
46 MLX5_INDIRECT_ACTION_TYPE_RSS,
47 MLX5_INDIRECT_ACTION_TYPE_AGE,
48 MLX5_INDIRECT_ACTION_TYPE_COUNT,
49 MLX5_INDIRECT_ACTION_TYPE_CT,
52 /* Now, the maximal ports will be supported is 256, action number is 4M. */
53 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100
55 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22
56 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)
58 /* 30-31: type, 22-29: owner port, 0-21: index. */
59 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \
60 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \
61 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \
62 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index))
64 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \
65 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \
66 MLX5_INDIRECT_ACT_CT_OWNER_MASK)
68 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \
69 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))
71 /* Matches on selected register. */
72 struct mlx5_rte_flow_item_tag {
77 /* Modify selected register. */
78 struct mlx5_rte_flow_action_set_tag {
85 struct mlx5_flow_action_copy_mreg {
90 /* Matches on source queue. */
91 struct mlx5_rte_flow_item_tx_queue {
95 /* Feature name to allocate metadata register. */
96 enum mlx5_feature_name {
111 /* Default queue number. */
112 #define MLX5_RSSQ_DEFAULT_NUM 16
114 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
115 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
116 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
117 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
118 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
119 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
121 /* Pattern inner Layer bits. */
122 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
123 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
124 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
125 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
126 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
127 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
129 /* Pattern tunnel Layer bits. */
130 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
131 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
132 #define MLX5_FLOW_LAYER_GRE (1u << 14)
133 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
134 /* List of tunnel Layer bits continued below. */
136 /* General pattern items bits. */
137 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
138 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
139 #define MLX5_FLOW_ITEM_TAG (1u << 18)
140 #define MLX5_FLOW_ITEM_MARK (1u << 19)
142 /* Pattern MISC bits. */
143 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
144 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
145 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
147 /* Pattern tunnel Layer bits (continued). */
148 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
149 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
150 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
151 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
154 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
156 /* Pattern tunnel Layer bits (continued). */
157 #define MLX5_FLOW_LAYER_GTP (1u << 28)
159 /* Pattern eCPRI Layer bit. */
160 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
162 /* IPv6 Fragment Extension Header bit. */
163 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
164 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
166 /* Pattern tunnel Layer bits (continued). */
167 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
168 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
170 /* INTEGRITY item bit */
171 #define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34)
173 /* Conntrack item. */
174 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 35)
177 #define MLX5_FLOW_LAYER_OUTER_L3 \
178 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
179 #define MLX5_FLOW_LAYER_OUTER_L4 \
180 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
181 #define MLX5_FLOW_LAYER_OUTER \
182 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
183 MLX5_FLOW_LAYER_OUTER_L4)
186 #define MLX5_FLOW_LAYER_TUNNEL \
187 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
188 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
189 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
190 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
193 #define MLX5_FLOW_LAYER_INNER_L3 \
194 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
195 #define MLX5_FLOW_LAYER_INNER_L4 \
196 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
197 #define MLX5_FLOW_LAYER_INNER \
198 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
199 MLX5_FLOW_LAYER_INNER_L4)
202 #define MLX5_FLOW_LAYER_L2 \
203 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
204 #define MLX5_FLOW_LAYER_L3_IPV4 \
205 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
206 #define MLX5_FLOW_LAYER_L3_IPV6 \
207 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
208 #define MLX5_FLOW_LAYER_L3 \
209 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
210 #define MLX5_FLOW_LAYER_L4 \
211 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
214 #define MLX5_FLOW_ACTION_DROP (1u << 0)
215 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
216 #define MLX5_FLOW_ACTION_RSS (1u << 2)
217 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
218 #define MLX5_FLOW_ACTION_MARK (1u << 4)
219 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
220 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
221 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
222 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
223 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
224 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
225 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
226 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
227 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
228 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
229 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
230 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
231 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
232 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
233 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
234 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
235 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
236 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
237 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
238 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
239 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
240 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
241 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
242 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
243 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
244 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
245 #define MLX5_FLOW_ACTION_METER (1ull << 31)
246 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
247 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
248 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
249 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
250 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
251 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
252 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
253 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
254 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
255 #define MLX5_FLOW_ACTION_CT (1ull << 41)
257 #define MLX5_FLOW_FATE_ACTIONS \
258 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
259 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
260 MLX5_FLOW_ACTION_DEFAULT_MISS | \
261 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
263 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
264 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
265 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
267 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
268 MLX5_FLOW_ACTION_SET_IPV4_DST | \
269 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
270 MLX5_FLOW_ACTION_SET_IPV6_DST | \
271 MLX5_FLOW_ACTION_SET_TP_SRC | \
272 MLX5_FLOW_ACTION_SET_TP_DST | \
273 MLX5_FLOW_ACTION_SET_TTL | \
274 MLX5_FLOW_ACTION_DEC_TTL | \
275 MLX5_FLOW_ACTION_SET_MAC_SRC | \
276 MLX5_FLOW_ACTION_SET_MAC_DST | \
277 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
278 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
279 MLX5_FLOW_ACTION_INC_TCP_ACK | \
280 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
281 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
282 MLX5_FLOW_ACTION_SET_TAG | \
283 MLX5_FLOW_ACTION_MARK_EXT | \
284 MLX5_FLOW_ACTION_SET_META | \
285 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
286 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
287 MLX5_FLOW_ACTION_MODIFY_FIELD)
289 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
290 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
292 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
295 #define IPPROTO_MPLS 137
298 /* UDP port number for MPLS */
299 #define MLX5_UDP_PORT_MPLS 6635
301 /* UDP port numbers for VxLAN. */
302 #define MLX5_UDP_PORT_VXLAN 4789
303 #define MLX5_UDP_PORT_VXLAN_GPE 4790
305 /* UDP port numbers for GENEVE. */
306 #define MLX5_UDP_PORT_GENEVE 6081
308 /* Lowest priority indicator. */
309 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
312 * Max priority for ingress\egress flow groups
313 * greater than 0 and for any transfer flow group.
314 * From user configation: 0 - 21843.
316 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
319 * Number of sub priorities.
320 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
321 * matching on the NIC (firmware dependent) L4 most have the higher priority
322 * followed by L3 and ending with L2.
324 #define MLX5_PRIORITY_MAP_L2 2
325 #define MLX5_PRIORITY_MAP_L3 1
326 #define MLX5_PRIORITY_MAP_L4 0
327 #define MLX5_PRIORITY_MAP_MAX 3
329 /* Valid layer type for IPV4 RSS. */
330 #define MLX5_IPV4_LAYER_TYPES \
331 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
332 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
333 ETH_RSS_NONFRAG_IPV4_OTHER)
335 /* IBV hash source bits for IPV4. */
336 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
338 /* Valid layer type for IPV6 RSS. */
339 #define MLX5_IPV6_LAYER_TYPES \
340 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
341 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
342 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
344 /* IBV hash source bits for IPV6. */
345 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
347 /* IBV hash bits for L3 SRC. */
348 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
350 /* IBV hash bits for L3 DST. */
351 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
353 /* IBV hash bits for TCP. */
354 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
355 IBV_RX_HASH_DST_PORT_TCP)
357 /* IBV hash bits for UDP. */
358 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
359 IBV_RX_HASH_DST_PORT_UDP)
361 /* IBV hash bits for L4 SRC. */
362 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
363 IBV_RX_HASH_SRC_PORT_UDP)
365 /* IBV hash bits for L4 DST. */
366 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
367 IBV_RX_HASH_DST_PORT_UDP)
369 /* Geneve header first 16Bit */
370 #define MLX5_GENEVE_VER_MASK 0x3
371 #define MLX5_GENEVE_VER_SHIFT 14
372 #define MLX5_GENEVE_VER_VAL(a) \
373 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
374 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
375 #define MLX5_GENEVE_OPTLEN_SHIFT 8
376 #define MLX5_GENEVE_OPTLEN_VAL(a) \
377 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
378 #define MLX5_GENEVE_OAMF_MASK 0x1
379 #define MLX5_GENEVE_OAMF_SHIFT 7
380 #define MLX5_GENEVE_OAMF_VAL(a) \
381 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
382 #define MLX5_GENEVE_CRITO_MASK 0x1
383 #define MLX5_GENEVE_CRITO_SHIFT 6
384 #define MLX5_GENEVE_CRITO_VAL(a) \
385 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
386 #define MLX5_GENEVE_RSVD_MASK 0x3F
387 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
389 * The length of the Geneve options fields, expressed in four byte multiples,
390 * not including the eight byte fixed tunnel.
392 #define MLX5_GENEVE_OPT_LEN_0 14
393 #define MLX5_GENEVE_OPT_LEN_1 63
395 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
396 sizeof(struct rte_ipv4_hdr))
397 /* GTP extension header flag. */
398 #define MLX5_GTP_EXT_HEADER_FLAG 4
400 /* GTP extension header max PDU type value. */
401 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
403 /* GTP extension header PDU type shift. */
404 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
406 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
407 #define MLX5_IPV4_FRAG_OFFSET_MASK \
408 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
410 /* Specific item's fields can accept a range of values (using spec and last). */
411 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
412 #define MLX5_ITEM_RANGE_ACCEPTED true
414 /* Software header modify action numbers of a flow. */
415 #define MLX5_ACT_NUM_MDF_IPV4 1
416 #define MLX5_ACT_NUM_MDF_IPV6 4
417 #define MLX5_ACT_NUM_MDF_MAC 2
418 #define MLX5_ACT_NUM_MDF_VID 1
419 #define MLX5_ACT_NUM_MDF_PORT 2
420 #define MLX5_ACT_NUM_MDF_TTL 1
421 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
422 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
423 #define MLX5_ACT_NUM_MDF_TCPACK 1
424 #define MLX5_ACT_NUM_SET_REG 1
425 #define MLX5_ACT_NUM_SET_TAG 1
426 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
427 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
428 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
429 #define MLX5_ACT_NUM_SET_DSCP 1
431 /* Maximum number of fields to modify in MODIFY_FIELD */
432 #define MLX5_ACT_MAX_MOD_FIELDS 5
434 /* Syndrome bits definition for connection tracking. */
435 #define MLX5_CT_SYNDROME_VALID (0x0 << 6)
436 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6)
437 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6)
438 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1)
439 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0)
441 enum mlx5_flow_drv_type {
444 MLX5_FLOW_TYPE_VERBS,
448 /* Fate action type. */
449 enum mlx5_flow_fate_type {
450 MLX5_FLOW_FATE_NONE, /* Egress flow. */
451 MLX5_FLOW_FATE_QUEUE,
453 MLX5_FLOW_FATE_PORT_ID,
455 MLX5_FLOW_FATE_DEFAULT_MISS,
456 MLX5_FLOW_FATE_SHARED_RSS,
460 /* Matcher PRM representation */
461 struct mlx5_flow_dv_match_params {
463 /**< Size of match value. Do NOT split size and key! */
464 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
465 /**< Matcher value. This value is used as the mask or as a key. */
468 /* Matcher structure. */
469 struct mlx5_flow_dv_matcher {
470 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
471 struct mlx5_flow_tbl_resource *tbl;
472 /**< Pointer to the table(group) the matcher associated with. */
473 void *matcher_object; /**< Pointer to DV matcher */
474 uint16_t crc; /**< CRC of key. */
475 uint16_t priority; /**< Priority of matcher. */
476 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
479 #define MLX5_ENCAP_MAX_LEN 132
481 /* Encap/decap resource structure. */
482 struct mlx5_flow_dv_encap_decap_resource {
483 struct mlx5_hlist_entry entry;
484 /* Pointer to next element. */
485 uint32_t refcnt; /**< Reference counter. */
487 /**< Encap/decap action object. */
488 uint8_t buf[MLX5_ENCAP_MAX_LEN];
490 uint8_t reformat_type;
492 uint64_t flags; /**< Flags for RDMA API. */
493 uint32_t idx; /**< Index for the index memory pool. */
496 /* Tag resource structure. */
497 struct mlx5_flow_dv_tag_resource {
498 struct mlx5_hlist_entry entry;
499 /**< hash list entry for tag resource, tag value as the key. */
501 /**< Tag action object. */
502 uint32_t refcnt; /**< Reference counter. */
503 uint32_t idx; /**< Index for the index memory pool. */
504 uint32_t tag_id; /**< Tag ID. */
508 * Number of modification commands.
509 * The maximal actions amount in FW is some constant, and it is 16 in the
510 * latest releases. In some old releases, it will be limited to 8.
511 * Since there is no interface to query the capacity, the maximal value should
512 * be used to allow PMD to create the flow. The validation will be done in the
513 * lower driver layer or FW. A failure will be returned if exceeds the maximal
514 * supported actions number on the root table.
515 * On non-root tables, there is no limitation, but 32 is enough right now.
517 #define MLX5_MAX_MODIFY_NUM 32
518 #define MLX5_ROOT_TBL_MODIFY_NUM 16
520 /* Modify resource structure */
521 struct mlx5_flow_dv_modify_hdr_resource {
522 struct mlx5_hlist_entry entry;
523 void *action; /**< Modify header action object. */
524 /* Key area for hash list matching: */
525 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
526 uint32_t actions_num; /**< Number of modification actions. */
527 uint64_t flags; /**< Flags for RDMA API. */
528 struct mlx5_modification_cmd actions[];
529 /**< Modification actions. */
532 /* Modify resource key of the hash organization. */
533 union mlx5_flow_modify_hdr_key {
535 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
536 uint32_t actions_num:5; /**< Number of modification actions. */
537 uint32_t group:19; /**< Flow group id. */
538 uint32_t cksum; /**< Actions check sum. */
540 uint64_t v64; /**< full 64bits value of key */
543 /* Jump action resource structure. */
544 struct mlx5_flow_dv_jump_tbl_resource {
545 void *action; /**< Pointer to the rdma core action. */
548 /* Port ID resource structure. */
549 struct mlx5_flow_dv_port_id_action_resource {
550 struct mlx5_cache_entry entry;
551 void *action; /**< Action object. */
552 uint32_t port_id; /**< Port ID value. */
553 uint32_t idx; /**< Indexed pool memory index. */
556 /* Push VLAN action resource structure */
557 struct mlx5_flow_dv_push_vlan_action_resource {
558 struct mlx5_cache_entry entry; /* Cache entry. */
559 void *action; /**< Action object. */
560 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
561 rte_be32_t vlan_tag; /**< VLAN tag value. */
562 uint32_t idx; /**< Indexed pool memory index. */
565 /* Metadata register copy table entry. */
566 struct mlx5_flow_mreg_copy_resource {
568 * Hash list entry for copy table.
569 * - Key is 32/64-bit MARK action ID.
570 * - MUST be the first entry.
572 struct mlx5_hlist_entry hlist_ent;
573 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
574 /* List entry for device flows. */
576 uint32_t rix_flow; /* Built flow for copy. */
580 /* Table tunnel parameter. */
581 struct mlx5_flow_tbl_tunnel_prm {
582 const struct mlx5_flow_tunnel *tunnel;
587 /* Table data structure of the hash organization. */
588 struct mlx5_flow_tbl_data_entry {
589 struct mlx5_hlist_entry entry;
590 /**< hash list entry, 64-bits key inside. */
591 struct mlx5_flow_tbl_resource tbl;
592 /**< flow table resource. */
593 struct mlx5_cache_list matchers;
594 /**< matchers' header associated with the flow table. */
595 struct mlx5_flow_dv_jump_tbl_resource jump;
596 /**< jump resource, at most one for each table created. */
597 uint32_t idx; /**< index for the indexed mempool. */
598 /**< tunnel offload */
599 const struct mlx5_flow_tunnel *tunnel;
602 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
603 uint32_t is_egress:1; /**< Egress table. */
604 uint32_t is_transfer:1; /**< Transfer table. */
605 uint32_t dummy:1; /**< DR table. */
606 uint32_t id:22; /**< Table ID. */
607 uint32_t reserve:5; /**< Reserved to future using. */
608 uint32_t level; /**< Table level. */
611 /* Sub rdma-core actions list. */
612 struct mlx5_flow_sub_actions_list {
613 uint32_t actions_num; /**< Number of sample actions. */
614 uint64_t action_flags;
615 void *dr_queue_action;
618 void *dr_port_id_action;
619 void *dr_encap_action;
620 void *dr_jump_action;
623 /* Sample sub-actions resource list. */
624 struct mlx5_flow_sub_actions_idx {
625 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
626 uint32_t rix_tag; /**< Index to the tag action. */
627 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
628 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
629 uint32_t rix_jump; /**< Index to the jump action resource. */
632 /* Sample action resource structure. */
633 struct mlx5_flow_dv_sample_resource {
634 struct mlx5_cache_entry entry; /**< Cache entry. */
636 void *verbs_action; /**< Verbs sample action object. */
637 void **sub_actions; /**< Sample sub-action array. */
639 struct rte_eth_dev *dev; /**< Device registers the action. */
640 uint32_t idx; /** Sample object index. */
641 uint8_t ft_type; /** Flow Table Type */
642 uint32_t ft_id; /** Flow Table Level */
643 uint32_t ratio; /** Sample Ratio */
644 uint64_t set_action; /** Restore reg_c0 value */
645 void *normal_path_tbl; /** Flow Table pointer */
646 struct mlx5_flow_sub_actions_idx sample_idx;
647 /**< Action index resources. */
648 struct mlx5_flow_sub_actions_list sample_act;
649 /**< Action resources. */
652 #define MLX5_MAX_DEST_NUM 2
654 /* Destination array action resource structure. */
655 struct mlx5_flow_dv_dest_array_resource {
656 struct mlx5_cache_entry entry; /**< Cache entry. */
657 uint32_t idx; /** Destination array action object index. */
658 uint8_t ft_type; /** Flow Table Type */
659 uint8_t num_of_dest; /**< Number of destination actions. */
660 struct rte_eth_dev *dev; /**< Device registers the action. */
661 void *action; /**< Pointer to the rdma core action. */
662 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
663 /**< Action index resources. */
664 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
665 /**< Action resources. */
668 /* PMD flow priority for tunnel */
669 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
670 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
673 /** Device flow handle structure for DV mode only. */
674 struct mlx5_flow_handle_dv {
676 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
677 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
678 /**< Pointer to modify header resource in cache. */
679 uint32_t rix_encap_decap;
680 /**< Index to encap/decap resource in cache. */
681 uint32_t rix_push_vlan;
682 /**< Index to push VLAN action resource in cache. */
684 /**< Index to the tag action. */
686 /**< Index to sample action resource in cache. */
687 uint32_t rix_dest_array;
688 /**< Index to destination array resource in cache. */
691 /** Device flow handle structure: used both for creating & destroying. */
692 struct mlx5_flow_handle {
693 SILIST_ENTRY(uint32_t)next;
694 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
695 /**< Index to next device flow handle. */
697 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
698 void *drv_flow; /**< pointer to driver flow object. */
699 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
700 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
701 uint32_t mark:1; /**< Metadate rxq mark flag. */
702 uint32_t fate_action:3; /**< Fate action type. */
704 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
705 uint32_t rix_jump; /**< Index to the jump action resource. */
706 uint32_t rix_port_id_action;
707 /**< Index to port ID action resource. */
709 /**< Generic value indicates the fate action. */
710 uint32_t rix_default_fate;
711 /**< Indicates default miss fate action. */
713 /**< Indicates shared RSS fate action. */
715 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
716 struct mlx5_flow_handle_dv dvh;
721 * Size for Verbs device flow handle structure only. Do not use the DV only
722 * structure in Verbs. No DV flows attributes will be accessed.
723 * Macro offsetof() could also be used here.
725 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
726 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
727 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
729 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
732 /** Device flow structure only for DV flow creation. */
733 struct mlx5_flow_dv_workspace {
734 uint32_t group; /**< The group index. */
735 uint32_t table_id; /**< Flow table identifier. */
736 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
737 int actions_n; /**< number of actions. */
738 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
739 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
740 /**< Pointer to encap/decap resource in cache. */
741 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
742 /**< Pointer to push VLAN action resource in cache. */
743 struct mlx5_flow_dv_tag_resource *tag_resource;
744 /**< pointer to the tag action. */
745 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
746 /**< Pointer to port ID action resource. */
747 struct mlx5_flow_dv_jump_tbl_resource *jump;
748 /**< Pointer to the jump action resource. */
749 struct mlx5_flow_dv_match_params value;
750 /**< Holds the value that the packet is compared to. */
751 struct mlx5_flow_dv_sample_resource *sample_res;
752 /**< Pointer to the sample action resource. */
753 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
754 /**< Pointer to the destination array resource. */
757 #ifdef HAVE_INFINIBAND_VERBS_H
759 * Maximal Verbs flow specifications & actions size.
760 * Some elements are mutually exclusive, but enough space should be allocated.
761 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
762 * 2. One tunnel header (exception: GRE + MPLS),
763 * SPEC length: GRE == tunnel.
764 * Actions: 1. 1 Mark OR Flag.
765 * 2. 1 Drop (if any).
766 * 3. No limitation for counters, but it makes no sense to support too
767 * many counters in a single device flow.
769 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
770 #define MLX5_VERBS_MAX_SPEC_SIZE \
772 (2 * (sizeof(struct ibv_flow_spec_eth) + \
773 sizeof(struct ibv_flow_spec_ipv6) + \
774 sizeof(struct ibv_flow_spec_tcp_udp)) + \
775 sizeof(struct ibv_flow_spec_gre) + \
776 sizeof(struct ibv_flow_spec_mpls)) \
779 #define MLX5_VERBS_MAX_SPEC_SIZE \
781 (2 * (sizeof(struct ibv_flow_spec_eth) + \
782 sizeof(struct ibv_flow_spec_ipv6) + \
783 sizeof(struct ibv_flow_spec_tcp_udp)) + \
784 sizeof(struct ibv_flow_spec_tunnel)) \
788 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
789 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
790 #define MLX5_VERBS_MAX_ACT_SIZE \
792 sizeof(struct ibv_flow_spec_action_tag) + \
793 sizeof(struct ibv_flow_spec_action_drop) + \
794 sizeof(struct ibv_flow_spec_counter_action) * 4 \
797 #define MLX5_VERBS_MAX_ACT_SIZE \
799 sizeof(struct ibv_flow_spec_action_tag) + \
800 sizeof(struct ibv_flow_spec_action_drop) \
804 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
805 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
807 /** Device flow structure only for Verbs flow creation. */
808 struct mlx5_flow_verbs_workspace {
809 unsigned int size; /**< Size of the attribute. */
810 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
811 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
812 /**< Specifications & actions buffer of verbs flow. */
814 #endif /* HAVE_INFINIBAND_VERBS_H */
816 #define MLX5_SCALE_FLOW_GROUP_BIT 0
817 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
819 /** Maximal number of device sub-flows supported. */
820 #define MLX5_NUM_MAX_DEV_FLOWS 32
823 * tunnel offload rules type
825 enum mlx5_tof_rule_type {
826 MLX5_TUNNEL_OFFLOAD_NONE = 0,
827 MLX5_TUNNEL_OFFLOAD_SET_RULE,
828 MLX5_TUNNEL_OFFLOAD_MATCH_RULE,
829 MLX5_TUNNEL_OFFLOAD_MISS_RULE,
832 /** Device flow structure. */
835 struct rte_flow *flow; /**< Pointer to the main flow. */
836 uint32_t flow_idx; /**< The memory pool index to the main flow. */
837 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
839 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
840 bool external; /**< true if the flow is created external to PMD. */
841 uint8_t ingress:1; /**< 1 if the flow is ingress. */
842 uint8_t skip_scale:2;
844 * Each Bit be set to 1 if Skip the scale the flow group with factor.
845 * If bit0 be set to 1, then skip the scale the original flow group;
846 * If bit1 be set to 1, then skip the scale the jump flow group if
847 * having jump action.
848 * 00: Enable scale in a flow, default value.
849 * 01: Skip scale the flow group with factor, enable scale the group
851 * 10: Enable scale the group with factor, skip scale the group of
853 * 11: Skip scale the table with factor both for flow group and jump
857 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
858 struct mlx5_flow_dv_workspace dv;
860 #ifdef HAVE_INFINIBAND_VERBS_H
861 struct mlx5_flow_verbs_workspace verbs;
864 struct mlx5_flow_handle *handle;
865 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
866 const struct mlx5_flow_tunnel *tunnel;
867 enum mlx5_tof_rule_type tof_type;
870 /* Flow meter state. */
871 #define MLX5_FLOW_METER_DISABLE 0
872 #define MLX5_FLOW_METER_ENABLE 1
874 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
875 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
877 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
879 #define MLX5_MAN_WIDTH 8
880 /* Legacy Meter parameter structure. */
881 struct mlx5_legacy_flow_meter {
882 struct mlx5_flow_meter_info fm;
883 /* Must be the first in struct. */
884 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
885 /**< Pointer to the next flow meter structure. */
887 /* Index to meter object. */
890 #define MLX5_MAX_TUNNELS 256
891 #define MLX5_TNL_MISS_RULE_PRIORITY 3
892 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
895 * When tunnel offload is active, all JUMP group ids are converted
896 * using the same method. That conversion is applied both to tunnel and
897 * regular rule types.
898 * Group ids used in tunnel rules are relative to it's tunnel (!).
899 * Application can create number of steer rules, using the same
900 * tunnel, with different group id in each rule.
901 * Each tunnel stores its groups internally in PMD tunnel object.
902 * Groups used in regular rules do not belong to any tunnel and are stored
906 struct mlx5_flow_tunnel {
907 LIST_ENTRY(mlx5_flow_tunnel) chain;
908 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
909 uint32_t tunnel_id; /** unique tunnel ID */
911 struct rte_flow_action action;
912 struct rte_flow_item item;
913 struct mlx5_hlist *groups; /** tunnel groups */
916 /** PMD tunnel related context */
917 struct mlx5_flow_tunnel_hub {
919 * Access to the list MUST be MT protected
921 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
922 /* protect access to the tunnels list */
924 struct mlx5_hlist *groups; /** non tunnel groups */
927 /* convert jump group to flow table ID in tunnel rules */
928 struct tunnel_tbl_entry {
929 struct mlx5_hlist_entry hash;
935 static inline uint32_t
936 tunnel_id_to_flow_tbl(uint32_t id)
938 return id | (1u << 16);
941 static inline uint32_t
942 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
944 return flow_tbl & ~(1u << 16);
947 union tunnel_tbl_key {
955 static inline struct mlx5_flow_tunnel_hub *
956 mlx5_tunnel_hub(struct rte_eth_dev *dev)
958 struct mlx5_priv *priv = dev->data->dev_private;
959 return priv->sh->tunnel_hub;
963 is_tunnel_offload_active(const struct rte_eth_dev *dev)
965 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
966 const struct mlx5_priv *priv = dev->data->dev_private;
967 return !!priv->config.dv_miss_info;
975 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type)
977 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE;
981 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type)
983 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE;
986 static inline const struct mlx5_flow_tunnel *
987 flow_actions_to_tunnel(const struct rte_flow_action actions[])
989 return actions[0].conf;
992 static inline const struct mlx5_flow_tunnel *
993 flow_items_to_tunnel(const struct rte_flow_item items[])
995 return items[0].spec;
998 /* Flow structure. */
1000 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1001 uint32_t dev_handles;
1002 /**< Device flow handles that are part of the flow. */
1003 uint32_t drv_type:2; /**< Driver type. */
1005 uint32_t meter:24; /**< Holds flow meter id. */
1006 uint32_t indirect_type:2; /**< Indirect action type. */
1007 uint32_t rix_mreg_copy;
1008 /**< Index to metadata register copy table resource. */
1009 uint32_t counter; /**< Holds flow counter. */
1010 uint32_t tunnel_id; /**< Tunnel id */
1012 uint32_t age; /**< Holds ASO age bit index. */
1013 uint32_t ct; /**< Holds ASO CT index. */
1015 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1019 * Define list of valid combinations of RX Hash fields
1020 * (see enum ibv_rx_hash_fields).
1022 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1023 #define MLX5_RSS_HASH_IPV4_TCP \
1024 (MLX5_RSS_HASH_IPV4 | \
1025 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1026 #define MLX5_RSS_HASH_IPV4_UDP \
1027 (MLX5_RSS_HASH_IPV4 | \
1028 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1029 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1030 #define MLX5_RSS_HASH_IPV6_TCP \
1031 (MLX5_RSS_HASH_IPV6 | \
1032 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1033 #define MLX5_RSS_HASH_IPV6_UDP \
1034 (MLX5_RSS_HASH_IPV6 | \
1035 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1036 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1037 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1038 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1039 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1040 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1041 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1042 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1043 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1044 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1045 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1046 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1047 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1048 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1049 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1050 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1051 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1052 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1053 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1054 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1055 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1056 #define MLX5_RSS_HASH_NONE 0ULL
1059 /* extract next protocol type from Ethernet & VLAN headers */
1060 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1061 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1062 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1063 (_prt) = rte_be_to_cpu_16((_prt)); \
1066 /* array of valid combinations of RX Hash fields for RSS */
1067 static const uint64_t mlx5_rss_hash_fields[] = {
1069 MLX5_RSS_HASH_IPV4_TCP,
1070 MLX5_RSS_HASH_IPV4_UDP,
1072 MLX5_RSS_HASH_IPV6_TCP,
1073 MLX5_RSS_HASH_IPV6_UDP,
1077 /* Shared RSS action structure */
1078 struct mlx5_shared_action_rss {
1079 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1080 uint32_t refcnt; /**< Atomically accessed refcnt. */
1081 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1082 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1083 struct mlx5_ind_table_obj *ind_tbl;
1084 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1085 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1086 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1087 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1090 struct rte_flow_action_handle {
1094 /* Thread specific flow workspace intermediate data. */
1095 struct mlx5_flow_workspace {
1096 /* If creating another flow in same thread, push new as stack. */
1097 struct mlx5_flow_workspace *prev;
1098 struct mlx5_flow_workspace *next;
1099 uint32_t inuse; /* can't create new flow with current. */
1100 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1101 struct mlx5_flow_rss_desc rss_desc;
1102 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1103 uint32_t flow_idx; /* Intermediate device flow index. */
1104 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1105 uint32_t skip_matcher_reg:1;
1106 /* Indicates if need to skip matcher register in translate. */
1109 struct mlx5_flow_split_info {
1111 /**< True if flow is created by request external to PMD. */
1112 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1113 uint32_t flow_idx; /**< This memory pool index to the flow. */
1114 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1115 uint64_t prefix_layers; /**< Prefix subflow layers. */
1116 uint32_t table_id; /**< Flow table identifier. */
1119 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1120 const struct rte_flow_attr *attr,
1121 const struct rte_flow_item items[],
1122 const struct rte_flow_action actions[],
1125 struct rte_flow_error *error);
1126 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1127 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1128 const struct rte_flow_item items[],
1129 const struct rte_flow_action actions[], struct rte_flow_error *error);
1130 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1131 struct mlx5_flow *dev_flow,
1132 const struct rte_flow_attr *attr,
1133 const struct rte_flow_item items[],
1134 const struct rte_flow_action actions[],
1135 struct rte_flow_error *error);
1136 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1137 struct rte_flow_error *error);
1138 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1139 struct rte_flow *flow);
1140 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1141 struct rte_flow *flow);
1142 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1143 struct rte_flow *flow,
1144 const struct rte_flow_action *actions,
1146 struct rte_flow_error *error);
1147 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1148 struct mlx5_flow_meter_info *fm,
1150 uint8_t domain_bitmap);
1151 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1152 struct mlx5_flow_meter_info *fm);
1153 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1154 typedef struct mlx5_flow_meter_sub_policy *
1155 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1156 (struct rte_eth_dev *dev,
1157 struct mlx5_flow_meter_policy *mtr_policy,
1158 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1159 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1160 (struct rte_eth_dev *dev);
1161 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1163 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1164 (struct rte_eth_dev *dev);
1165 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1167 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1169 bool clear, uint64_t *pkts,
1171 typedef int (*mlx5_flow_get_aged_flows_t)
1172 (struct rte_eth_dev *dev,
1174 uint32_t nb_contexts,
1175 struct rte_flow_error *error);
1176 typedef int (*mlx5_flow_action_validate_t)
1177 (struct rte_eth_dev *dev,
1178 const struct rte_flow_indir_action_conf *conf,
1179 const struct rte_flow_action *action,
1180 struct rte_flow_error *error);
1181 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1182 (struct rte_eth_dev *dev,
1183 const struct rte_flow_indir_action_conf *conf,
1184 const struct rte_flow_action *action,
1185 struct rte_flow_error *error);
1186 typedef int (*mlx5_flow_action_destroy_t)
1187 (struct rte_eth_dev *dev,
1188 struct rte_flow_action_handle *action,
1189 struct rte_flow_error *error);
1190 typedef int (*mlx5_flow_action_update_t)
1191 (struct rte_eth_dev *dev,
1192 struct rte_flow_action_handle *action,
1194 struct rte_flow_error *error);
1195 typedef int (*mlx5_flow_action_query_t)
1196 (struct rte_eth_dev *dev,
1197 const struct rte_flow_action_handle *action,
1199 struct rte_flow_error *error);
1200 typedef int (*mlx5_flow_sync_domain_t)
1201 (struct rte_eth_dev *dev,
1204 typedef int (*mlx5_flow_validate_mtr_acts_t)
1205 (struct rte_eth_dev *dev,
1206 const struct rte_flow_action *actions[RTE_COLORS],
1207 struct rte_flow_attr *attr,
1209 uint8_t *domain_bitmap,
1210 bool *is_def_policy,
1211 struct rte_mtr_error *error);
1212 typedef int (*mlx5_flow_create_mtr_acts_t)
1213 (struct rte_eth_dev *dev,
1214 struct mlx5_flow_meter_policy *mtr_policy,
1215 const struct rte_flow_action *actions[RTE_COLORS],
1216 struct rte_mtr_error *error);
1217 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1218 (struct rte_eth_dev *dev,
1219 struct mlx5_flow_meter_policy *mtr_policy);
1220 typedef int (*mlx5_flow_create_policy_rules_t)
1221 (struct rte_eth_dev *dev,
1222 struct mlx5_flow_meter_policy *mtr_policy);
1223 typedef void (*mlx5_flow_destroy_policy_rules_t)
1224 (struct rte_eth_dev *dev,
1225 struct mlx5_flow_meter_policy *mtr_policy);
1226 typedef int (*mlx5_flow_create_def_policy_t)
1227 (struct rte_eth_dev *dev);
1228 typedef void (*mlx5_flow_destroy_def_policy_t)
1229 (struct rte_eth_dev *dev);
1231 struct mlx5_flow_driver_ops {
1232 mlx5_flow_validate_t validate;
1233 mlx5_flow_prepare_t prepare;
1234 mlx5_flow_translate_t translate;
1235 mlx5_flow_apply_t apply;
1236 mlx5_flow_remove_t remove;
1237 mlx5_flow_destroy_t destroy;
1238 mlx5_flow_query_t query;
1239 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1240 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1241 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1242 mlx5_flow_mtr_alloc_t create_meter;
1243 mlx5_flow_mtr_free_t free_meter;
1244 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1245 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1246 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1247 mlx5_flow_create_policy_rules_t create_policy_rules;
1248 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1249 mlx5_flow_create_def_policy_t create_def_policy;
1250 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1251 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1252 mlx5_flow_counter_alloc_t counter_alloc;
1253 mlx5_flow_counter_free_t counter_free;
1254 mlx5_flow_counter_query_t counter_query;
1255 mlx5_flow_get_aged_flows_t get_aged_flows;
1256 mlx5_flow_action_validate_t action_validate;
1257 mlx5_flow_action_create_t action_create;
1258 mlx5_flow_action_destroy_t action_destroy;
1259 mlx5_flow_action_update_t action_update;
1260 mlx5_flow_action_query_t action_query;
1261 mlx5_flow_sync_domain_t sync_domain;
1266 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1268 struct flow_grp_info {
1269 uint64_t external:1;
1270 uint64_t transfer:1;
1271 uint64_t fdb_def_rule:1;
1272 /* force standard group translation */
1273 uint64_t std_tbl_fix:1;
1274 uint64_t skip_scale:2;
1278 tunnel_use_standard_attr_group_translate
1279 (const struct rte_eth_dev *dev,
1280 const struct rte_flow_attr *attr,
1281 const struct mlx5_flow_tunnel *tunnel,
1282 enum mlx5_tof_rule_type tof_rule_type)
1286 if (!is_tunnel_offload_active(dev))
1287 /* no tunnel offload API */
1291 * OvS will use jump to group 0 in tunnel steer rule.
1292 * If tunnel steer rule starts from group 0 (attr.group == 0)
1293 * that 0 group must be translated with standard method.
1294 * attr.group == 0 in tunnel match rule translated with tunnel
1297 verdict = !attr->group &&
1298 is_flow_tunnel_steer_rule(tof_rule_type);
1301 * non-tunnel group translation uses standard method for
1302 * root group only: attr.group == 0
1304 verdict = !attr->group;
1311 * Get DV flow aso meter by index.
1314 * Pointer to the Ethernet device structure.
1316 * mlx5 flow aso meter index in the container.
1318 * mlx5 flow aso meter pool in the container,
1321 * Pointer to the aso meter, NULL otherwise.
1323 static inline struct mlx5_aso_mtr *
1324 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1326 struct mlx5_aso_mtr_pool *pool;
1327 struct mlx5_aso_mtr_pools_mng *pools_mng =
1328 &priv->sh->mtrmng->pools_mng;
1330 /* Decrease to original index. */
1332 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1333 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1334 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1337 static __rte_always_inline const struct rte_flow_item *
1338 mlx5_find_end_item(const struct rte_flow_item *item)
1340 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1344 static __rte_always_inline bool
1345 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1347 struct rte_flow_item_integrity test = *item;
1350 test.ipv4_csum_ok = 0;
1351 test.l4_csum_ok = 0;
1352 return (test.value == 0);
1356 * Get ASO CT action by device and index.
1359 * Pointer to the Ethernet device structure.
1361 * Index to the ASO CT action.
1364 * The specified ASO CT action pointer.
1366 static inline struct mlx5_aso_ct_action *
1367 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx)
1369 struct mlx5_priv *priv = dev->data->dev_private;
1370 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
1371 struct mlx5_aso_ct_pool *pool;
1374 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n);
1375 /* Bit operation AND could be used. */
1376 rte_rwlock_read_lock(&mng->resize_rwl);
1377 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL];
1378 rte_rwlock_read_unlock(&mng->resize_rwl);
1379 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];
1383 * Get ASO CT action by owner & index.
1386 * Pointer to the Ethernet device structure.
1388 * Index to the ASO CT action and owner port combination.
1391 * The specified ASO CT action pointer.
1393 static inline struct mlx5_aso_ct_action *
1394 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx)
1396 struct mlx5_priv *priv = dev->data->dev_private;
1397 struct mlx5_aso_ct_action *ct;
1398 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
1399 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
1401 if (owner == PORT_ID(priv)) {
1402 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
1404 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
1406 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
1407 if (dev->data->dev_started != 1)
1409 ct = flow_aso_ct_get_by_dev_idx(owndev, idx);
1410 if (ct->peer != PORT_ID(priv))
1416 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1417 const struct mlx5_flow_tunnel *tunnel,
1418 uint32_t group, uint32_t *table,
1419 const struct flow_grp_info *flags,
1420 struct rte_flow_error *error);
1421 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1422 int tunnel, uint64_t layer_types,
1423 uint64_t hash_fields);
1424 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1425 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1426 uint32_t subpriority);
1427 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1428 const struct rte_flow_attr *attr);
1429 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1430 const struct rte_flow_attr *attr,
1431 uint32_t subpriority);
1432 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1433 enum mlx5_feature_name feature,
1435 struct rte_flow_error *error);
1436 const struct rte_flow_action *mlx5_flow_find_action
1437 (const struct rte_flow_action *actions,
1438 enum rte_flow_action_type action);
1439 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1440 const struct rte_flow_action *action,
1441 struct rte_flow_error *error);
1442 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1443 const struct rte_flow_attr *attr,
1444 struct rte_flow_error *error);
1445 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1446 const struct rte_flow_attr *attr,
1447 struct rte_flow_error *error);
1448 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1449 const struct rte_flow_attr *attr,
1450 struct rte_flow_error *error);
1451 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1452 uint64_t action_flags,
1453 const struct rte_flow_attr *attr,
1454 struct rte_flow_error *error);
1455 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1456 uint64_t action_flags,
1457 struct rte_eth_dev *dev,
1458 const struct rte_flow_attr *attr,
1459 struct rte_flow_error *error);
1460 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1461 uint64_t action_flags,
1462 struct rte_eth_dev *dev,
1463 const struct rte_flow_attr *attr,
1464 uint64_t item_flags,
1465 struct rte_flow_error *error);
1466 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1467 const struct rte_flow_attr *attr,
1468 struct rte_flow_error *error);
1469 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1470 const struct rte_flow_attr *attributes,
1471 struct rte_flow_error *error);
1472 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1473 const uint8_t *mask,
1474 const uint8_t *nic_mask,
1476 bool range_accepted,
1477 struct rte_flow_error *error);
1478 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1479 uint64_t item_flags, bool ext_vlan_sup,
1480 struct rte_flow_error *error);
1481 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1482 uint64_t item_flags,
1483 uint8_t target_protocol,
1484 struct rte_flow_error *error);
1485 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1486 uint64_t item_flags,
1487 const struct rte_flow_item *gre_item,
1488 struct rte_flow_error *error);
1489 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1490 uint64_t item_flags,
1492 uint16_t ether_type,
1493 const struct rte_flow_item_ipv4 *acc_mask,
1494 bool range_accepted,
1495 struct rte_flow_error *error);
1496 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1497 uint64_t item_flags,
1499 uint16_t ether_type,
1500 const struct rte_flow_item_ipv6 *acc_mask,
1501 struct rte_flow_error *error);
1502 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1503 const struct rte_flow_item *item,
1504 uint64_t item_flags,
1505 uint64_t prev_layer,
1506 struct rte_flow_error *error);
1507 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1508 uint64_t item_flags,
1509 uint8_t target_protocol,
1510 const struct rte_flow_item_tcp *flow_mask,
1511 struct rte_flow_error *error);
1512 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1513 uint64_t item_flags,
1514 uint8_t target_protocol,
1515 struct rte_flow_error *error);
1516 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1517 uint64_t item_flags,
1518 struct rte_eth_dev *dev,
1519 struct rte_flow_error *error);
1520 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1521 uint64_t item_flags,
1522 struct rte_flow_error *error);
1523 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1524 uint64_t item_flags,
1525 struct rte_eth_dev *dev,
1526 struct rte_flow_error *error);
1527 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1528 uint64_t item_flags,
1529 uint8_t target_protocol,
1530 struct rte_flow_error *error);
1531 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1532 uint64_t item_flags,
1533 uint8_t target_protocol,
1534 struct rte_flow_error *error);
1535 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1536 uint64_t item_flags,
1537 uint8_t target_protocol,
1538 struct rte_flow_error *error);
1539 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1540 uint64_t item_flags,
1541 struct rte_eth_dev *dev,
1542 struct rte_flow_error *error);
1543 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1545 const struct rte_flow_item *geneve_item,
1546 struct rte_eth_dev *dev,
1547 struct rte_flow_error *error);
1548 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1549 uint64_t item_flags,
1551 uint16_t ether_type,
1552 const struct rte_flow_item_ecpri *acc_mask,
1553 struct rte_flow_error *error);
1554 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1555 struct mlx5_flow_meter_info *fm,
1557 uint8_t domain_bitmap);
1558 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1559 struct mlx5_flow_meter_info *fm);
1560 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1561 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1562 (struct rte_eth_dev *dev,
1563 struct mlx5_flow_meter_policy *mtr_policy,
1564 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1565 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1566 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1567 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1568 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1570 /* Hash list callbacks for flow tables: */
1571 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1572 uint64_t key, void *entry_ctx);
1573 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1574 struct mlx5_hlist_entry *entry, uint64_t key,
1576 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1577 struct mlx5_hlist_entry *entry);
1578 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1579 uint32_t table_level, uint8_t egress, uint8_t transfer,
1580 bool external, const struct mlx5_flow_tunnel *tunnel,
1581 uint32_t group_id, uint8_t dummy,
1582 uint32_t table_id, struct rte_flow_error *error);
1584 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1585 uint64_t key, void *cb_ctx);
1586 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1587 struct mlx5_hlist_entry *entry, uint64_t key,
1589 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1590 struct mlx5_hlist_entry *entry);
1592 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1593 struct mlx5_hlist_entry *entry,
1594 uint64_t key, void *cb_ctx);
1595 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1596 uint64_t key, void *ctx);
1597 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1598 struct mlx5_hlist_entry *entry);
1600 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1601 uint64_t key, void *ctx);
1602 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1603 struct mlx5_hlist_entry *entry, uint64_t key,
1605 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1606 struct mlx5_hlist_entry *entry);
1608 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1609 struct mlx5_hlist_entry *entry,
1610 uint64_t key, void *cb_ctx);
1611 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1612 uint64_t key, void *cb_ctx);
1613 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1614 struct mlx5_hlist_entry *entry);
1616 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1617 struct mlx5_cache_entry *entry, void *ctx);
1618 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1619 struct mlx5_cache_entry *entry, void *ctx);
1620 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1621 struct mlx5_cache_entry *entry);
1623 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1624 struct mlx5_cache_entry *entry, void *cb_ctx);
1625 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1626 struct mlx5_cache_entry *entry, void *cb_ctx);
1627 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1628 struct mlx5_cache_entry *entry);
1630 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1631 struct mlx5_cache_entry *entry, void *cb_ctx);
1632 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1633 (struct mlx5_cache_list *list,
1634 struct mlx5_cache_entry *entry, void *cb_ctx);
1635 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1636 struct mlx5_cache_entry *entry);
1638 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1639 struct mlx5_cache_entry *entry, void *cb_ctx);
1640 struct mlx5_cache_entry *flow_dv_sample_create_cb
1641 (struct mlx5_cache_list *list,
1642 struct mlx5_cache_entry *entry, void *cb_ctx);
1643 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1644 struct mlx5_cache_entry *entry);
1646 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1647 struct mlx5_cache_entry *entry, void *cb_ctx);
1648 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1649 (struct mlx5_cache_list *list,
1650 struct mlx5_cache_entry *entry, void *cb_ctx);
1651 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1652 struct mlx5_cache_entry *entry);
1653 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1655 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1656 const struct rte_flow_item *item,
1657 struct rte_flow_error *error);
1658 void flow_release_workspace(void *data);
1659 int mlx5_flow_os_init_workspace_once(void);
1660 void *mlx5_flow_os_get_specific_workspace(void);
1661 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1662 void mlx5_flow_os_release_workspace(void);
1663 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1664 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1665 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1666 const struct rte_flow_action *actions[RTE_COLORS],
1667 struct rte_flow_attr *attr,
1669 uint8_t *domain_bitmap,
1670 bool *is_def_policy,
1671 struct rte_mtr_error *error);
1672 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1673 struct mlx5_flow_meter_policy *mtr_policy);
1674 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1675 struct mlx5_flow_meter_policy *mtr_policy,
1676 const struct rte_flow_action *actions[RTE_COLORS],
1677 struct rte_mtr_error *error);
1678 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1679 struct mlx5_flow_meter_policy *mtr_policy);
1680 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1681 struct mlx5_flow_meter_policy *mtr_policy);
1682 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1683 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1684 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1685 struct mlx5_flow_handle *dev_handle);
1686 const struct mlx5_flow_tunnel *
1687 mlx5_get_tof(const struct rte_flow_item *items,
1688 const struct rte_flow_action *actions,
1689 enum mlx5_tof_rule_type *rule_type);
1692 #endif /* RTE_PMD_MLX5_FLOW_H_ */