1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Pattern outer Layer bits. */
31 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
32 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
33 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
34 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
35 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
36 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
38 /* Pattern inner Layer bits. */
39 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
40 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
41 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
42 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
43 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
44 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
46 /* Pattern tunnel Layer bits. */
47 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
48 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
49 #define MLX5_FLOW_LAYER_GRE (1u << 14)
50 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
51 /* List of tunnel Layer bits continued below. */
53 /* General pattern items bits. */
54 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
55 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
57 /* Pattern MISC bits. */
58 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
59 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
60 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)
62 /* Pattern tunnel Layer bits (continued). */
63 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
64 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
65 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
68 #define MLX5_FLOW_LAYER_OUTER_L3 \
69 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
70 #define MLX5_FLOW_LAYER_OUTER_L4 \
71 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
72 #define MLX5_FLOW_LAYER_OUTER \
73 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
74 MLX5_FLOW_LAYER_OUTER_L4)
76 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
77 #define MLX5_FLOW_LAYER_IPV4_LRO \
78 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
79 #define MLX5_FLOW_LAYER_IPV6_LRO \
80 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
83 #define MLX5_FLOW_LAYER_TUNNEL \
84 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
85 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
86 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP)
89 #define MLX5_FLOW_LAYER_INNER_L3 \
90 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
91 #define MLX5_FLOW_LAYER_INNER_L4 \
92 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
93 #define MLX5_FLOW_LAYER_INNER \
94 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
95 MLX5_FLOW_LAYER_INNER_L4)
98 #define MLX5_FLOW_LAYER_L2 \
99 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
100 #define MLX5_FLOW_LAYER_L3_IPV4 \
101 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
102 #define MLX5_FLOW_LAYER_L3_IPV6 \
103 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
104 #define MLX5_FLOW_LAYER_L3 \
105 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
106 #define MLX5_FLOW_LAYER_L4 \
107 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
110 #define MLX5_FLOW_ACTION_DROP (1u << 0)
111 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
112 #define MLX5_FLOW_ACTION_RSS (1u << 2)
113 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
114 #define MLX5_FLOW_ACTION_MARK (1u << 4)
115 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
116 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
117 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
118 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
119 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
120 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
121 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
122 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
123 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
124 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
125 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
126 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
127 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
128 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
129 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
130 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
131 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
132 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
133 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
134 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
135 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
136 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
137 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
138 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
139 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
140 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
141 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
143 #define MLX5_FLOW_FATE_ACTIONS \
144 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
145 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
147 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
148 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
149 MLX5_FLOW_ACTION_JUMP)
151 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
152 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
153 MLX5_FLOW_ACTION_RAW_ENCAP)
155 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
156 MLX5_FLOW_ACTION_NVGRE_DECAP | \
157 MLX5_FLOW_ACTION_RAW_DECAP | \
158 MLX5_FLOW_ACTION_OF_POP_VLAN)
160 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
161 MLX5_FLOW_ACTION_SET_IPV4_DST | \
162 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
163 MLX5_FLOW_ACTION_SET_IPV6_DST | \
164 MLX5_FLOW_ACTION_SET_TP_SRC | \
165 MLX5_FLOW_ACTION_SET_TP_DST | \
166 MLX5_FLOW_ACTION_SET_TTL | \
167 MLX5_FLOW_ACTION_DEC_TTL | \
168 MLX5_FLOW_ACTION_SET_MAC_SRC | \
169 MLX5_FLOW_ACTION_SET_MAC_DST | \
170 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
171 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
172 MLX5_FLOW_ACTION_INC_TCP_ACK | \
173 MLX5_FLOW_ACTION_DEC_TCP_ACK)
175 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN)
178 #define IPPROTO_MPLS 137
181 /* UDP port number for MPLS */
182 #define MLX5_UDP_PORT_MPLS 6635
184 /* UDP port numbers for VxLAN. */
185 #define MLX5_UDP_PORT_VXLAN 4789
186 #define MLX5_UDP_PORT_VXLAN_GPE 4790
188 /* Priority reserved for default flows. */
189 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
192 * Number of sub priorities.
193 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
194 * matching on the NIC (firmware dependent) L4 most have the higher priority
195 * followed by L3 and ending with L2.
197 #define MLX5_PRIORITY_MAP_L2 2
198 #define MLX5_PRIORITY_MAP_L3 1
199 #define MLX5_PRIORITY_MAP_L4 0
200 #define MLX5_PRIORITY_MAP_MAX 3
202 /* Valid layer type for IPV4 RSS. */
203 #define MLX5_IPV4_LAYER_TYPES \
204 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
205 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
206 ETH_RSS_NONFRAG_IPV4_OTHER)
208 /* IBV hash source bits for IPV4. */
209 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
211 /* Valid layer type for IPV6 RSS. */
212 #define MLX5_IPV6_LAYER_TYPES \
213 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
214 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
215 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
217 /* IBV hash source bits for IPV6. */
218 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
220 enum mlx5_flow_drv_type {
223 MLX5_FLOW_TYPE_VERBS,
227 /* Matcher PRM representation */
228 struct mlx5_flow_dv_match_params {
230 /**< Size of match value. Do NOT split size and key! */
231 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
232 /**< Matcher value. This value is used as the mask or as a key. */
235 /* Matcher structure. */
236 struct mlx5_flow_dv_matcher {
237 LIST_ENTRY(mlx5_flow_dv_matcher) next;
238 /* Pointer to the next element. */
239 rte_atomic32_t refcnt; /**< Reference counter. */
240 void *matcher_object; /**< Pointer to DV matcher */
241 uint16_t crc; /**< CRC of key. */
242 uint16_t priority; /**< Priority of matcher. */
243 uint8_t egress; /**< Egress matcher. */
244 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
245 uint32_t group; /**< The matcher group. */
246 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
249 #define MLX5_ENCAP_MAX_LEN 132
251 /* Encap/decap resource structure. */
252 struct mlx5_flow_dv_encap_decap_resource {
253 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
254 /* Pointer to next element. */
255 rte_atomic32_t refcnt; /**< Reference counter. */
257 /**< Verbs encap/decap action object. */
258 uint8_t buf[MLX5_ENCAP_MAX_LEN];
260 uint8_t reformat_type;
262 uint64_t flags; /**< Flags for RDMA API. */
265 /* Tag resource structure. */
266 struct mlx5_flow_dv_tag_resource {
267 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
268 /* Pointer to next element. */
269 rte_atomic32_t refcnt; /**< Reference counter. */
271 /**< Verbs tag action object. */
272 uint32_t tag; /**< the tag value. */
275 /* Number of modification commands. */
276 #define MLX5_MODIFY_NUM 8
278 /* Modify resource structure */
279 struct mlx5_flow_dv_modify_hdr_resource {
280 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
281 /* Pointer to next element. */
282 rte_atomic32_t refcnt; /**< Reference counter. */
283 struct ibv_flow_action *verbs_action;
284 /**< Verbs modify header action object. */
285 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
286 uint32_t actions_num; /**< Number of modification actions. */
287 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
288 /**< Modification actions. */
289 uint64_t flags; /**< Flags for RDMA API. */
292 /* Jump action resource structure. */
293 struct mlx5_flow_dv_jump_tbl_resource {
294 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
295 /* Pointer to next element. */
296 rte_atomic32_t refcnt; /**< Reference counter. */
297 void *action; /**< Pointer to the rdma core action. */
298 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
299 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
302 /* Port ID resource structure. */
303 struct mlx5_flow_dv_port_id_action_resource {
304 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
305 /* Pointer to next element. */
306 rte_atomic32_t refcnt; /**< Reference counter. */
308 /**< Verbs tag action object. */
309 uint32_t port_id; /**< Port ID value. */
313 * Max number of actions per DV flow.
314 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
315 * In rdma-core file providers/mlx5/verbs.c
317 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
319 /* DV flows structure. */
320 struct mlx5_flow_dv {
321 uint64_t hash_fields; /**< Fields that participate in the hash. */
322 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
324 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
325 struct mlx5_flow_dv_match_params value;
326 /**< Holds the value that the packet is compared to. */
327 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
328 /**< Pointer to encap/decap resource in cache. */
329 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
330 /**< Pointer to modify header resource in cache. */
331 struct ibv_flow *flow; /**< Installed flow. */
332 struct mlx5_flow_dv_jump_tbl_resource *jump;
333 /**< Pointer to the jump action resource. */
334 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
335 /**< Pointer to port ID action resource. */
336 struct mlx5_vf_vlan vf_vlan;
337 /**< Structure for VF VLAN workaround. */
338 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
339 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
342 int actions_n; /**< number of actions. */
345 /* Verbs specification header. */
346 struct ibv_spec_header {
347 enum ibv_flow_spec_type type;
351 /** Handles information leading to a drop fate. */
352 struct mlx5_flow_verbs {
353 LIST_ENTRY(mlx5_flow_verbs) next;
354 unsigned int size; /**< Size of the attribute. */
356 struct ibv_flow_attr *attr;
357 /**< Pointer to the Specification buffer. */
358 uint8_t *specs; /**< Pointer to the specifications. */
360 struct ibv_flow *flow; /**< Verbs flow pointer. */
361 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
362 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
363 struct mlx5_vf_vlan vf_vlan;
364 /**< Structure for VF VLAN workaround. */
367 /** Device flow structure. */
369 LIST_ENTRY(mlx5_flow) next;
370 struct rte_flow *flow; /**< Pointer to the main flow. */
372 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
374 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
375 struct mlx5_flow_dv dv;
377 struct mlx5_flow_verbs verbs;
381 /* Flow structure. */
383 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
384 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
385 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
386 struct mlx5_flow_dv_tag_resource *tag_resource;
387 /**< pointer to the tag action. */
388 struct rte_flow_action_rss rss;/**< RSS context. */
389 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
390 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
391 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
392 /**< Device flows that are part of the flow. */
394 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
395 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
396 uint8_t ingress; /**< 1 if the flow is ingress. */
397 uint32_t group; /**< The group index. */
398 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
401 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
402 const struct rte_flow_attr *attr,
403 const struct rte_flow_item items[],
404 const struct rte_flow_action actions[],
405 struct rte_flow_error *error);
406 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
407 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
408 const struct rte_flow_action actions[], struct rte_flow_error *error);
409 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
410 struct mlx5_flow *dev_flow,
411 const struct rte_flow_attr *attr,
412 const struct rte_flow_item items[],
413 const struct rte_flow_action actions[],
414 struct rte_flow_error *error);
415 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
416 struct rte_flow_error *error);
417 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
418 struct rte_flow *flow);
419 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
420 struct rte_flow *flow);
421 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
422 struct rte_flow *flow,
423 const struct rte_flow_action *actions,
425 struct rte_flow_error *error);
426 struct mlx5_flow_driver_ops {
427 mlx5_flow_validate_t validate;
428 mlx5_flow_prepare_t prepare;
429 mlx5_flow_translate_t translate;
430 mlx5_flow_apply_t apply;
431 mlx5_flow_remove_t remove;
432 mlx5_flow_destroy_t destroy;
433 mlx5_flow_query_t query;
436 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
437 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
438 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
439 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
443 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
444 uint64_t layer_types,
445 uint64_t hash_fields);
446 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
447 uint32_t subpriority);
448 const struct rte_flow_action *mlx5_flow_find_action
449 (const struct rte_flow_action *actions,
450 enum rte_flow_action_type action);
451 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
452 const struct rte_flow_attr *attr,
453 struct rte_flow_error *error);
454 int mlx5_flow_validate_action_drop(uint64_t action_flags,
455 const struct rte_flow_attr *attr,
456 struct rte_flow_error *error);
457 int mlx5_flow_validate_action_flag(uint64_t action_flags,
458 const struct rte_flow_attr *attr,
459 struct rte_flow_error *error);
460 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
461 uint64_t action_flags,
462 const struct rte_flow_attr *attr,
463 struct rte_flow_error *error);
464 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
465 uint64_t action_flags,
466 struct rte_eth_dev *dev,
467 const struct rte_flow_attr *attr,
468 struct rte_flow_error *error);
469 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
470 uint64_t action_flags,
471 struct rte_eth_dev *dev,
472 const struct rte_flow_attr *attr,
474 struct rte_flow_error *error);
475 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
476 const struct rte_flow_attr *attributes,
477 struct rte_flow_error *error);
478 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
480 const uint8_t *nic_mask,
482 struct rte_flow_error *error);
483 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
485 struct rte_flow_error *error);
486 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
488 uint8_t target_protocol,
489 struct rte_flow_error *error);
490 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
492 const struct rte_flow_item *gre_item,
493 struct rte_flow_error *error);
494 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
496 const struct rte_flow_item_ipv4 *acc_mask,
497 struct rte_flow_error *error);
498 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
500 const struct rte_flow_item_ipv6 *acc_mask,
501 struct rte_flow_error *error);
502 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
503 const struct rte_flow_item *item,
506 struct rte_flow_error *error);
507 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
509 uint8_t target_protocol,
510 const struct rte_flow_item_tcp *flow_mask,
511 struct rte_flow_error *error);
512 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
514 uint8_t target_protocol,
515 struct rte_flow_error *error);
516 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
518 struct rte_eth_dev *dev,
519 struct rte_flow_error *error);
520 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
522 struct rte_flow_error *error);
523 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
525 struct rte_eth_dev *dev,
526 struct rte_flow_error *error);
527 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
529 uint8_t target_protocol,
530 struct rte_flow_error *error);
531 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
533 uint8_t target_protocol,
534 struct rte_flow_error *error);
535 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
537 uint8_t target_protocol,
538 struct rte_flow_error *error);
539 #endif /* RTE_PMD_MLX5_FLOW_H_ */