1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
31 /* Private rte flow items. */
32 enum mlx5_rte_flow_item_type {
33 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
35 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
38 /* Private (internal) rte flow actions. */
39 enum mlx5_rte_flow_action_type {
40 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
41 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
42 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
43 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
46 /* Matches on selected register. */
47 struct mlx5_rte_flow_item_tag {
52 /* Modify selected register. */
53 struct mlx5_rte_flow_action_set_tag {
58 struct mlx5_flow_action_copy_mreg {
63 /* Matches on source queue. */
64 struct mlx5_rte_flow_item_tx_queue {
68 /* Feature name to allocate metadata register. */
69 enum mlx5_feature_name {
82 /* Pattern outer Layer bits. */
83 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
84 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
85 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
86 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
87 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
88 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
90 /* Pattern inner Layer bits. */
91 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
92 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
93 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
94 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
95 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
96 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
98 /* Pattern tunnel Layer bits. */
99 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
100 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
101 #define MLX5_FLOW_LAYER_GRE (1u << 14)
102 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
103 /* List of tunnel Layer bits continued below. */
105 /* General pattern items bits. */
106 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
107 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
108 #define MLX5_FLOW_ITEM_TAG (1u << 18)
109 #define MLX5_FLOW_ITEM_MARK (1u << 19)
111 /* Pattern MISC bits. */
112 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
113 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
114 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
116 /* Pattern tunnel Layer bits (continued). */
117 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
118 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
119 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
120 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
123 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
126 #define MLX5_FLOW_LAYER_OUTER_L3 \
127 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
128 #define MLX5_FLOW_LAYER_OUTER_L4 \
129 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
130 #define MLX5_FLOW_LAYER_OUTER \
131 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
132 MLX5_FLOW_LAYER_OUTER_L4)
135 #define MLX5_FLOW_LAYER_TUNNEL \
136 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
137 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
138 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
139 MLX5_FLOW_LAYER_GENEVE)
142 #define MLX5_FLOW_LAYER_INNER_L3 \
143 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
144 #define MLX5_FLOW_LAYER_INNER_L4 \
145 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
146 #define MLX5_FLOW_LAYER_INNER \
147 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
148 MLX5_FLOW_LAYER_INNER_L4)
151 #define MLX5_FLOW_LAYER_L2 \
152 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
153 #define MLX5_FLOW_LAYER_L3_IPV4 \
154 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
155 #define MLX5_FLOW_LAYER_L3_IPV6 \
156 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
157 #define MLX5_FLOW_LAYER_L3 \
158 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
159 #define MLX5_FLOW_LAYER_L4 \
160 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
163 #define MLX5_FLOW_ACTION_DROP (1u << 0)
164 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
165 #define MLX5_FLOW_ACTION_RSS (1u << 2)
166 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
167 #define MLX5_FLOW_ACTION_MARK (1u << 4)
168 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
169 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
170 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
171 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
172 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
173 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
174 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
175 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
176 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
177 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
178 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
179 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
180 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
181 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
182 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
183 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
184 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
185 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
186 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
187 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
188 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
189 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
190 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
191 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
192 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
193 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
194 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
195 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
196 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33)
197 #define MLX5_FLOW_ACTION_SET_META (1ull << 34)
198 #define MLX5_FLOW_ACTION_METER (1ull << 35)
200 #define MLX5_FLOW_FATE_ACTIONS \
201 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
202 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
204 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
205 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
206 MLX5_FLOW_ACTION_JUMP)
208 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
209 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
210 MLX5_FLOW_ACTION_RAW_ENCAP | \
211 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
213 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
214 MLX5_FLOW_ACTION_NVGRE_DECAP | \
215 MLX5_FLOW_ACTION_RAW_DECAP | \
216 MLX5_FLOW_ACTION_OF_POP_VLAN)
218 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
219 MLX5_FLOW_ACTION_SET_IPV4_DST | \
220 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
221 MLX5_FLOW_ACTION_SET_IPV6_DST | \
222 MLX5_FLOW_ACTION_SET_TP_SRC | \
223 MLX5_FLOW_ACTION_SET_TP_DST | \
224 MLX5_FLOW_ACTION_SET_TTL | \
225 MLX5_FLOW_ACTION_DEC_TTL | \
226 MLX5_FLOW_ACTION_SET_MAC_SRC | \
227 MLX5_FLOW_ACTION_SET_MAC_DST | \
228 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
229 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
230 MLX5_FLOW_ACTION_INC_TCP_ACK | \
231 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
232 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
233 MLX5_FLOW_ACTION_SET_TAG | \
234 MLX5_FLOW_ACTION_MARK_EXT | \
235 MLX5_FLOW_ACTION_SET_META)
237 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
238 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
240 #define IPPROTO_MPLS 137
243 /* UDP port number for MPLS */
244 #define MLX5_UDP_PORT_MPLS 6635
246 /* UDP port numbers for VxLAN. */
247 #define MLX5_UDP_PORT_VXLAN 4789
248 #define MLX5_UDP_PORT_VXLAN_GPE 4790
250 /* UDP port numbers for GENEVE. */
251 #define MLX5_UDP_PORT_GENEVE 6081
253 /* Priority reserved for default flows. */
254 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
257 * Number of sub priorities.
258 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
259 * matching on the NIC (firmware dependent) L4 most have the higher priority
260 * followed by L3 and ending with L2.
262 #define MLX5_PRIORITY_MAP_L2 2
263 #define MLX5_PRIORITY_MAP_L3 1
264 #define MLX5_PRIORITY_MAP_L4 0
265 #define MLX5_PRIORITY_MAP_MAX 3
267 /* Valid layer type for IPV4 RSS. */
268 #define MLX5_IPV4_LAYER_TYPES \
269 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
270 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
271 ETH_RSS_NONFRAG_IPV4_OTHER)
273 /* IBV hash source bits for IPV4. */
274 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
276 /* Valid layer type for IPV6 RSS. */
277 #define MLX5_IPV6_LAYER_TYPES \
278 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
279 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
280 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
282 /* IBV hash source bits for IPV6. */
283 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
286 /* Geneve header first 16Bit */
287 #define MLX5_GENEVE_VER_MASK 0x3
288 #define MLX5_GENEVE_VER_SHIFT 14
289 #define MLX5_GENEVE_VER_VAL(a) \
290 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
291 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
292 #define MLX5_GENEVE_OPTLEN_SHIFT 7
293 #define MLX5_GENEVE_OPTLEN_VAL(a) \
294 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
295 #define MLX5_GENEVE_OAMF_MASK 0x1
296 #define MLX5_GENEVE_OAMF_SHIFT 7
297 #define MLX5_GENEVE_OAMF_VAL(a) \
298 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
299 #define MLX5_GENEVE_CRITO_MASK 0x1
300 #define MLX5_GENEVE_CRITO_SHIFT 6
301 #define MLX5_GENEVE_CRITO_VAL(a) \
302 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
303 #define MLX5_GENEVE_RSVD_MASK 0x3F
304 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
306 * The length of the Geneve options fields, expressed in four byte multiples,
307 * not including the eight byte fixed tunnel.
309 #define MLX5_GENEVE_OPT_LEN_0 14
310 #define MLX5_GENEVE_OPT_LEN_1 63
312 enum mlx5_flow_drv_type {
315 MLX5_FLOW_TYPE_VERBS,
319 /* Matcher PRM representation */
320 struct mlx5_flow_dv_match_params {
322 /**< Size of match value. Do NOT split size and key! */
323 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
324 /**< Matcher value. This value is used as the mask or as a key. */
327 /* Matcher structure. */
328 struct mlx5_flow_dv_matcher {
329 LIST_ENTRY(mlx5_flow_dv_matcher) next;
330 /**< Pointer to the next element. */
331 struct mlx5_flow_tbl_resource *tbl;
332 /**< Pointer to the table(group) the matcher associated with. */
333 rte_atomic32_t refcnt; /**< Reference counter. */
334 void *matcher_object; /**< Pointer to DV matcher */
335 uint16_t crc; /**< CRC of key. */
336 uint16_t priority; /**< Priority of matcher. */
337 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
340 #define MLX5_ENCAP_MAX_LEN 132
342 /* Encap/decap resource structure. */
343 struct mlx5_flow_dv_encap_decap_resource {
344 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
345 /* Pointer to next element. */
346 rte_atomic32_t refcnt; /**< Reference counter. */
348 /**< Verbs encap/decap action object. */
349 uint8_t buf[MLX5_ENCAP_MAX_LEN];
351 uint8_t reformat_type;
353 uint64_t flags; /**< Flags for RDMA API. */
356 /* Tag resource structure. */
357 struct mlx5_flow_dv_tag_resource {
358 struct mlx5_hlist_entry entry;
359 /**< hash list entry for tag resource, tag value as the key. */
361 /**< Verbs tag action object. */
362 rte_atomic32_t refcnt; /**< Reference counter. */
366 * Number of modification commands.
367 * If extensive metadata registers are supported
368 * the maximal actions amount is 16 and 8 otherwise.
370 #define MLX5_MODIFY_NUM 16
371 #define MLX5_MODIFY_NUM_NO_MREG 8
373 /* Modify resource structure */
374 struct mlx5_flow_dv_modify_hdr_resource {
375 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
376 /* Pointer to next element. */
377 rte_atomic32_t refcnt; /**< Reference counter. */
378 struct ibv_flow_action *verbs_action;
379 /**< Verbs modify header action object. */
380 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
381 uint32_t actions_num; /**< Number of modification actions. */
382 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
383 /**< Modification actions. */
384 uint64_t flags; /**< Flags for RDMA API. */
387 /* Jump action resource structure. */
388 struct mlx5_flow_dv_jump_tbl_resource {
389 rte_atomic32_t refcnt; /**< Reference counter. */
390 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
391 void *action; /**< Pointer to the rdma core action. */
394 /* Port ID resource structure. */
395 struct mlx5_flow_dv_port_id_action_resource {
396 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
397 /* Pointer to next element. */
398 rte_atomic32_t refcnt; /**< Reference counter. */
400 /**< Verbs tag action object. */
401 uint32_t port_id; /**< Port ID value. */
404 /* Push VLAN action resource structure */
405 struct mlx5_flow_dv_push_vlan_action_resource {
406 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
407 /* Pointer to next element. */
408 rte_atomic32_t refcnt; /**< Reference counter. */
409 void *action; /**< Direct verbs action object. */
410 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
411 rte_be32_t vlan_tag; /**< VLAN tag value. */
414 /* Metadata register copy table entry. */
415 struct mlx5_flow_mreg_copy_resource {
417 * Hash list entry for copy table.
418 * - Key is 32/64-bit MARK action ID.
419 * - MUST be the first entry.
421 struct mlx5_hlist_entry hlist_ent;
422 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
423 /* List entry for device flows. */
424 uint32_t refcnt; /* Reference counter. */
425 uint32_t appcnt; /* Apply/Remove counter. */
426 struct rte_flow *flow; /* Built flow for copy. */
429 /* Table data structure of the hash organization. */
430 struct mlx5_flow_tbl_data_entry {
431 struct mlx5_hlist_entry entry;
432 /**< hash list entry, 64-bits key inside. */
433 struct mlx5_flow_tbl_resource tbl;
434 /**< flow table resource. */
435 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
436 /**< matchers' header associated with the flow table. */
437 struct mlx5_flow_dv_jump_tbl_resource jump;
438 /**< jump resource, at most one for each table created. */
442 * Max number of actions per DV flow.
443 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
444 * In rdma-core file providers/mlx5/verbs.c
446 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
448 /* DV flows structure. */
449 struct mlx5_flow_dv {
450 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
452 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
453 struct mlx5_flow_dv_match_params value;
454 /**< Holds the value that the packet is compared to. */
455 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
456 /**< Pointer to encap/decap resource in cache. */
457 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
458 /**< Pointer to modify header resource in cache. */
459 struct ibv_flow *flow; /**< Installed flow. */
460 struct mlx5_flow_dv_jump_tbl_resource *jump;
461 /**< Pointer to the jump action resource. */
462 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
463 /**< Pointer to port ID action resource. */
464 struct mlx5_vf_vlan vf_vlan;
465 /**< Structure for VF VLAN workaround. */
466 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
467 /**< Pointer to push VLAN action resource in cache. */
468 struct mlx5_flow_dv_tag_resource *tag_resource;
469 /**< pointer to the tag action. */
470 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
471 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
474 int actions_n; /**< number of actions. */
477 /* Verbs specification header. */
478 struct ibv_spec_header {
479 enum ibv_flow_spec_type type;
483 /** Handles information leading to a drop fate. */
484 struct mlx5_flow_verbs {
485 LIST_ENTRY(mlx5_flow_verbs) next;
486 unsigned int size; /**< Size of the attribute. */
488 struct ibv_flow_attr *attr;
489 /**< Pointer to the Specification buffer. */
490 uint8_t *specs; /**< Pointer to the specifications. */
492 struct ibv_flow *flow; /**< Verbs flow pointer. */
493 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
494 struct mlx5_vf_vlan vf_vlan;
495 /**< Structure for VF VLAN workaround. */
498 struct mlx5_flow_rss {
500 uint32_t queue_num; /**< Number of entries in @p queue. */
501 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
502 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
503 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
506 /** Device flow structure. */
508 LIST_ENTRY(mlx5_flow) next;
509 struct rte_flow *flow; /**< Pointer to the main flow. */
511 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
513 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
514 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
515 uint8_t ingress; /**< 1 if the flow is ingress. */
516 uint32_t group; /**< The group index. */
517 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
519 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
520 struct mlx5_flow_dv dv;
522 struct mlx5_flow_verbs verbs;
525 uint32_t qrss_id; /**< Uniqie Q/RSS suffix subflow tag. */
526 uint32_t mtr_flow_id; /**< Unique meter match flow id. */
528 bool external; /**< true if the flow is created external to PMD. */
531 /* Flow meter state. */
532 #define MLX5_FLOW_METER_DISABLE 0
533 #define MLX5_FLOW_METER_ENABLE 1
535 #define MLX5_MAN_WIDTH 8
536 /* Modify this value if enum rte_mtr_color changes. */
537 #define RTE_MTR_DROPPED RTE_COLORS
539 /* Meter policer statistics */
540 struct mlx5_flow_policer_stats {
541 struct mlx5_flow_counter *cnt[RTE_COLORS + 1];
542 /**< Color counter, extra for drop. */
544 /**< Statistics mask for the colors. */
547 /* Meter table structure. */
548 struct mlx5_meter_domain_info {
549 struct mlx5_flow_tbl_resource *tbl;
552 /**< Meter color not match default criteria. */
554 /**< Meter color match criteria. */
556 /**< Meter match action. */
557 void *policer_rules[RTE_MTR_DROPPED + 1];
558 /**< Meter policer for the match. */
561 /* Meter table set for TX RX FDB. */
562 struct mlx5_meter_domains_infos {
564 /**< Table user count. */
565 struct mlx5_meter_domain_info egress;
566 /**< TX meter table. */
567 struct mlx5_meter_domain_info ingress;
568 /**< RX meter table. */
569 struct mlx5_meter_domain_info transfer;
570 /**< FDB meter table. */
572 /**< Drop action as not matched. */
573 void *count_actns[RTE_MTR_DROPPED + 1];
574 /**< Counters for match and unmatched statistics. */
575 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
576 /**< Flow meter parameter. */
578 /**< Flow meter parameter size. */
580 /**< Flow meter action. */
583 /* Meter parameter structure. */
584 struct mlx5_flow_meter {
585 TAILQ_ENTRY(mlx5_flow_meter) next;
586 /**< Pointer to the next flow meter structure. */
589 struct rte_mtr_params params;
590 /**< Meter rule parameters. */
591 struct mlx5_flow_meter_profile *profile;
592 /**< Meter profile parameters. */
593 struct rte_flow_attr attr;
594 /**< Flow attributes. */
595 struct mlx5_meter_domains_infos *mfts;
596 /**< Flow table created for this meter. */
597 struct mlx5_flow_policer_stats policer_stats;
598 /**< Meter policer statistics. */
601 uint32_t active_state:1;
604 /**< Meter shared or not. */
607 /* RFC2697 parameter structure. */
608 struct mlx5_flow_meter_srtcm_rfc2697_prm {
609 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
610 uint32_t cbs_exponent:5;
611 uint32_t cbs_mantissa:8;
612 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
613 uint32_t cir_exponent:5;
614 uint32_t cir_mantissa:8;
615 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
616 uint32_t ebs_exponent:5;
617 uint32_t ebs_mantissa:8;
620 /* Flow meter profile structure. */
621 struct mlx5_flow_meter_profile {
622 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
623 /**< Pointer to the next flow meter structure. */
624 uint32_t meter_profile_id; /**< Profile id. */
625 struct rte_mtr_meter_profile profile; /**< Profile detail. */
627 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
628 /**< srtcm_rfc2697 struct. */
630 uint32_t ref_cnt; /**< Use count. */
633 /* Flow structure. */
635 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
636 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
637 struct mlx5_flow_rss rss; /**< RSS context. */
638 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
639 struct mlx5_flow_mreg_copy_resource *mreg_copy;
640 /**< pointer to metadata register copy table resource. */
641 struct mlx5_flow_meter *meter; /**< Holds flow meter. */
642 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
643 /**< Device flows that are part of the flow. */
644 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
645 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
646 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
649 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
650 const struct rte_flow_attr *attr,
651 const struct rte_flow_item items[],
652 const struct rte_flow_action actions[],
654 struct rte_flow_error *error);
655 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
656 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
657 const struct rte_flow_action actions[], struct rte_flow_error *error);
658 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
659 struct mlx5_flow *dev_flow,
660 const struct rte_flow_attr *attr,
661 const struct rte_flow_item items[],
662 const struct rte_flow_action actions[],
663 struct rte_flow_error *error);
664 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
665 struct rte_flow_error *error);
666 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
667 struct rte_flow *flow);
668 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
669 struct rte_flow *flow);
670 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
671 struct rte_flow *flow,
672 const struct rte_flow_action *actions,
674 struct rte_flow_error *error);
675 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
676 (struct rte_eth_dev *dev,
677 const struct mlx5_flow_meter *fm);
678 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
679 struct mlx5_meter_domains_infos *tbls);
680 typedef int (*mlx5_flow_create_policer_rules_t)
681 (struct rte_eth_dev *dev,
682 struct mlx5_flow_meter *fm,
683 const struct rte_flow_attr *attr);
684 typedef int (*mlx5_flow_destroy_policer_rules_t)
685 (struct rte_eth_dev *dev,
686 const struct mlx5_flow_meter *fm,
687 const struct rte_flow_attr *attr);
688 typedef struct mlx5_flow_counter * (*mlx5_flow_counter_alloc_t)
689 (struct rte_eth_dev *dev);
690 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
691 struct mlx5_flow_counter *cnt);
692 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
693 struct mlx5_flow_counter *cnt,
694 bool clear, uint64_t *pkts,
696 struct mlx5_flow_driver_ops {
697 mlx5_flow_validate_t validate;
698 mlx5_flow_prepare_t prepare;
699 mlx5_flow_translate_t translate;
700 mlx5_flow_apply_t apply;
701 mlx5_flow_remove_t remove;
702 mlx5_flow_destroy_t destroy;
703 mlx5_flow_query_t query;
704 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
705 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
706 mlx5_flow_create_policer_rules_t create_policer_rules;
707 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
708 mlx5_flow_counter_alloc_t counter_alloc;
709 mlx5_flow_counter_free_t counter_free;
710 mlx5_flow_counter_query_t counter_query;
714 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
715 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
716 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
717 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
721 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
722 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
723 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
724 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
726 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
727 bool external, uint32_t group, uint32_t *table,
728 struct rte_flow_error *error);
729 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
730 uint64_t layer_types,
731 uint64_t hash_fields);
732 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
733 uint32_t subpriority);
734 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
735 enum mlx5_feature_name feature,
737 struct rte_flow_error *error);
738 const struct rte_flow_action *mlx5_flow_find_action
739 (const struct rte_flow_action *actions,
740 enum rte_flow_action_type action);
741 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
742 const struct rte_flow_attr *attr,
743 struct rte_flow_error *error);
744 int mlx5_flow_validate_action_drop(uint64_t action_flags,
745 const struct rte_flow_attr *attr,
746 struct rte_flow_error *error);
747 int mlx5_flow_validate_action_flag(uint64_t action_flags,
748 const struct rte_flow_attr *attr,
749 struct rte_flow_error *error);
750 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
751 uint64_t action_flags,
752 const struct rte_flow_attr *attr,
753 struct rte_flow_error *error);
754 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
755 uint64_t action_flags,
756 struct rte_eth_dev *dev,
757 const struct rte_flow_attr *attr,
758 struct rte_flow_error *error);
759 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
760 uint64_t action_flags,
761 struct rte_eth_dev *dev,
762 const struct rte_flow_attr *attr,
764 struct rte_flow_error *error);
765 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
766 const struct rte_flow_attr *attributes,
767 struct rte_flow_error *error);
768 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
770 const uint8_t *nic_mask,
772 struct rte_flow_error *error);
773 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
775 struct rte_flow_error *error);
776 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
778 uint8_t target_protocol,
779 struct rte_flow_error *error);
780 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
782 const struct rte_flow_item *gre_item,
783 struct rte_flow_error *error);
784 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
788 const struct rte_flow_item_ipv4 *acc_mask,
789 struct rte_flow_error *error);
790 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
794 const struct rte_flow_item_ipv6 *acc_mask,
795 struct rte_flow_error *error);
796 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
797 const struct rte_flow_item *item,
800 struct rte_flow_error *error);
801 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
803 uint8_t target_protocol,
804 const struct rte_flow_item_tcp *flow_mask,
805 struct rte_flow_error *error);
806 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
808 uint8_t target_protocol,
809 struct rte_flow_error *error);
810 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
812 struct rte_eth_dev *dev,
813 struct rte_flow_error *error);
814 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
816 struct rte_flow_error *error);
817 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
819 struct rte_eth_dev *dev,
820 struct rte_flow_error *error);
821 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
823 uint8_t target_protocol,
824 struct rte_flow_error *error);
825 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
827 uint8_t target_protocol,
828 struct rte_flow_error *error);
829 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
831 uint8_t target_protocol,
832 struct rte_flow_error *error);
833 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
835 struct rte_eth_dev *dev,
836 struct rte_flow_error *error);
837 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
838 (struct rte_eth_dev *dev,
839 const struct mlx5_flow_meter *fm);
840 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
841 struct mlx5_meter_domains_infos *tbl);
842 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
843 struct mlx5_flow_meter *fm,
844 const struct rte_flow_attr *attr);
845 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
846 struct mlx5_flow_meter *fm,
847 const struct rte_flow_attr *attr);
848 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
849 struct rte_mtr_error *error);
850 #endif /* RTE_PMD_MLX5_FLOW_H_ */