1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_atomic.h>
15 #include <rte_alarm.h>
18 #include <mlx5_glue.h>
23 /* Private rte flow items. */
24 enum mlx5_rte_flow_item_type {
25 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
26 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
27 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
28 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 /* Matches on selected register. */
41 struct mlx5_rte_flow_item_tag {
46 /* Modify selected register. */
47 struct mlx5_rte_flow_action_set_tag {
52 struct mlx5_flow_action_copy_mreg {
57 /* Matches on source queue. */
58 struct mlx5_rte_flow_item_tx_queue {
62 /* Feature name to allocate metadata register. */
63 enum mlx5_feature_name {
76 /* Pattern outer Layer bits. */
77 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
78 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
79 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
80 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
81 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
82 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
84 /* Pattern inner Layer bits. */
85 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
86 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
87 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
88 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
89 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
90 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
92 /* Pattern tunnel Layer bits. */
93 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
94 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
95 #define MLX5_FLOW_LAYER_GRE (1u << 14)
96 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
97 /* List of tunnel Layer bits continued below. */
99 /* General pattern items bits. */
100 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
101 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
102 #define MLX5_FLOW_ITEM_TAG (1u << 18)
103 #define MLX5_FLOW_ITEM_MARK (1u << 19)
105 /* Pattern MISC bits. */
106 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
107 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
108 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
110 /* Pattern tunnel Layer bits (continued). */
111 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
112 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
113 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
114 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
117 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
119 /* Pattern tunnel Layer bits (continued). */
120 #define MLX5_FLOW_LAYER_GTP (1u << 28)
122 /* Pattern eCPRI Layer bit. */
123 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
126 #define MLX5_FLOW_LAYER_OUTER_L3 \
127 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
128 #define MLX5_FLOW_LAYER_OUTER_L4 \
129 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
130 #define MLX5_FLOW_LAYER_OUTER \
131 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
132 MLX5_FLOW_LAYER_OUTER_L4)
135 #define MLX5_FLOW_LAYER_TUNNEL \
136 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
137 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
138 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
139 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
142 #define MLX5_FLOW_LAYER_INNER_L3 \
143 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
144 #define MLX5_FLOW_LAYER_INNER_L4 \
145 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
146 #define MLX5_FLOW_LAYER_INNER \
147 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
148 MLX5_FLOW_LAYER_INNER_L4)
151 #define MLX5_FLOW_LAYER_L2 \
152 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
153 #define MLX5_FLOW_LAYER_L3_IPV4 \
154 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
155 #define MLX5_FLOW_LAYER_L3_IPV6 \
156 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
157 #define MLX5_FLOW_LAYER_L3 \
158 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
159 #define MLX5_FLOW_LAYER_L4 \
160 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
163 #define MLX5_FLOW_ACTION_DROP (1u << 0)
164 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
165 #define MLX5_FLOW_ACTION_RSS (1u << 2)
166 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
167 #define MLX5_FLOW_ACTION_MARK (1u << 4)
168 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
169 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
170 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
171 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
172 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
173 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
174 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
175 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
176 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
177 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
178 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
179 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
180 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
181 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
182 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
183 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
184 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
185 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
186 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
187 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
188 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
189 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
190 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
191 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
192 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
193 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
194 #define MLX5_FLOW_ACTION_METER (1ull << 31)
195 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
196 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
197 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
198 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
200 #define MLX5_FLOW_FATE_ACTIONS \
201 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
202 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
203 MLX5_FLOW_ACTION_DEFAULT_MISS)
205 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
206 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
207 MLX5_FLOW_ACTION_JUMP)
210 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
211 MLX5_FLOW_ACTION_SET_IPV4_DST | \
212 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
213 MLX5_FLOW_ACTION_SET_IPV6_DST | \
214 MLX5_FLOW_ACTION_SET_TP_SRC | \
215 MLX5_FLOW_ACTION_SET_TP_DST | \
216 MLX5_FLOW_ACTION_SET_TTL | \
217 MLX5_FLOW_ACTION_DEC_TTL | \
218 MLX5_FLOW_ACTION_SET_MAC_SRC | \
219 MLX5_FLOW_ACTION_SET_MAC_DST | \
220 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
221 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
222 MLX5_FLOW_ACTION_INC_TCP_ACK | \
223 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
224 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
225 MLX5_FLOW_ACTION_SET_TAG | \
226 MLX5_FLOW_ACTION_MARK_EXT | \
227 MLX5_FLOW_ACTION_SET_META | \
228 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
229 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
231 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
232 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
234 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
237 #define IPPROTO_MPLS 137
240 /* UDP port number for MPLS */
241 #define MLX5_UDP_PORT_MPLS 6635
243 /* UDP port numbers for VxLAN. */
244 #define MLX5_UDP_PORT_VXLAN 4789
245 #define MLX5_UDP_PORT_VXLAN_GPE 4790
247 /* UDP port numbers for GENEVE. */
248 #define MLX5_UDP_PORT_GENEVE 6081
250 /* Priority reserved for default flows. */
251 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
254 * Number of sub priorities.
255 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
256 * matching on the NIC (firmware dependent) L4 most have the higher priority
257 * followed by L3 and ending with L2.
259 #define MLX5_PRIORITY_MAP_L2 2
260 #define MLX5_PRIORITY_MAP_L3 1
261 #define MLX5_PRIORITY_MAP_L4 0
262 #define MLX5_PRIORITY_MAP_MAX 3
264 /* Valid layer type for IPV4 RSS. */
265 #define MLX5_IPV4_LAYER_TYPES \
266 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
267 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
268 ETH_RSS_NONFRAG_IPV4_OTHER)
270 /* IBV hash source bits for IPV4. */
271 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
273 /* Valid layer type for IPV6 RSS. */
274 #define MLX5_IPV6_LAYER_TYPES \
275 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
276 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
277 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
279 /* IBV hash source bits for IPV6. */
280 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
282 /* IBV hash bits for L3 SRC. */
283 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
285 /* IBV hash bits for L3 DST. */
286 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
288 /* IBV hash bits for TCP. */
289 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
290 IBV_RX_HASH_DST_PORT_TCP)
292 /* IBV hash bits for UDP. */
293 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
294 IBV_RX_HASH_DST_PORT_UDP)
296 /* IBV hash bits for L4 SRC. */
297 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
298 IBV_RX_HASH_SRC_PORT_UDP)
300 /* IBV hash bits for L4 DST. */
301 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
302 IBV_RX_HASH_DST_PORT_UDP)
304 /* Geneve header first 16Bit */
305 #define MLX5_GENEVE_VER_MASK 0x3
306 #define MLX5_GENEVE_VER_SHIFT 14
307 #define MLX5_GENEVE_VER_VAL(a) \
308 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
309 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
310 #define MLX5_GENEVE_OPTLEN_SHIFT 7
311 #define MLX5_GENEVE_OPTLEN_VAL(a) \
312 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
313 #define MLX5_GENEVE_OAMF_MASK 0x1
314 #define MLX5_GENEVE_OAMF_SHIFT 7
315 #define MLX5_GENEVE_OAMF_VAL(a) \
316 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
317 #define MLX5_GENEVE_CRITO_MASK 0x1
318 #define MLX5_GENEVE_CRITO_SHIFT 6
319 #define MLX5_GENEVE_CRITO_VAL(a) \
320 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
321 #define MLX5_GENEVE_RSVD_MASK 0x3F
322 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
324 * The length of the Geneve options fields, expressed in four byte multiples,
325 * not including the eight byte fixed tunnel.
327 #define MLX5_GENEVE_OPT_LEN_0 14
328 #define MLX5_GENEVE_OPT_LEN_1 63
330 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
331 sizeof(struct rte_flow_item_ipv4))
333 /* Software header modify action numbers of a flow. */
334 #define MLX5_ACT_NUM_MDF_IPV4 1
335 #define MLX5_ACT_NUM_MDF_IPV6 4
336 #define MLX5_ACT_NUM_MDF_MAC 2
337 #define MLX5_ACT_NUM_MDF_VID 1
338 #define MLX5_ACT_NUM_MDF_PORT 2
339 #define MLX5_ACT_NUM_MDF_TTL 1
340 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
341 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
342 #define MLX5_ACT_NUM_MDF_TCPACK 1
343 #define MLX5_ACT_NUM_SET_REG 1
344 #define MLX5_ACT_NUM_SET_TAG 1
345 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
346 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
347 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
348 #define MLX5_ACT_NUM_SET_DSCP 1
350 enum mlx5_flow_drv_type {
353 MLX5_FLOW_TYPE_VERBS,
357 /* Fate action type. */
358 enum mlx5_flow_fate_type {
359 MLX5_FLOW_FATE_NONE, /* Egress flow. */
360 MLX5_FLOW_FATE_QUEUE,
362 MLX5_FLOW_FATE_PORT_ID,
364 MLX5_FLOW_FATE_DEFAULT_MISS,
368 /* Matcher PRM representation */
369 struct mlx5_flow_dv_match_params {
371 /**< Size of match value. Do NOT split size and key! */
372 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
373 /**< Matcher value. This value is used as the mask or as a key. */
376 /* Matcher structure. */
377 struct mlx5_flow_dv_matcher {
378 LIST_ENTRY(mlx5_flow_dv_matcher) next;
379 /**< Pointer to the next element. */
380 struct mlx5_flow_tbl_resource *tbl;
381 /**< Pointer to the table(group) the matcher associated with. */
382 rte_atomic32_t refcnt; /**< Reference counter. */
383 void *matcher_object; /**< Pointer to DV matcher */
384 uint16_t crc; /**< CRC of key. */
385 uint16_t priority; /**< Priority of matcher. */
386 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
389 #define MLX5_ENCAP_MAX_LEN 132
391 /* Encap/decap resource key of the hash organization. */
392 union mlx5_flow_encap_decap_key {
394 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
395 uint32_t refmt_type:8; /**< Header reformat type. */
396 uint32_t buf_size:8; /**< Encap buf size. */
397 uint32_t table_level:8; /**< Root table or not. */
398 uint32_t cksum; /**< Encap buf check sum. */
400 uint64_t v64; /**< full 64bits value of key */
403 /* Encap/decap resource structure. */
404 struct mlx5_flow_dv_encap_decap_resource {
405 struct mlx5_hlist_entry entry;
406 /* Pointer to next element. */
407 rte_atomic32_t refcnt; /**< Reference counter. */
409 /**< Encap/decap action object. */
410 uint8_t buf[MLX5_ENCAP_MAX_LEN];
412 uint8_t reformat_type;
414 uint64_t flags; /**< Flags for RDMA API. */
415 uint32_t idx; /**< Index for the index memory pool. */
418 /* Tag resource structure. */
419 struct mlx5_flow_dv_tag_resource {
420 struct mlx5_hlist_entry entry;
421 /**< hash list entry for tag resource, tag value as the key. */
423 /**< Tag action object. */
424 rte_atomic32_t refcnt; /**< Reference counter. */
425 uint32_t idx; /**< Index for the index memory pool. */
429 * Number of modification commands.
430 * The maximal actions amount in FW is some constant, and it is 16 in the
431 * latest releases. In some old releases, it will be limited to 8.
432 * Since there is no interface to query the capacity, the maximal value should
433 * be used to allow PMD to create the flow. The validation will be done in the
434 * lower driver layer or FW. A failure will be returned if exceeds the maximal
435 * supported actions number on the root table.
436 * On non-root tables, there is no limitation, but 32 is enough right now.
438 #define MLX5_MAX_MODIFY_NUM 32
439 #define MLX5_ROOT_TBL_MODIFY_NUM 16
441 /* Modify resource structure */
442 struct mlx5_flow_dv_modify_hdr_resource {
443 struct mlx5_hlist_entry entry;
444 /* Pointer to next element. */
445 rte_atomic32_t refcnt; /**< Reference counter. */
447 /**< Modify header action object. */
448 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
449 uint32_t actions_num; /**< Number of modification actions. */
450 uint64_t flags; /**< Flags for RDMA API. */
451 struct mlx5_modification_cmd actions[];
452 /**< Modification actions. */
455 /* Modify resource key of the hash organization. */
456 union mlx5_flow_modify_hdr_key {
458 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
459 uint32_t actions_num:5; /**< Number of modification actions. */
460 uint32_t group:19; /**< Flow group id. */
461 uint32_t cksum; /**< Actions check sum. */
463 uint64_t v64; /**< full 64bits value of key */
466 /* Jump action resource structure. */
467 struct mlx5_flow_dv_jump_tbl_resource {
468 rte_atomic32_t refcnt; /**< Reference counter. */
469 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
470 void *action; /**< Pointer to the rdma core action. */
473 /* Port ID resource structure. */
474 struct mlx5_flow_dv_port_id_action_resource {
475 ILIST_ENTRY(uint32_t)next;
476 /* Pointer to next element. */
477 rte_atomic32_t refcnt; /**< Reference counter. */
479 /**< Action object. */
480 uint32_t port_id; /**< Port ID value. */
483 /* Push VLAN action resource structure */
484 struct mlx5_flow_dv_push_vlan_action_resource {
485 ILIST_ENTRY(uint32_t)next;
486 /* Pointer to next element. */
487 rte_atomic32_t refcnt; /**< Reference counter. */
488 void *action; /**< Action object. */
489 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
490 rte_be32_t vlan_tag; /**< VLAN tag value. */
493 /* Metadata register copy table entry. */
494 struct mlx5_flow_mreg_copy_resource {
496 * Hash list entry for copy table.
497 * - Key is 32/64-bit MARK action ID.
498 * - MUST be the first entry.
500 struct mlx5_hlist_entry hlist_ent;
501 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
502 /* List entry for device flows. */
503 uint32_t refcnt; /* Reference counter. */
504 uint32_t appcnt; /* Apply/Remove counter. */
506 uint32_t rix_flow; /* Built flow for copy. */
509 /* Table data structure of the hash organization. */
510 struct mlx5_flow_tbl_data_entry {
511 struct mlx5_hlist_entry entry;
512 /**< hash list entry, 64-bits key inside. */
513 struct mlx5_flow_tbl_resource tbl;
514 /**< flow table resource. */
515 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
516 /**< matchers' header associated with the flow table. */
517 struct mlx5_flow_dv_jump_tbl_resource jump;
518 /**< jump resource, at most one for each table created. */
519 uint32_t idx; /**< index for the indexed mempool. */
522 /* Verbs specification header. */
523 struct ibv_spec_header {
524 enum ibv_flow_spec_type type;
528 /* RSS description. */
529 struct mlx5_flow_rss_desc {
531 uint32_t queue_num; /**< Number of entries in @p queue. */
532 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
533 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
534 uint16_t queue[]; /**< Destination queues to redirect traffic to. */
537 /* PMD flow priority for tunnel */
538 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
539 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
542 /** Device flow handle structure for DV mode only. */
543 struct mlx5_flow_handle_dv {
545 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
546 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
547 /**< Pointer to modify header resource in cache. */
548 uint32_t rix_encap_decap;
549 /**< Index to encap/decap resource in cache. */
550 uint32_t rix_push_vlan;
551 /**< Index to push VLAN action resource in cache. */
553 /**< Index to the tag action. */
556 /** Device flow handle structure: used both for creating & destroying. */
557 struct mlx5_flow_handle {
558 SILIST_ENTRY(uint32_t)next;
559 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
560 /**< Index to next device flow handle. */
562 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
563 void *drv_flow; /**< pointer to driver flow object. */
564 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
565 uint32_t mark:1; /**< Metadate rxq mark flag. */
566 uint32_t fate_action:3; /**< Fate action type. */
568 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
569 uint32_t rix_jump; /**< Index to the jump action resource. */
570 uint32_t rix_port_id_action;
571 /**< Index to port ID action resource. */
573 /**< Generic value indicates the fate action. */
574 uint32_t rix_default_fate;
575 /**< Indicates default miss fate action. */
577 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
578 struct mlx5_flow_handle_dv dvh;
583 * Size for Verbs device flow handle structure only. Do not use the DV only
584 * structure in Verbs. No DV flows attributes will be accessed.
585 * Macro offsetof() could also be used here.
587 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
588 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
589 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
591 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
595 * Max number of actions per DV flow.
596 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
597 * in rdma-core file providers/mlx5/verbs.c.
599 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
601 /** Device flow structure only for DV flow creation. */
602 struct mlx5_flow_dv_workspace {
603 uint32_t group; /**< The group index. */
604 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
605 int actions_n; /**< number of actions. */
606 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
607 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
608 /**< Pointer to encap/decap resource in cache. */
609 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
610 /**< Pointer to push VLAN action resource in cache. */
611 struct mlx5_flow_dv_tag_resource *tag_resource;
612 /**< pointer to the tag action. */
613 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
614 /**< Pointer to port ID action resource. */
615 struct mlx5_flow_dv_jump_tbl_resource *jump;
616 /**< Pointer to the jump action resource. */
617 struct mlx5_flow_dv_match_params value;
618 /**< Holds the value that the packet is compared to. */
622 * Maximal Verbs flow specifications & actions size.
623 * Some elements are mutually exclusive, but enough space should be allocated.
624 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
625 * 2. One tunnel header (exception: GRE + MPLS),
626 * SPEC length: GRE == tunnel.
627 * Actions: 1. 1 Mark OR Flag.
628 * 2. 1 Drop (if any).
629 * 3. No limitation for counters, but it makes no sense to support too
630 * many counters in a single device flow.
632 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
633 #define MLX5_VERBS_MAX_SPEC_SIZE \
635 (2 * (sizeof(struct ibv_flow_spec_eth) + \
636 sizeof(struct ibv_flow_spec_ipv6) + \
637 sizeof(struct ibv_flow_spec_tcp_udp)) + \
638 sizeof(struct ibv_flow_spec_gre) + \
639 sizeof(struct ibv_flow_spec_mpls)) \
642 #define MLX5_VERBS_MAX_SPEC_SIZE \
644 (2 * (sizeof(struct ibv_flow_spec_eth) + \
645 sizeof(struct ibv_flow_spec_ipv6) + \
646 sizeof(struct ibv_flow_spec_tcp_udp)) + \
647 sizeof(struct ibv_flow_spec_tunnel)) \
651 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
652 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
653 #define MLX5_VERBS_MAX_ACT_SIZE \
655 sizeof(struct ibv_flow_spec_action_tag) + \
656 sizeof(struct ibv_flow_spec_action_drop) + \
657 sizeof(struct ibv_flow_spec_counter_action) * 4 \
660 #define MLX5_VERBS_MAX_ACT_SIZE \
662 sizeof(struct ibv_flow_spec_action_tag) + \
663 sizeof(struct ibv_flow_spec_action_drop) \
667 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
668 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
670 /** Device flow structure only for Verbs flow creation. */
671 struct mlx5_flow_verbs_workspace {
672 unsigned int size; /**< Size of the attribute. */
673 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
674 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
675 /**< Specifications & actions buffer of verbs flow. */
678 /** Maximal number of device sub-flows supported. */
679 #define MLX5_NUM_MAX_DEV_FLOWS 32
681 /** Device flow structure. */
683 struct rte_flow *flow; /**< Pointer to the main flow. */
684 uint32_t flow_idx; /**< The memory pool index to the main flow. */
685 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
687 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
688 bool external; /**< true if the flow is created external to PMD. */
689 uint8_t ingress; /**< 1 if the flow is ingress. */
691 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
692 struct mlx5_flow_dv_workspace dv;
694 struct mlx5_flow_verbs_workspace verbs;
696 struct mlx5_flow_handle *handle;
697 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
700 /* Flow meter state. */
701 #define MLX5_FLOW_METER_DISABLE 0
702 #define MLX5_FLOW_METER_ENABLE 1
704 #define MLX5_MAN_WIDTH 8
705 /* Modify this value if enum rte_mtr_color changes. */
706 #define RTE_MTR_DROPPED RTE_COLORS
708 /* Meter policer statistics */
709 struct mlx5_flow_policer_stats {
710 uint32_t cnt[RTE_COLORS + 1];
711 /**< Color counter, extra for drop. */
713 /**< Statistics mask for the colors. */
716 /* Meter table structure. */
717 struct mlx5_meter_domain_info {
718 struct mlx5_flow_tbl_resource *tbl;
720 struct mlx5_flow_tbl_resource *sfx_tbl;
721 /**< Meter suffix table. */
723 /**< Meter color not match default criteria. */
725 /**< Meter color match criteria. */
727 /**< Meter match action. */
728 void *policer_rules[RTE_MTR_DROPPED + 1];
729 /**< Meter policer for the match. */
732 /* Meter table set for TX RX FDB. */
733 struct mlx5_meter_domains_infos {
735 /**< Table user count. */
736 struct mlx5_meter_domain_info egress;
737 /**< TX meter table. */
738 struct mlx5_meter_domain_info ingress;
739 /**< RX meter table. */
740 struct mlx5_meter_domain_info transfer;
741 /**< FDB meter table. */
743 /**< Drop action as not matched. */
744 void *count_actns[RTE_MTR_DROPPED + 1];
745 /**< Counters for match and unmatched statistics. */
746 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
747 /**< Flow meter parameter. */
749 /**< Flow meter parameter size. */
751 /**< Flow meter action. */
754 /* Meter parameter structure. */
755 struct mlx5_flow_meter {
756 TAILQ_ENTRY(mlx5_flow_meter) next;
757 /**< Pointer to the next flow meter structure. */
758 uint32_t idx; /* Index to meter object. */
761 struct mlx5_flow_meter_profile *profile;
762 /**< Meter profile parameters. */
764 /** Policer actions (per meter output color). */
765 enum rte_mtr_policer_action action[RTE_COLORS];
767 /** Set of stats counters to be enabled.
768 * @see enum rte_mtr_stats_type
772 /**< Rule applies to ingress traffic. */
775 /**< Rule applies to egress traffic. */
778 * Instead of simply matching the properties of traffic as it would
779 * appear on a given DPDK port ID, enabling this attribute transfers
780 * a flow rule to the lowest possible level of any device endpoints
781 * found in the pattern.
783 * When supported, this effectively enables an application to
784 * re-route traffic not necessarily intended for it (e.g. coming
785 * from or addressed to different physical ports, VFs or
786 * applications) at the device level.
788 * It complements the behavior of some pattern items such as
789 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
791 * When transferring flow rules, ingress and egress attributes keep
792 * their original meaning, as if processing traffic emitted or
793 * received by the application.
796 struct mlx5_meter_domains_infos *mfts;
797 /**< Flow table created for this meter. */
798 struct mlx5_flow_policer_stats policer_stats;
799 /**< Meter policer statistics. */
802 uint32_t active_state:1;
805 /**< Meter shared or not. */
808 /* RFC2697 parameter structure. */
809 struct mlx5_flow_meter_srtcm_rfc2697_prm {
810 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
811 uint32_t cbs_exponent:5;
812 uint32_t cbs_mantissa:8;
813 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
814 uint32_t cir_exponent:5;
815 uint32_t cir_mantissa:8;
816 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
817 uint32_t ebs_exponent:5;
818 uint32_t ebs_mantissa:8;
821 /* Flow meter profile structure. */
822 struct mlx5_flow_meter_profile {
823 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
824 /**< Pointer to the next flow meter structure. */
825 uint32_t meter_profile_id; /**< Profile id. */
826 struct rte_mtr_meter_profile profile; /**< Profile detail. */
828 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
829 /**< srtcm_rfc2697 struct. */
831 uint32_t ref_cnt; /**< Use count. */
834 /* Fdir flow structure */
835 struct mlx5_fdir_flow {
836 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */
837 struct mlx5_fdir *fdir; /* Pointer to fdir. */
838 uint32_t rix_flow; /* Index to flow. */
841 #define HAIRPIN_FLOW_ID_BITS 28
843 /* Flow structure. */
845 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
846 uint32_t dev_handles;
847 /**< Device flow handles that are part of the flow. */
848 uint32_t drv_type:2; /**< Driver type. */
849 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */
850 uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS;
851 /**< The flow id used for hairpin. */
852 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
853 uint32_t rix_mreg_copy;
854 /**< Index to metadata register copy table resource. */
855 uint32_t counter; /**< Holds flow counter. */
856 uint16_t meter; /**< Holds flow meter id. */
859 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
860 const struct rte_flow_attr *attr,
861 const struct rte_flow_item items[],
862 const struct rte_flow_action actions[],
865 struct rte_flow_error *error);
866 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
867 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
868 const struct rte_flow_item items[],
869 const struct rte_flow_action actions[], struct rte_flow_error *error);
870 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
871 struct mlx5_flow *dev_flow,
872 const struct rte_flow_attr *attr,
873 const struct rte_flow_item items[],
874 const struct rte_flow_action actions[],
875 struct rte_flow_error *error);
876 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
877 struct rte_flow_error *error);
878 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
879 struct rte_flow *flow);
880 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
881 struct rte_flow *flow);
882 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
883 struct rte_flow *flow,
884 const struct rte_flow_action *actions,
886 struct rte_flow_error *error);
887 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
888 (struct rte_eth_dev *dev,
889 const struct mlx5_flow_meter *fm);
890 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
891 struct mlx5_meter_domains_infos *tbls);
892 typedef int (*mlx5_flow_create_policer_rules_t)
893 (struct rte_eth_dev *dev,
894 struct mlx5_flow_meter *fm,
895 const struct rte_flow_attr *attr);
896 typedef int (*mlx5_flow_destroy_policer_rules_t)
897 (struct rte_eth_dev *dev,
898 const struct mlx5_flow_meter *fm,
899 const struct rte_flow_attr *attr);
900 typedef uint32_t (*mlx5_flow_counter_alloc_t)
901 (struct rte_eth_dev *dev);
902 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
904 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
906 bool clear, uint64_t *pkts,
908 typedef int (*mlx5_flow_get_aged_flows_t)
909 (struct rte_eth_dev *dev,
911 uint32_t nb_contexts,
912 struct rte_flow_error *error);
913 struct mlx5_flow_driver_ops {
914 mlx5_flow_validate_t validate;
915 mlx5_flow_prepare_t prepare;
916 mlx5_flow_translate_t translate;
917 mlx5_flow_apply_t apply;
918 mlx5_flow_remove_t remove;
919 mlx5_flow_destroy_t destroy;
920 mlx5_flow_query_t query;
921 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
922 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
923 mlx5_flow_create_policer_rules_t create_policer_rules;
924 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
925 mlx5_flow_counter_alloc_t counter_alloc;
926 mlx5_flow_counter_free_t counter_free;
927 mlx5_flow_counter_query_t counter_query;
928 mlx5_flow_get_aged_flows_t get_aged_flows;
933 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id);
934 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
935 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
936 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
938 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
939 bool external, uint32_t group, bool fdb_def_rule,
940 uint32_t *table, struct rte_flow_error *error);
941 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
942 int tunnel, uint64_t layer_types,
943 uint64_t hash_fields);
944 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
945 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
946 uint32_t subpriority);
947 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
948 enum mlx5_feature_name feature,
950 struct rte_flow_error *error);
951 const struct rte_flow_action *mlx5_flow_find_action
952 (const struct rte_flow_action *actions,
953 enum rte_flow_action_type action);
954 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
955 const struct rte_flow_attr *attr,
956 struct rte_flow_error *error);
957 int mlx5_flow_validate_action_drop(uint64_t action_flags,
958 const struct rte_flow_attr *attr,
959 struct rte_flow_error *error);
960 int mlx5_flow_validate_action_flag(uint64_t action_flags,
961 const struct rte_flow_attr *attr,
962 struct rte_flow_error *error);
963 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
964 uint64_t action_flags,
965 const struct rte_flow_attr *attr,
966 struct rte_flow_error *error);
967 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
968 uint64_t action_flags,
969 struct rte_eth_dev *dev,
970 const struct rte_flow_attr *attr,
971 struct rte_flow_error *error);
972 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
973 uint64_t action_flags,
974 struct rte_eth_dev *dev,
975 const struct rte_flow_attr *attr,
977 struct rte_flow_error *error);
978 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
979 const struct rte_flow_attr *attr,
980 struct rte_flow_error *error);
981 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
982 const struct rte_flow_attr *attributes,
983 struct rte_flow_error *error);
984 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
986 const uint8_t *nic_mask,
988 struct rte_flow_error *error);
989 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
991 struct rte_flow_error *error);
992 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
994 uint8_t target_protocol,
995 struct rte_flow_error *error);
996 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
998 const struct rte_flow_item *gre_item,
999 struct rte_flow_error *error);
1000 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1001 uint64_t item_flags,
1003 uint16_t ether_type,
1004 const struct rte_flow_item_ipv4 *acc_mask,
1005 struct rte_flow_error *error);
1006 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1007 uint64_t item_flags,
1009 uint16_t ether_type,
1010 const struct rte_flow_item_ipv6 *acc_mask,
1011 struct rte_flow_error *error);
1012 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1013 const struct rte_flow_item *item,
1014 uint64_t item_flags,
1015 uint64_t prev_layer,
1016 struct rte_flow_error *error);
1017 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1018 uint64_t item_flags,
1019 uint8_t target_protocol,
1020 const struct rte_flow_item_tcp *flow_mask,
1021 struct rte_flow_error *error);
1022 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1023 uint64_t item_flags,
1024 uint8_t target_protocol,
1025 struct rte_flow_error *error);
1026 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1027 uint64_t item_flags,
1028 struct rte_eth_dev *dev,
1029 struct rte_flow_error *error);
1030 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1031 uint64_t item_flags,
1032 struct rte_flow_error *error);
1033 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1034 uint64_t item_flags,
1035 struct rte_eth_dev *dev,
1036 struct rte_flow_error *error);
1037 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1038 uint64_t item_flags,
1039 uint8_t target_protocol,
1040 struct rte_flow_error *error);
1041 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1042 uint64_t item_flags,
1043 uint8_t target_protocol,
1044 struct rte_flow_error *error);
1045 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1046 uint64_t item_flags,
1047 uint8_t target_protocol,
1048 struct rte_flow_error *error);
1049 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1050 uint64_t item_flags,
1051 struct rte_eth_dev *dev,
1052 struct rte_flow_error *error);
1053 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1054 uint64_t item_flags,
1056 uint16_t ether_type,
1057 const struct rte_flow_item_ecpri *acc_mask,
1058 struct rte_flow_error *error);
1059 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1060 (struct rte_eth_dev *dev,
1061 const struct mlx5_flow_meter *fm);
1062 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1063 struct mlx5_meter_domains_infos *tbl);
1064 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1065 struct mlx5_flow_meter *fm,
1066 const struct rte_flow_attr *attr);
1067 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1068 struct mlx5_flow_meter *fm,
1069 const struct rte_flow_attr *attr);
1070 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1071 struct rte_mtr_error *error);
1072 #endif /* RTE_PMD_MLX5_FLOW_H_ */