1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* Private rte flow items. */
22 enum mlx5_rte_flow_item_type {
23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
24 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
30 /* Private (internal) rte flow actions. */
31 enum mlx5_rte_flow_action_type {
32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
34 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
38 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
39 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
40 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
43 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
46 MLX5_INDIRECT_ACTION_TYPE_RSS,
47 MLX5_INDIRECT_ACTION_TYPE_AGE,
48 MLX5_INDIRECT_ACTION_TYPE_COUNT,
51 /* Matches on selected register. */
52 struct mlx5_rte_flow_item_tag {
57 /* Modify selected register. */
58 struct mlx5_rte_flow_action_set_tag {
65 struct mlx5_flow_action_copy_mreg {
70 /* Matches on source queue. */
71 struct mlx5_rte_flow_item_tx_queue {
75 /* Feature name to allocate metadata register. */
76 enum mlx5_feature_name {
91 /* Default queue number. */
92 #define MLX5_RSSQ_DEFAULT_NUM 16
94 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
95 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
96 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
97 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
98 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
99 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
101 /* Pattern inner Layer bits. */
102 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
103 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
104 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
105 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
106 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
107 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
109 /* Pattern tunnel Layer bits. */
110 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
111 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
112 #define MLX5_FLOW_LAYER_GRE (1u << 14)
113 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
114 /* List of tunnel Layer bits continued below. */
116 /* General pattern items bits. */
117 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
118 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
119 #define MLX5_FLOW_ITEM_TAG (1u << 18)
120 #define MLX5_FLOW_ITEM_MARK (1u << 19)
122 /* Pattern MISC bits. */
123 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
124 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
125 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
127 /* Pattern tunnel Layer bits (continued). */
128 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
129 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
130 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
131 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
134 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
136 /* Pattern tunnel Layer bits (continued). */
137 #define MLX5_FLOW_LAYER_GTP (1u << 28)
139 /* Pattern eCPRI Layer bit. */
140 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
142 /* IPv6 Fragment Extension Header bit. */
143 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
144 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
146 /* Pattern tunnel Layer bits (continued). */
147 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
148 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
150 /* INTEGRITY item bit */
151 #define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34)
154 #define MLX5_FLOW_LAYER_OUTER_L3 \
155 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
156 #define MLX5_FLOW_LAYER_OUTER_L4 \
157 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
158 #define MLX5_FLOW_LAYER_OUTER \
159 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
160 MLX5_FLOW_LAYER_OUTER_L4)
163 #define MLX5_FLOW_LAYER_TUNNEL \
164 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
165 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
166 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
167 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
170 #define MLX5_FLOW_LAYER_INNER_L3 \
171 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
172 #define MLX5_FLOW_LAYER_INNER_L4 \
173 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
174 #define MLX5_FLOW_LAYER_INNER \
175 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
176 MLX5_FLOW_LAYER_INNER_L4)
179 #define MLX5_FLOW_LAYER_L2 \
180 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
181 #define MLX5_FLOW_LAYER_L3_IPV4 \
182 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
183 #define MLX5_FLOW_LAYER_L3_IPV6 \
184 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
185 #define MLX5_FLOW_LAYER_L3 \
186 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
187 #define MLX5_FLOW_LAYER_L4 \
188 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
191 #define MLX5_FLOW_ACTION_DROP (1u << 0)
192 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
193 #define MLX5_FLOW_ACTION_RSS (1u << 2)
194 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
195 #define MLX5_FLOW_ACTION_MARK (1u << 4)
196 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
197 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
198 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
199 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
200 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
201 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
202 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
203 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
204 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
205 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
206 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
207 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
208 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
209 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
210 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
211 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
212 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
213 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
214 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
215 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
216 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
217 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
218 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
219 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
220 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
221 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
222 #define MLX5_FLOW_ACTION_METER (1ull << 31)
223 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
224 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
225 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
226 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
227 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
228 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
229 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
230 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
231 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
233 #define MLX5_FLOW_FATE_ACTIONS \
234 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
235 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
236 MLX5_FLOW_ACTION_DEFAULT_MISS | \
237 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
239 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
240 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
241 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
243 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
244 MLX5_FLOW_ACTION_SET_IPV4_DST | \
245 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
246 MLX5_FLOW_ACTION_SET_IPV6_DST | \
247 MLX5_FLOW_ACTION_SET_TP_SRC | \
248 MLX5_FLOW_ACTION_SET_TP_DST | \
249 MLX5_FLOW_ACTION_SET_TTL | \
250 MLX5_FLOW_ACTION_DEC_TTL | \
251 MLX5_FLOW_ACTION_SET_MAC_SRC | \
252 MLX5_FLOW_ACTION_SET_MAC_DST | \
253 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
254 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
255 MLX5_FLOW_ACTION_INC_TCP_ACK | \
256 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
257 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
258 MLX5_FLOW_ACTION_SET_TAG | \
259 MLX5_FLOW_ACTION_MARK_EXT | \
260 MLX5_FLOW_ACTION_SET_META | \
261 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
262 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
263 MLX5_FLOW_ACTION_MODIFY_FIELD)
265 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
266 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
268 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
271 #define IPPROTO_MPLS 137
274 /* UDP port number for MPLS */
275 #define MLX5_UDP_PORT_MPLS 6635
277 /* UDP port numbers for VxLAN. */
278 #define MLX5_UDP_PORT_VXLAN 4789
279 #define MLX5_UDP_PORT_VXLAN_GPE 4790
281 /* UDP port numbers for GENEVE. */
282 #define MLX5_UDP_PORT_GENEVE 6081
284 /* Lowest priority indicator. */
285 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
288 * Max priority for ingress\egress flow groups
289 * greater than 0 and for any transfer flow group.
290 * From user configation: 0 - 21843.
292 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
295 * Number of sub priorities.
296 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
297 * matching on the NIC (firmware dependent) L4 most have the higher priority
298 * followed by L3 and ending with L2.
300 #define MLX5_PRIORITY_MAP_L2 2
301 #define MLX5_PRIORITY_MAP_L3 1
302 #define MLX5_PRIORITY_MAP_L4 0
303 #define MLX5_PRIORITY_MAP_MAX 3
305 /* Valid layer type for IPV4 RSS. */
306 #define MLX5_IPV4_LAYER_TYPES \
307 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
308 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
309 ETH_RSS_NONFRAG_IPV4_OTHER)
311 /* IBV hash source bits for IPV4. */
312 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
314 /* Valid layer type for IPV6 RSS. */
315 #define MLX5_IPV6_LAYER_TYPES \
316 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
317 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
318 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
320 /* IBV hash source bits for IPV6. */
321 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
323 /* IBV hash bits for L3 SRC. */
324 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
326 /* IBV hash bits for L3 DST. */
327 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
329 /* IBV hash bits for TCP. */
330 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
331 IBV_RX_HASH_DST_PORT_TCP)
333 /* IBV hash bits for UDP. */
334 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
335 IBV_RX_HASH_DST_PORT_UDP)
337 /* IBV hash bits for L4 SRC. */
338 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
339 IBV_RX_HASH_SRC_PORT_UDP)
341 /* IBV hash bits for L4 DST. */
342 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
343 IBV_RX_HASH_DST_PORT_UDP)
345 /* Geneve header first 16Bit */
346 #define MLX5_GENEVE_VER_MASK 0x3
347 #define MLX5_GENEVE_VER_SHIFT 14
348 #define MLX5_GENEVE_VER_VAL(a) \
349 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
350 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
351 #define MLX5_GENEVE_OPTLEN_SHIFT 8
352 #define MLX5_GENEVE_OPTLEN_VAL(a) \
353 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
354 #define MLX5_GENEVE_OAMF_MASK 0x1
355 #define MLX5_GENEVE_OAMF_SHIFT 7
356 #define MLX5_GENEVE_OAMF_VAL(a) \
357 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
358 #define MLX5_GENEVE_CRITO_MASK 0x1
359 #define MLX5_GENEVE_CRITO_SHIFT 6
360 #define MLX5_GENEVE_CRITO_VAL(a) \
361 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
362 #define MLX5_GENEVE_RSVD_MASK 0x3F
363 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
365 * The length of the Geneve options fields, expressed in four byte multiples,
366 * not including the eight byte fixed tunnel.
368 #define MLX5_GENEVE_OPT_LEN_0 14
369 #define MLX5_GENEVE_OPT_LEN_1 63
371 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
372 sizeof(struct rte_ipv4_hdr))
373 /* GTP extension header flag. */
374 #define MLX5_GTP_EXT_HEADER_FLAG 4
376 /* GTP extension header max PDU type value. */
377 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
379 /* GTP extension header PDU type shift. */
380 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
382 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
383 #define MLX5_IPV4_FRAG_OFFSET_MASK \
384 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
386 /* Specific item's fields can accept a range of values (using spec and last). */
387 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
388 #define MLX5_ITEM_RANGE_ACCEPTED true
390 /* Software header modify action numbers of a flow. */
391 #define MLX5_ACT_NUM_MDF_IPV4 1
392 #define MLX5_ACT_NUM_MDF_IPV6 4
393 #define MLX5_ACT_NUM_MDF_MAC 2
394 #define MLX5_ACT_NUM_MDF_VID 1
395 #define MLX5_ACT_NUM_MDF_PORT 2
396 #define MLX5_ACT_NUM_MDF_TTL 1
397 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
398 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
399 #define MLX5_ACT_NUM_MDF_TCPACK 1
400 #define MLX5_ACT_NUM_SET_REG 1
401 #define MLX5_ACT_NUM_SET_TAG 1
402 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
403 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
404 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
405 #define MLX5_ACT_NUM_SET_DSCP 1
407 /* Maximum number of fields to modify in MODIFY_FIELD */
408 #define MLX5_ACT_MAX_MOD_FIELDS 5
410 enum mlx5_flow_drv_type {
413 MLX5_FLOW_TYPE_VERBS,
417 /* Fate action type. */
418 enum mlx5_flow_fate_type {
419 MLX5_FLOW_FATE_NONE, /* Egress flow. */
420 MLX5_FLOW_FATE_QUEUE,
422 MLX5_FLOW_FATE_PORT_ID,
424 MLX5_FLOW_FATE_DEFAULT_MISS,
425 MLX5_FLOW_FATE_SHARED_RSS,
429 /* Matcher PRM representation */
430 struct mlx5_flow_dv_match_params {
432 /**< Size of match value. Do NOT split size and key! */
433 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
434 /**< Matcher value. This value is used as the mask or as a key. */
437 /* Matcher structure. */
438 struct mlx5_flow_dv_matcher {
439 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
440 struct mlx5_flow_tbl_resource *tbl;
441 /**< Pointer to the table(group) the matcher associated with. */
442 void *matcher_object; /**< Pointer to DV matcher */
443 uint16_t crc; /**< CRC of key. */
444 uint16_t priority; /**< Priority of matcher. */
445 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
448 #define MLX5_ENCAP_MAX_LEN 132
450 /* Encap/decap resource structure. */
451 struct mlx5_flow_dv_encap_decap_resource {
452 struct mlx5_hlist_entry entry;
453 /* Pointer to next element. */
454 uint32_t refcnt; /**< Reference counter. */
456 /**< Encap/decap action object. */
457 uint8_t buf[MLX5_ENCAP_MAX_LEN];
459 uint8_t reformat_type;
461 uint64_t flags; /**< Flags for RDMA API. */
462 uint32_t idx; /**< Index for the index memory pool. */
465 /* Tag resource structure. */
466 struct mlx5_flow_dv_tag_resource {
467 struct mlx5_hlist_entry entry;
468 /**< hash list entry for tag resource, tag value as the key. */
470 /**< Tag action object. */
471 uint32_t refcnt; /**< Reference counter. */
472 uint32_t idx; /**< Index for the index memory pool. */
473 uint32_t tag_id; /**< Tag ID. */
477 * Number of modification commands.
478 * The maximal actions amount in FW is some constant, and it is 16 in the
479 * latest releases. In some old releases, it will be limited to 8.
480 * Since there is no interface to query the capacity, the maximal value should
481 * be used to allow PMD to create the flow. The validation will be done in the
482 * lower driver layer or FW. A failure will be returned if exceeds the maximal
483 * supported actions number on the root table.
484 * On non-root tables, there is no limitation, but 32 is enough right now.
486 #define MLX5_MAX_MODIFY_NUM 32
487 #define MLX5_ROOT_TBL_MODIFY_NUM 16
489 /* Modify resource structure */
490 struct mlx5_flow_dv_modify_hdr_resource {
491 struct mlx5_hlist_entry entry;
492 void *action; /**< Modify header action object. */
493 /* Key area for hash list matching: */
494 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
495 uint32_t actions_num; /**< Number of modification actions. */
496 uint64_t flags; /**< Flags for RDMA API. */
497 struct mlx5_modification_cmd actions[];
498 /**< Modification actions. */
501 /* Modify resource key of the hash organization. */
502 union mlx5_flow_modify_hdr_key {
504 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
505 uint32_t actions_num:5; /**< Number of modification actions. */
506 uint32_t group:19; /**< Flow group id. */
507 uint32_t cksum; /**< Actions check sum. */
509 uint64_t v64; /**< full 64bits value of key */
512 /* Jump action resource structure. */
513 struct mlx5_flow_dv_jump_tbl_resource {
514 void *action; /**< Pointer to the rdma core action. */
517 /* Port ID resource structure. */
518 struct mlx5_flow_dv_port_id_action_resource {
519 struct mlx5_cache_entry entry;
520 void *action; /**< Action object. */
521 uint32_t port_id; /**< Port ID value. */
522 uint32_t idx; /**< Indexed pool memory index. */
525 /* Push VLAN action resource structure */
526 struct mlx5_flow_dv_push_vlan_action_resource {
527 struct mlx5_cache_entry entry; /* Cache entry. */
528 void *action; /**< Action object. */
529 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
530 rte_be32_t vlan_tag; /**< VLAN tag value. */
531 uint32_t idx; /**< Indexed pool memory index. */
534 /* Metadata register copy table entry. */
535 struct mlx5_flow_mreg_copy_resource {
537 * Hash list entry for copy table.
538 * - Key is 32/64-bit MARK action ID.
539 * - MUST be the first entry.
541 struct mlx5_hlist_entry hlist_ent;
542 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
543 /* List entry for device flows. */
545 uint32_t rix_flow; /* Built flow for copy. */
549 /* Table tunnel parameter. */
550 struct mlx5_flow_tbl_tunnel_prm {
551 const struct mlx5_flow_tunnel *tunnel;
556 /* Table data structure of the hash organization. */
557 struct mlx5_flow_tbl_data_entry {
558 struct mlx5_hlist_entry entry;
559 /**< hash list entry, 64-bits key inside. */
560 struct mlx5_flow_tbl_resource tbl;
561 /**< flow table resource. */
562 struct mlx5_cache_list matchers;
563 /**< matchers' header associated with the flow table. */
564 struct mlx5_flow_dv_jump_tbl_resource jump;
565 /**< jump resource, at most one for each table created. */
566 uint32_t idx; /**< index for the indexed mempool. */
567 /**< tunnel offload */
568 const struct mlx5_flow_tunnel *tunnel;
571 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
572 uint32_t is_egress:1; /**< Egress table. */
573 uint32_t is_transfer:1; /**< Transfer table. */
574 uint32_t dummy:1; /**< DR table. */
575 uint32_t id:22; /**< Table ID. */
576 uint32_t reserve:5; /**< Reserved to future using. */
577 uint32_t level; /**< Table level. */
580 /* Sub rdma-core actions list. */
581 struct mlx5_flow_sub_actions_list {
582 uint32_t actions_num; /**< Number of sample actions. */
583 uint64_t action_flags;
584 void *dr_queue_action;
587 void *dr_port_id_action;
588 void *dr_encap_action;
589 void *dr_jump_action;
592 /* Sample sub-actions resource list. */
593 struct mlx5_flow_sub_actions_idx {
594 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
595 uint32_t rix_tag; /**< Index to the tag action. */
596 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
597 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
598 uint32_t rix_jump; /**< Index to the jump action resource. */
601 /* Sample action resource structure. */
602 struct mlx5_flow_dv_sample_resource {
603 struct mlx5_cache_entry entry; /**< Cache entry. */
605 void *verbs_action; /**< Verbs sample action object. */
606 void **sub_actions; /**< Sample sub-action array. */
608 struct rte_eth_dev *dev; /**< Device registers the action. */
609 uint32_t idx; /** Sample object index. */
610 uint8_t ft_type; /** Flow Table Type */
611 uint32_t ft_id; /** Flow Table Level */
612 uint32_t ratio; /** Sample Ratio */
613 uint64_t set_action; /** Restore reg_c0 value */
614 void *normal_path_tbl; /** Flow Table pointer */
615 struct mlx5_flow_sub_actions_idx sample_idx;
616 /**< Action index resources. */
617 struct mlx5_flow_sub_actions_list sample_act;
618 /**< Action resources. */
621 #define MLX5_MAX_DEST_NUM 2
623 /* Destination array action resource structure. */
624 struct mlx5_flow_dv_dest_array_resource {
625 struct mlx5_cache_entry entry; /**< Cache entry. */
626 uint32_t idx; /** Destination array action object index. */
627 uint8_t ft_type; /** Flow Table Type */
628 uint8_t num_of_dest; /**< Number of destination actions. */
629 struct rte_eth_dev *dev; /**< Device registers the action. */
630 void *action; /**< Pointer to the rdma core action. */
631 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
632 /**< Action index resources. */
633 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
634 /**< Action resources. */
637 /* PMD flow priority for tunnel */
638 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
639 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
642 /** Device flow handle structure for DV mode only. */
643 struct mlx5_flow_handle_dv {
645 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
646 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
647 /**< Pointer to modify header resource in cache. */
648 uint32_t rix_encap_decap;
649 /**< Index to encap/decap resource in cache. */
650 uint32_t rix_push_vlan;
651 /**< Index to push VLAN action resource in cache. */
653 /**< Index to the tag action. */
655 /**< Index to sample action resource in cache. */
656 uint32_t rix_dest_array;
657 /**< Index to destination array resource in cache. */
660 /** Device flow handle structure: used both for creating & destroying. */
661 struct mlx5_flow_handle {
662 SILIST_ENTRY(uint32_t)next;
663 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
664 /**< Index to next device flow handle. */
666 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
667 void *drv_flow; /**< pointer to driver flow object. */
668 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
669 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
670 uint32_t mark:1; /**< Metadate rxq mark flag. */
671 uint32_t fate_action:3; /**< Fate action type. */
673 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
674 uint32_t rix_jump; /**< Index to the jump action resource. */
675 uint32_t rix_port_id_action;
676 /**< Index to port ID action resource. */
678 /**< Generic value indicates the fate action. */
679 uint32_t rix_default_fate;
680 /**< Indicates default miss fate action. */
682 /**< Indicates shared RSS fate action. */
684 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
685 struct mlx5_flow_handle_dv dvh;
690 * Size for Verbs device flow handle structure only. Do not use the DV only
691 * structure in Verbs. No DV flows attributes will be accessed.
692 * Macro offsetof() could also be used here.
694 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
695 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
696 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
698 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
701 /** Device flow structure only for DV flow creation. */
702 struct mlx5_flow_dv_workspace {
703 uint32_t group; /**< The group index. */
704 uint32_t table_id; /**< Flow table identifier. */
705 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
706 int actions_n; /**< number of actions. */
707 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
708 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
709 /**< Pointer to encap/decap resource in cache. */
710 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
711 /**< Pointer to push VLAN action resource in cache. */
712 struct mlx5_flow_dv_tag_resource *tag_resource;
713 /**< pointer to the tag action. */
714 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
715 /**< Pointer to port ID action resource. */
716 struct mlx5_flow_dv_jump_tbl_resource *jump;
717 /**< Pointer to the jump action resource. */
718 struct mlx5_flow_dv_match_params value;
719 /**< Holds the value that the packet is compared to. */
720 struct mlx5_flow_dv_sample_resource *sample_res;
721 /**< Pointer to the sample action resource. */
722 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
723 /**< Pointer to the destination array resource. */
726 #ifdef HAVE_INFINIBAND_VERBS_H
728 * Maximal Verbs flow specifications & actions size.
729 * Some elements are mutually exclusive, but enough space should be allocated.
730 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
731 * 2. One tunnel header (exception: GRE + MPLS),
732 * SPEC length: GRE == tunnel.
733 * Actions: 1. 1 Mark OR Flag.
734 * 2. 1 Drop (if any).
735 * 3. No limitation for counters, but it makes no sense to support too
736 * many counters in a single device flow.
738 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
739 #define MLX5_VERBS_MAX_SPEC_SIZE \
741 (2 * (sizeof(struct ibv_flow_spec_eth) + \
742 sizeof(struct ibv_flow_spec_ipv6) + \
743 sizeof(struct ibv_flow_spec_tcp_udp)) + \
744 sizeof(struct ibv_flow_spec_gre) + \
745 sizeof(struct ibv_flow_spec_mpls)) \
748 #define MLX5_VERBS_MAX_SPEC_SIZE \
750 (2 * (sizeof(struct ibv_flow_spec_eth) + \
751 sizeof(struct ibv_flow_spec_ipv6) + \
752 sizeof(struct ibv_flow_spec_tcp_udp)) + \
753 sizeof(struct ibv_flow_spec_tunnel)) \
757 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
758 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
759 #define MLX5_VERBS_MAX_ACT_SIZE \
761 sizeof(struct ibv_flow_spec_action_tag) + \
762 sizeof(struct ibv_flow_spec_action_drop) + \
763 sizeof(struct ibv_flow_spec_counter_action) * 4 \
766 #define MLX5_VERBS_MAX_ACT_SIZE \
768 sizeof(struct ibv_flow_spec_action_tag) + \
769 sizeof(struct ibv_flow_spec_action_drop) \
773 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
774 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
776 /** Device flow structure only for Verbs flow creation. */
777 struct mlx5_flow_verbs_workspace {
778 unsigned int size; /**< Size of the attribute. */
779 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
780 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
781 /**< Specifications & actions buffer of verbs flow. */
783 #endif /* HAVE_INFINIBAND_VERBS_H */
785 #define MLX5_SCALE_FLOW_GROUP_BIT 0
786 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
788 /** Maximal number of device sub-flows supported. */
789 #define MLX5_NUM_MAX_DEV_FLOWS 32
791 /** Device flow structure. */
794 struct rte_flow *flow; /**< Pointer to the main flow. */
795 uint32_t flow_idx; /**< The memory pool index to the main flow. */
796 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
798 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
799 bool external; /**< true if the flow is created external to PMD. */
800 uint8_t ingress:1; /**< 1 if the flow is ingress. */
801 uint8_t skip_scale:2;
803 * Each Bit be set to 1 if Skip the scale the flow group with factor.
804 * If bit0 be set to 1, then skip the scale the original flow group;
805 * If bit1 be set to 1, then skip the scale the jump flow group if
806 * having jump action.
807 * 00: Enable scale in a flow, default value.
808 * 01: Skip scale the flow group with factor, enable scale the group
810 * 10: Enable scale the group with factor, skip scale the group of
812 * 11: Skip scale the table with factor both for flow group and jump
816 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
817 struct mlx5_flow_dv_workspace dv;
819 #ifdef HAVE_INFINIBAND_VERBS_H
820 struct mlx5_flow_verbs_workspace verbs;
823 struct mlx5_flow_handle *handle;
824 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
825 const struct mlx5_flow_tunnel *tunnel;
828 /* Flow meter state. */
829 #define MLX5_FLOW_METER_DISABLE 0
830 #define MLX5_FLOW_METER_ENABLE 1
832 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
833 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
835 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
837 #define MLX5_MAN_WIDTH 8
838 /* Legacy Meter parameter structure. */
839 struct mlx5_legacy_flow_meter {
840 struct mlx5_flow_meter_info fm;
841 /* Must be the first in struct. */
842 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
843 /**< Pointer to the next flow meter structure. */
845 /* Index to meter object. */
848 #define MLX5_MAX_TUNNELS 256
849 #define MLX5_TNL_MISS_RULE_PRIORITY 3
850 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
853 * When tunnel offload is active, all JUMP group ids are converted
854 * using the same method. That conversion is applied both to tunnel and
855 * regular rule types.
856 * Group ids used in tunnel rules are relative to it's tunnel (!).
857 * Application can create number of steer rules, using the same
858 * tunnel, with different group id in each rule.
859 * Each tunnel stores its groups internally in PMD tunnel object.
860 * Groups used in regular rules do not belong to any tunnel and are stored
864 struct mlx5_flow_tunnel {
865 LIST_ENTRY(mlx5_flow_tunnel) chain;
866 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
867 uint32_t tunnel_id; /** unique tunnel ID */
869 struct rte_flow_action action;
870 struct rte_flow_item item;
871 struct mlx5_hlist *groups; /** tunnel groups */
874 /** PMD tunnel related context */
875 struct mlx5_flow_tunnel_hub {
877 * Access to the list MUST be MT protected
879 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
880 /* protect access to the tunnels list */
882 struct mlx5_hlist *groups; /** non tunnel groups */
885 /* convert jump group to flow table ID in tunnel rules */
886 struct tunnel_tbl_entry {
887 struct mlx5_hlist_entry hash;
893 static inline uint32_t
894 tunnel_id_to_flow_tbl(uint32_t id)
896 return id | (1u << 16);
899 static inline uint32_t
900 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
902 return flow_tbl & ~(1u << 16);
905 union tunnel_tbl_key {
913 static inline struct mlx5_flow_tunnel_hub *
914 mlx5_tunnel_hub(struct rte_eth_dev *dev)
916 struct mlx5_priv *priv = dev->data->dev_private;
917 return priv->sh->tunnel_hub;
921 is_tunnel_offload_active(struct rte_eth_dev *dev)
923 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
924 struct mlx5_priv *priv = dev->data->dev_private;
925 return !!priv->config.dv_miss_info;
933 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
934 __rte_unused const struct rte_flow_attr *attr,
935 __rte_unused const struct rte_flow_item items[],
936 __rte_unused const struct rte_flow_action actions[])
938 return (items[0].type == (typeof(items[0].type))
939 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
943 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
944 __rte_unused const struct rte_flow_attr *attr,
945 __rte_unused const struct rte_flow_item items[],
946 __rte_unused const struct rte_flow_action actions[])
948 return (actions[0].type == (typeof(actions[0].type))
949 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
952 static inline const struct mlx5_flow_tunnel *
953 flow_actions_to_tunnel(const struct rte_flow_action actions[])
955 return actions[0].conf;
958 static inline const struct mlx5_flow_tunnel *
959 flow_items_to_tunnel(const struct rte_flow_item items[])
961 return items[0].spec;
964 /* Flow structure. */
966 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
967 uint32_t dev_handles;
968 /**< Device flow handles that are part of the flow. */
969 uint32_t drv_type:2; /**< Driver type. */
971 uint32_t meter:24; /**< Holds flow meter id. */
972 uint32_t rix_mreg_copy;
973 /**< Index to metadata register copy table resource. */
974 uint32_t counter; /**< Holds flow counter. */
975 uint32_t tunnel_id; /**< Tunnel id */
976 uint32_t age; /**< Holds ASO age bit index. */
977 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
981 * Define list of valid combinations of RX Hash fields
982 * (see enum ibv_rx_hash_fields).
984 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
985 #define MLX5_RSS_HASH_IPV4_TCP \
986 (MLX5_RSS_HASH_IPV4 | \
987 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
988 #define MLX5_RSS_HASH_IPV4_UDP \
989 (MLX5_RSS_HASH_IPV4 | \
990 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
991 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
992 #define MLX5_RSS_HASH_IPV6_TCP \
993 (MLX5_RSS_HASH_IPV6 | \
994 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
995 #define MLX5_RSS_HASH_IPV6_UDP \
996 (MLX5_RSS_HASH_IPV6 | \
997 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
998 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
999 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1000 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1001 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1002 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1003 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1004 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1005 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1006 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1007 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1008 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1009 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1010 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1011 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1012 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1013 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1014 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1015 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1016 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1017 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1018 #define MLX5_RSS_HASH_NONE 0ULL
1021 /* extract next protocol type from Ethernet & VLAN headers */
1022 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1023 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1024 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1025 (_prt) = rte_be_to_cpu_16((_prt)); \
1028 /* array of valid combinations of RX Hash fields for RSS */
1029 static const uint64_t mlx5_rss_hash_fields[] = {
1031 MLX5_RSS_HASH_IPV4_TCP,
1032 MLX5_RSS_HASH_IPV4_UDP,
1034 MLX5_RSS_HASH_IPV6_TCP,
1035 MLX5_RSS_HASH_IPV6_UDP,
1039 /* Shared RSS action structure */
1040 struct mlx5_shared_action_rss {
1041 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1042 uint32_t refcnt; /**< Atomically accessed refcnt. */
1043 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1044 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1045 struct mlx5_ind_table_obj *ind_tbl;
1046 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1047 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1048 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1049 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1052 struct rte_flow_action_handle {
1056 /* Thread specific flow workspace intermediate data. */
1057 struct mlx5_flow_workspace {
1058 /* If creating another flow in same thread, push new as stack. */
1059 struct mlx5_flow_workspace *prev;
1060 struct mlx5_flow_workspace *next;
1061 uint32_t inuse; /* can't create new flow with current. */
1062 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1063 struct mlx5_flow_rss_desc rss_desc;
1064 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1065 uint32_t flow_idx; /* Intermediate device flow index. */
1066 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1067 uint32_t skip_matcher_reg:1;
1068 /* Indicates if need to skip matcher register in translate. */
1071 struct mlx5_flow_split_info {
1073 /**< True if flow is created by request external to PMD. */
1074 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1075 uint32_t flow_idx; /**< This memory pool index to the flow. */
1076 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1077 uint64_t prefix_layers; /**< Prefix subflow layers. */
1078 uint32_t table_id; /**< Flow table identifier. */
1081 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1082 const struct rte_flow_attr *attr,
1083 const struct rte_flow_item items[],
1084 const struct rte_flow_action actions[],
1087 struct rte_flow_error *error);
1088 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1089 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1090 const struct rte_flow_item items[],
1091 const struct rte_flow_action actions[], struct rte_flow_error *error);
1092 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1093 struct mlx5_flow *dev_flow,
1094 const struct rte_flow_attr *attr,
1095 const struct rte_flow_item items[],
1096 const struct rte_flow_action actions[],
1097 struct rte_flow_error *error);
1098 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1099 struct rte_flow_error *error);
1100 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1101 struct rte_flow *flow);
1102 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1103 struct rte_flow *flow);
1104 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1105 struct rte_flow *flow,
1106 const struct rte_flow_action *actions,
1108 struct rte_flow_error *error);
1109 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1110 struct mlx5_flow_meter_info *fm,
1112 uint8_t domain_bitmap);
1113 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1114 struct mlx5_flow_meter_info *fm);
1115 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1116 typedef struct mlx5_flow_meter_sub_policy *
1117 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1118 (struct rte_eth_dev *dev,
1119 struct mlx5_flow_meter_policy *mtr_policy,
1120 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1121 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1122 (struct rte_eth_dev *dev);
1123 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1125 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1126 (struct rte_eth_dev *dev);
1127 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1129 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1131 bool clear, uint64_t *pkts,
1133 typedef int (*mlx5_flow_get_aged_flows_t)
1134 (struct rte_eth_dev *dev,
1136 uint32_t nb_contexts,
1137 struct rte_flow_error *error);
1138 typedef int (*mlx5_flow_action_validate_t)
1139 (struct rte_eth_dev *dev,
1140 const struct rte_flow_indir_action_conf *conf,
1141 const struct rte_flow_action *action,
1142 struct rte_flow_error *error);
1143 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1144 (struct rte_eth_dev *dev,
1145 const struct rte_flow_indir_action_conf *conf,
1146 const struct rte_flow_action *action,
1147 struct rte_flow_error *error);
1148 typedef int (*mlx5_flow_action_destroy_t)
1149 (struct rte_eth_dev *dev,
1150 struct rte_flow_action_handle *action,
1151 struct rte_flow_error *error);
1152 typedef int (*mlx5_flow_action_update_t)
1153 (struct rte_eth_dev *dev,
1154 struct rte_flow_action_handle *action,
1156 struct rte_flow_error *error);
1157 typedef int (*mlx5_flow_action_query_t)
1158 (struct rte_eth_dev *dev,
1159 const struct rte_flow_action_handle *action,
1161 struct rte_flow_error *error);
1162 typedef int (*mlx5_flow_sync_domain_t)
1163 (struct rte_eth_dev *dev,
1166 typedef int (*mlx5_flow_validate_mtr_acts_t)
1167 (struct rte_eth_dev *dev,
1168 const struct rte_flow_action *actions[RTE_COLORS],
1169 struct rte_flow_attr *attr,
1171 uint8_t *domain_bitmap,
1172 bool *is_def_policy,
1173 struct rte_mtr_error *error);
1174 typedef int (*mlx5_flow_create_mtr_acts_t)
1175 (struct rte_eth_dev *dev,
1176 struct mlx5_flow_meter_policy *mtr_policy,
1177 const struct rte_flow_action *actions[RTE_COLORS],
1178 struct rte_mtr_error *error);
1179 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1180 (struct rte_eth_dev *dev,
1181 struct mlx5_flow_meter_policy *mtr_policy);
1182 typedef int (*mlx5_flow_create_policy_rules_t)
1183 (struct rte_eth_dev *dev,
1184 struct mlx5_flow_meter_policy *mtr_policy);
1185 typedef void (*mlx5_flow_destroy_policy_rules_t)
1186 (struct rte_eth_dev *dev,
1187 struct mlx5_flow_meter_policy *mtr_policy);
1188 typedef int (*mlx5_flow_create_def_policy_t)
1189 (struct rte_eth_dev *dev);
1190 typedef void (*mlx5_flow_destroy_def_policy_t)
1191 (struct rte_eth_dev *dev);
1193 struct mlx5_flow_driver_ops {
1194 mlx5_flow_validate_t validate;
1195 mlx5_flow_prepare_t prepare;
1196 mlx5_flow_translate_t translate;
1197 mlx5_flow_apply_t apply;
1198 mlx5_flow_remove_t remove;
1199 mlx5_flow_destroy_t destroy;
1200 mlx5_flow_query_t query;
1201 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1202 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1203 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1204 mlx5_flow_mtr_alloc_t create_meter;
1205 mlx5_flow_mtr_free_t free_meter;
1206 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1207 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1208 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1209 mlx5_flow_create_policy_rules_t create_policy_rules;
1210 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1211 mlx5_flow_create_def_policy_t create_def_policy;
1212 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1213 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1214 mlx5_flow_counter_alloc_t counter_alloc;
1215 mlx5_flow_counter_free_t counter_free;
1216 mlx5_flow_counter_query_t counter_query;
1217 mlx5_flow_get_aged_flows_t get_aged_flows;
1218 mlx5_flow_action_validate_t action_validate;
1219 mlx5_flow_action_create_t action_create;
1220 mlx5_flow_action_destroy_t action_destroy;
1221 mlx5_flow_action_update_t action_update;
1222 mlx5_flow_action_query_t action_query;
1223 mlx5_flow_sync_domain_t sync_domain;
1228 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1230 struct flow_grp_info {
1231 uint64_t external:1;
1232 uint64_t transfer:1;
1233 uint64_t fdb_def_rule:1;
1234 /* force standard group translation */
1235 uint64_t std_tbl_fix:1;
1236 uint64_t skip_scale:2;
1240 tunnel_use_standard_attr_group_translate
1241 (struct rte_eth_dev *dev,
1242 const struct mlx5_flow_tunnel *tunnel,
1243 const struct rte_flow_attr *attr,
1244 const struct rte_flow_item items[],
1245 const struct rte_flow_action actions[])
1249 if (!is_tunnel_offload_active(dev))
1250 /* no tunnel offload API */
1254 * OvS will use jump to group 0 in tunnel steer rule.
1255 * If tunnel steer rule starts from group 0 (attr.group == 0)
1256 * that 0 group must be translated with standard method.
1257 * attr.group == 0 in tunnel match rule translated with tunnel
1260 verdict = !attr->group &&
1261 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1264 * non-tunnel group translation uses standard method for
1265 * root group only: attr.group == 0
1267 verdict = !attr->group;
1274 * Get DV flow aso meter by index.
1277 * Pointer to the Ethernet device structure.
1279 * mlx5 flow aso meter index in the container.
1281 * mlx5 flow aso meter pool in the container,
1284 * Pointer to the aso meter, NULL otherwise.
1286 static inline struct mlx5_aso_mtr *
1287 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1289 struct mlx5_aso_mtr_pool *pool;
1290 struct mlx5_aso_mtr_pools_mng *pools_mng =
1291 &priv->sh->mtrmng->pools_mng;
1293 /* Decrease to original index. */
1295 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1296 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1297 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1300 static __rte_always_inline const struct rte_flow_item *
1301 mlx5_find_end_item(const struct rte_flow_item *item)
1303 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1307 static __rte_always_inline bool
1308 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1310 struct rte_flow_item_integrity test = *item;
1313 test.ipv4_csum_ok = 0;
1314 test.l4_csum_ok = 0;
1315 return (test.value == 0);
1318 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1319 const struct mlx5_flow_tunnel *tunnel,
1320 uint32_t group, uint32_t *table,
1321 const struct flow_grp_info *flags,
1322 struct rte_flow_error *error);
1323 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1324 int tunnel, uint64_t layer_types,
1325 uint64_t hash_fields);
1326 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1327 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1328 uint32_t subpriority);
1329 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1330 const struct rte_flow_attr *attr);
1331 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1332 const struct rte_flow_attr *attr,
1333 uint32_t subpriority);
1334 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1335 enum mlx5_feature_name feature,
1337 struct rte_flow_error *error);
1338 const struct rte_flow_action *mlx5_flow_find_action
1339 (const struct rte_flow_action *actions,
1340 enum rte_flow_action_type action);
1341 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1342 const struct rte_flow_action *action,
1343 struct rte_flow_error *error);
1344 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1345 const struct rte_flow_attr *attr,
1346 struct rte_flow_error *error);
1347 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1348 const struct rte_flow_attr *attr,
1349 struct rte_flow_error *error);
1350 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1351 const struct rte_flow_attr *attr,
1352 struct rte_flow_error *error);
1353 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1354 uint64_t action_flags,
1355 const struct rte_flow_attr *attr,
1356 struct rte_flow_error *error);
1357 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1358 uint64_t action_flags,
1359 struct rte_eth_dev *dev,
1360 const struct rte_flow_attr *attr,
1361 struct rte_flow_error *error);
1362 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1363 uint64_t action_flags,
1364 struct rte_eth_dev *dev,
1365 const struct rte_flow_attr *attr,
1366 uint64_t item_flags,
1367 struct rte_flow_error *error);
1368 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1369 const struct rte_flow_attr *attr,
1370 struct rte_flow_error *error);
1371 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1372 const struct rte_flow_attr *attributes,
1373 struct rte_flow_error *error);
1374 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1375 const uint8_t *mask,
1376 const uint8_t *nic_mask,
1378 bool range_accepted,
1379 struct rte_flow_error *error);
1380 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1381 uint64_t item_flags, bool ext_vlan_sup,
1382 struct rte_flow_error *error);
1383 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1384 uint64_t item_flags,
1385 uint8_t target_protocol,
1386 struct rte_flow_error *error);
1387 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1388 uint64_t item_flags,
1389 const struct rte_flow_item *gre_item,
1390 struct rte_flow_error *error);
1391 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1392 uint64_t item_flags,
1394 uint16_t ether_type,
1395 const struct rte_flow_item_ipv4 *acc_mask,
1396 bool range_accepted,
1397 struct rte_flow_error *error);
1398 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1399 uint64_t item_flags,
1401 uint16_t ether_type,
1402 const struct rte_flow_item_ipv6 *acc_mask,
1403 struct rte_flow_error *error);
1404 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1405 const struct rte_flow_item *item,
1406 uint64_t item_flags,
1407 uint64_t prev_layer,
1408 struct rte_flow_error *error);
1409 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1410 uint64_t item_flags,
1411 uint8_t target_protocol,
1412 const struct rte_flow_item_tcp *flow_mask,
1413 struct rte_flow_error *error);
1414 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1415 uint64_t item_flags,
1416 uint8_t target_protocol,
1417 struct rte_flow_error *error);
1418 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1419 uint64_t item_flags,
1420 struct rte_eth_dev *dev,
1421 struct rte_flow_error *error);
1422 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1423 uint64_t item_flags,
1424 struct rte_flow_error *error);
1425 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1426 uint64_t item_flags,
1427 struct rte_eth_dev *dev,
1428 struct rte_flow_error *error);
1429 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1430 uint64_t item_flags,
1431 uint8_t target_protocol,
1432 struct rte_flow_error *error);
1433 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1434 uint64_t item_flags,
1435 uint8_t target_protocol,
1436 struct rte_flow_error *error);
1437 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1438 uint64_t item_flags,
1439 uint8_t target_protocol,
1440 struct rte_flow_error *error);
1441 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1442 uint64_t item_flags,
1443 struct rte_eth_dev *dev,
1444 struct rte_flow_error *error);
1445 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1447 const struct rte_flow_item *geneve_item,
1448 struct rte_eth_dev *dev,
1449 struct rte_flow_error *error);
1450 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1451 uint64_t item_flags,
1453 uint16_t ether_type,
1454 const struct rte_flow_item_ecpri *acc_mask,
1455 struct rte_flow_error *error);
1456 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1457 struct mlx5_flow_meter_info *fm,
1459 uint8_t domain_bitmap);
1460 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1461 struct mlx5_flow_meter_info *fm);
1462 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1463 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1464 (struct rte_eth_dev *dev,
1465 struct mlx5_flow_meter_policy *mtr_policy,
1466 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1467 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1468 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1469 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1470 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1472 /* Hash list callbacks for flow tables: */
1473 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1474 uint64_t key, void *entry_ctx);
1475 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1476 struct mlx5_hlist_entry *entry, uint64_t key,
1478 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1479 struct mlx5_hlist_entry *entry);
1480 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1481 uint32_t table_level, uint8_t egress, uint8_t transfer,
1482 bool external, const struct mlx5_flow_tunnel *tunnel,
1483 uint32_t group_id, uint8_t dummy,
1484 uint32_t table_id, struct rte_flow_error *error);
1486 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1487 uint64_t key, void *cb_ctx);
1488 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1489 struct mlx5_hlist_entry *entry, uint64_t key,
1491 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1492 struct mlx5_hlist_entry *entry);
1494 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1495 struct mlx5_hlist_entry *entry,
1496 uint64_t key, void *cb_ctx);
1497 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1498 uint64_t key, void *ctx);
1499 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1500 struct mlx5_hlist_entry *entry);
1502 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1503 uint64_t key, void *ctx);
1504 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1505 struct mlx5_hlist_entry *entry, uint64_t key,
1507 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1508 struct mlx5_hlist_entry *entry);
1510 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1511 struct mlx5_hlist_entry *entry,
1512 uint64_t key, void *cb_ctx);
1513 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1514 uint64_t key, void *cb_ctx);
1515 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1516 struct mlx5_hlist_entry *entry);
1518 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1519 struct mlx5_cache_entry *entry, void *ctx);
1520 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1521 struct mlx5_cache_entry *entry, void *ctx);
1522 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1523 struct mlx5_cache_entry *entry);
1525 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1526 struct mlx5_cache_entry *entry, void *cb_ctx);
1527 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1528 struct mlx5_cache_entry *entry, void *cb_ctx);
1529 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1530 struct mlx5_cache_entry *entry);
1532 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1533 struct mlx5_cache_entry *entry, void *cb_ctx);
1534 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1535 (struct mlx5_cache_list *list,
1536 struct mlx5_cache_entry *entry, void *cb_ctx);
1537 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1538 struct mlx5_cache_entry *entry);
1540 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1541 struct mlx5_cache_entry *entry, void *cb_ctx);
1542 struct mlx5_cache_entry *flow_dv_sample_create_cb
1543 (struct mlx5_cache_list *list,
1544 struct mlx5_cache_entry *entry, void *cb_ctx);
1545 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1546 struct mlx5_cache_entry *entry);
1548 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1549 struct mlx5_cache_entry *entry, void *cb_ctx);
1550 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1551 (struct mlx5_cache_list *list,
1552 struct mlx5_cache_entry *entry, void *cb_ctx);
1553 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1554 struct mlx5_cache_entry *entry);
1555 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1557 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1558 const struct rte_flow_item *item,
1559 struct rte_flow_error *error);
1560 void flow_release_workspace(void *data);
1561 int mlx5_flow_os_init_workspace_once(void);
1562 void *mlx5_flow_os_get_specific_workspace(void);
1563 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1564 void mlx5_flow_os_release_workspace(void);
1565 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1566 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1567 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1568 const struct rte_flow_action *actions[RTE_COLORS],
1569 struct rte_flow_attr *attr,
1571 uint8_t *domain_bitmap,
1572 bool *is_def_policy,
1573 struct rte_mtr_error *error);
1574 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1575 struct mlx5_flow_meter_policy *mtr_policy);
1576 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1577 struct mlx5_flow_meter_policy *mtr_policy,
1578 const struct rte_flow_action *actions[RTE_COLORS],
1579 struct rte_mtr_error *error);
1580 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1581 struct mlx5_flow_meter_policy *mtr_policy);
1582 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1583 struct mlx5_flow_meter_policy *mtr_policy);
1584 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1585 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1586 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1587 struct mlx5_flow_handle *dev_handle);
1588 #endif /* RTE_PMD_MLX5_FLOW_H_ */