1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
27 /* Pattern outer Layer bits. */
28 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
29 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
30 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
31 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
32 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
33 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
35 /* Pattern inner Layer bits. */
36 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
37 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
38 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
39 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
40 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
41 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
43 /* Pattern tunnel Layer bits. */
44 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
45 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
46 #define MLX5_FLOW_LAYER_GRE (1u << 14)
47 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
49 /* General pattern items bits. */
50 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
51 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
53 /* Pattern MISC bits. */
54 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
55 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
58 #define MLX5_FLOW_LAYER_OUTER_L3 \
59 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
60 #define MLX5_FLOW_LAYER_OUTER_L4 \
61 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
62 #define MLX5_FLOW_LAYER_OUTER \
63 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
64 MLX5_FLOW_LAYER_OUTER_L4)
67 #define MLX5_FLOW_LAYER_TUNNEL \
68 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
69 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS)
72 #define MLX5_FLOW_LAYER_INNER_L3 \
73 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
74 #define MLX5_FLOW_LAYER_INNER_L4 \
75 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
76 #define MLX5_FLOW_LAYER_INNER \
77 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
78 MLX5_FLOW_LAYER_INNER_L4)
81 #define MLX5_FLOW_LAYER_L2 \
82 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
83 #define MLX5_FLOW_LAYER_L3_IPV4 \
84 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
85 #define MLX5_FLOW_LAYER_L3_IPV6 \
86 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
87 #define MLX5_FLOW_LAYER_L3 \
88 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
89 #define MLX5_FLOW_LAYER_L4 \
90 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
93 #define MLX5_FLOW_ACTION_DROP (1u << 0)
94 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
95 #define MLX5_FLOW_ACTION_RSS (1u << 2)
96 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
97 #define MLX5_FLOW_ACTION_MARK (1u << 4)
98 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
99 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
100 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
101 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
102 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
103 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
104 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
105 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
106 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
107 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
108 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
109 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
110 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
111 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
112 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
113 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
114 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
115 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
116 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
117 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
118 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
119 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
120 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
121 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
122 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
123 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
124 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
126 #define MLX5_FLOW_FATE_ACTIONS \
127 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
128 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
130 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
131 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
132 MLX5_FLOW_ACTION_JUMP)
134 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
135 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
136 MLX5_FLOW_ACTION_RAW_ENCAP)
138 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
139 MLX5_FLOW_ACTION_NVGRE_DECAP | \
140 MLX5_FLOW_ACTION_RAW_DECAP)
142 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
143 MLX5_FLOW_ACTION_SET_IPV4_DST | \
144 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
145 MLX5_FLOW_ACTION_SET_IPV6_DST | \
146 MLX5_FLOW_ACTION_SET_TP_SRC | \
147 MLX5_FLOW_ACTION_SET_TP_DST | \
148 MLX5_FLOW_ACTION_SET_TTL | \
149 MLX5_FLOW_ACTION_DEC_TTL | \
150 MLX5_FLOW_ACTION_SET_MAC_SRC | \
151 MLX5_FLOW_ACTION_SET_MAC_DST | \
152 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
153 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
154 MLX5_FLOW_ACTION_INC_TCP_ACK | \
155 MLX5_FLOW_ACTION_DEC_TCP_ACK)
158 #define IPPROTO_MPLS 137
161 /* UDP port number for MPLS */
162 #define MLX5_UDP_PORT_MPLS 6635
164 /* UDP port numbers for VxLAN. */
165 #define MLX5_UDP_PORT_VXLAN 4789
166 #define MLX5_UDP_PORT_VXLAN_GPE 4790
168 /* Priority reserved for default flows. */
169 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
172 * Number of sub priorities.
173 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
174 * matching on the NIC (firmware dependent) L4 most have the higher priority
175 * followed by L3 and ending with L2.
177 #define MLX5_PRIORITY_MAP_L2 2
178 #define MLX5_PRIORITY_MAP_L3 1
179 #define MLX5_PRIORITY_MAP_L4 0
180 #define MLX5_PRIORITY_MAP_MAX 3
182 /* Valid layer type for IPV4 RSS. */
183 #define MLX5_IPV4_LAYER_TYPES \
184 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
185 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
186 ETH_RSS_NONFRAG_IPV4_OTHER)
188 /* IBV hash source bits for IPV4. */
189 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
191 /* Valid layer type for IPV6 RSS. */
192 #define MLX5_IPV6_LAYER_TYPES \
193 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
194 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
195 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
197 /* IBV hash source bits for IPV6. */
198 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
200 enum mlx5_flow_drv_type {
203 MLX5_FLOW_TYPE_VERBS,
207 /* Matcher PRM representation */
208 struct mlx5_flow_dv_match_params {
210 /**< Size of match value. Do NOT split size and key! */
211 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
212 /**< Matcher value. This value is used as the mask or as a key. */
215 /* Matcher structure. */
216 struct mlx5_flow_dv_matcher {
217 LIST_ENTRY(mlx5_flow_dv_matcher) next;
218 /* Pointer to the next element. */
219 rte_atomic32_t refcnt; /**< Reference counter. */
220 void *matcher_object; /**< Pointer to DV matcher */
221 uint16_t crc; /**< CRC of key. */
222 uint16_t priority; /**< Priority of matcher. */
223 uint8_t egress; /**< Egress matcher. */
224 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
225 uint32_t group; /**< The matcher group. */
226 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
229 #define MLX5_ENCAP_MAX_LEN 132
231 /* Encap/decap resource structure. */
232 struct mlx5_flow_dv_encap_decap_resource {
233 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
234 /* Pointer to next element. */
235 rte_atomic32_t refcnt; /**< Reference counter. */
237 /**< Verbs encap/decap action object. */
238 uint8_t buf[MLX5_ENCAP_MAX_LEN];
240 uint8_t reformat_type;
242 uint64_t flags; /**< Flags for RDMA API. */
245 /* Tag resource structure. */
246 struct mlx5_flow_dv_tag_resource {
247 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
248 /* Pointer to next element. */
249 rte_atomic32_t refcnt; /**< Reference counter. */
251 /**< Verbs tag action object. */
252 uint32_t tag; /**< the tag value. */
255 /* Number of modification commands. */
256 #define MLX5_MODIFY_NUM 8
258 /* Modify resource structure */
259 struct mlx5_flow_dv_modify_hdr_resource {
260 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
261 /* Pointer to next element. */
262 rte_atomic32_t refcnt; /**< Reference counter. */
263 struct ibv_flow_action *verbs_action;
264 /**< Verbs modify header action object. */
265 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
266 uint32_t actions_num; /**< Number of modification actions. */
267 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
268 /**< Modification actions. */
269 uint64_t flags; /**< Flags for RDMA API. */
272 /* Jump action resource structure. */
273 struct mlx5_flow_dv_jump_tbl_resource {
274 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
275 /* Pointer to next element. */
276 rte_atomic32_t refcnt; /**< Reference counter. */
277 void *action; /**< Pointer to the rdma core action. */
278 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
279 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
282 /* Port ID resource structure. */
283 struct mlx5_flow_dv_port_id_action_resource {
284 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
285 /* Pointer to next element. */
286 rte_atomic32_t refcnt; /**< Reference counter. */
288 /**< Verbs tag action object. */
289 uint32_t port_id; /**< Port ID value. */
293 * Max number of actions per DV flow.
294 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
295 * In rdma-core file providers/mlx5/verbs.c
297 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
299 /* DV flows structure. */
300 struct mlx5_flow_dv {
301 uint64_t hash_fields; /**< Fields that participate in the hash. */
302 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
304 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
305 struct mlx5_flow_dv_match_params value;
306 /**< Holds the value that the packet is compared to. */
307 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
308 /**< Pointer to encap/decap resource in cache. */
309 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
310 /**< Pointer to modify header resource in cache. */
311 struct ibv_flow *flow; /**< Installed flow. */
312 struct mlx5_flow_dv_jump_tbl_resource *jump;
313 /**< Pointer to the jump action resource. */
314 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
315 /**< Pointer to port ID action resource. */
316 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
317 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
320 int actions_n; /**< number of actions. */
323 /* Verbs specification header. */
324 struct ibv_spec_header {
325 enum ibv_flow_spec_type type;
329 /** Handles information leading to a drop fate. */
330 struct mlx5_flow_verbs {
331 LIST_ENTRY(mlx5_flow_verbs) next;
332 unsigned int size; /**< Size of the attribute. */
334 struct ibv_flow_attr *attr;
335 /**< Pointer to the Specification buffer. */
336 uint8_t *specs; /**< Pointer to the specifications. */
338 struct ibv_flow *flow; /**< Verbs flow pointer. */
339 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
340 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
343 /** Device flow structure. */
345 LIST_ENTRY(mlx5_flow) next;
346 struct rte_flow *flow; /**< Pointer to the main flow. */
348 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
350 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
351 struct mlx5_flow_dv dv;
353 struct mlx5_flow_verbs verbs;
357 /* Counters information. */
358 struct mlx5_flow_counter {
359 LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */
360 uint32_t shared:1; /**< Share counter ID with other flow rules. */
361 uint32_t ref_cnt:31; /**< Reference counter. */
362 uint32_t id; /**< Counter ID. */
363 union { /**< Holds the counters for the rule. */
364 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
365 struct ibv_counter_set *cs;
366 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
367 struct ibv_counters *cs;
369 struct mlx5_devx_counter_set *dcs;
371 uint64_t hits; /**< Number of packets matched by the rule. */
372 uint64_t bytes; /**< Number of bytes matched by the rule. */
373 void *action; /**< Pointer to the dv action. */
376 /* Flow structure. */
378 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
379 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
380 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
381 struct mlx5_flow_dv_tag_resource *tag_resource;
382 /**< pointer to the tag action. */
383 struct rte_flow_action_rss rss;/**< RSS context. */
384 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
385 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
386 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
387 /**< Device flows that are part of the flow. */
389 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
390 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
391 uint8_t ingress; /**< 1 if the flow is ingress. */
392 uint32_t group; /**< The group index. */
393 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
396 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
397 const struct rte_flow_attr *attr,
398 const struct rte_flow_item items[],
399 const struct rte_flow_action actions[],
400 struct rte_flow_error *error);
401 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
402 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
403 const struct rte_flow_action actions[], struct rte_flow_error *error);
404 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
405 struct mlx5_flow *dev_flow,
406 const struct rte_flow_attr *attr,
407 const struct rte_flow_item items[],
408 const struct rte_flow_action actions[],
409 struct rte_flow_error *error);
410 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
411 struct rte_flow_error *error);
412 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
413 struct rte_flow *flow);
414 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
415 struct rte_flow *flow);
416 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
417 struct rte_flow *flow,
418 const struct rte_flow_action *actions,
420 struct rte_flow_error *error);
421 struct mlx5_flow_driver_ops {
422 mlx5_flow_validate_t validate;
423 mlx5_flow_prepare_t prepare;
424 mlx5_flow_translate_t translate;
425 mlx5_flow_apply_t apply;
426 mlx5_flow_remove_t remove;
427 mlx5_flow_destroy_t destroy;
428 mlx5_flow_query_t query;
433 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
434 uint64_t layer_types,
435 uint64_t hash_fields);
436 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
437 uint32_t subpriority);
438 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
439 const struct rte_flow_attr *attr,
440 struct rte_flow_error *error);
441 int mlx5_flow_validate_action_drop(uint64_t action_flags,
442 const struct rte_flow_attr *attr,
443 struct rte_flow_error *error);
444 int mlx5_flow_validate_action_flag(uint64_t action_flags,
445 const struct rte_flow_attr *attr,
446 struct rte_flow_error *error);
447 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
448 uint64_t action_flags,
449 const struct rte_flow_attr *attr,
450 struct rte_flow_error *error);
451 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
452 uint64_t action_flags,
453 struct rte_eth_dev *dev,
454 const struct rte_flow_attr *attr,
455 struct rte_flow_error *error);
456 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
457 uint64_t action_flags,
458 struct rte_eth_dev *dev,
459 const struct rte_flow_attr *attr,
461 struct rte_flow_error *error);
462 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
463 const struct rte_flow_attr *attributes,
464 struct rte_flow_error *error);
465 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
467 const uint8_t *nic_mask,
469 struct rte_flow_error *error);
470 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
472 struct rte_flow_error *error);
473 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
475 uint8_t target_protocol,
476 struct rte_flow_error *error);
477 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
479 const struct rte_flow_item_ipv4 *acc_mask,
480 struct rte_flow_error *error);
481 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
483 const struct rte_flow_item_ipv6 *acc_mask,
484 struct rte_flow_error *error);
485 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
486 const struct rte_flow_item *item,
489 struct rte_flow_error *error);
490 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
492 uint8_t target_protocol,
493 const struct rte_flow_item_tcp *flow_mask,
494 struct rte_flow_error *error);
495 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
497 uint8_t target_protocol,
498 struct rte_flow_error *error);
499 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
501 struct rte_flow_error *error);
502 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
504 struct rte_flow_error *error);
505 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
507 struct rte_eth_dev *dev,
508 struct rte_flow_error *error);
509 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
511 uint8_t target_protocol,
512 struct rte_flow_error *error);
513 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
515 uint8_t target_protocol,
516 struct rte_flow_error *error);
518 #endif /* RTE_PMD_MLX5_FLOW_H_ */