1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* E-Switch Manager port, used for rte_flow_item_port_id. */
22 #define MLX5_PORT_ESW_MGR UINT32_MAX
24 /* Private rte flow items. */
25 enum mlx5_rte_flow_item_type {
26 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
28 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
29 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
30 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
33 /* Private (internal) rte flow actions. */
34 enum mlx5_rte_flow_action_type {
35 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
36 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
37 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
38 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
39 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
41 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
43 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
46 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
49 MLX5_INDIRECT_ACTION_TYPE_RSS,
50 MLX5_INDIRECT_ACTION_TYPE_AGE,
51 MLX5_INDIRECT_ACTION_TYPE_COUNT,
52 MLX5_INDIRECT_ACTION_TYPE_CT,
55 /* Now, the maximal ports will be supported is 256, action number is 4M. */
56 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100
58 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22
59 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)
61 /* 30-31: type, 22-29: owner port, 0-21: index. */
62 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \
63 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \
64 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \
65 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index))
67 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \
68 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \
69 MLX5_INDIRECT_ACT_CT_OWNER_MASK)
71 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \
72 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))
74 /* Matches on selected register. */
75 struct mlx5_rte_flow_item_tag {
80 /* Modify selected register. */
81 struct mlx5_rte_flow_action_set_tag {
88 struct mlx5_flow_action_copy_mreg {
93 /* Matches on source queue. */
94 struct mlx5_rte_flow_item_tx_queue {
98 /* Feature name to allocate metadata register. */
99 enum mlx5_feature_name {
114 /* Default queue number. */
115 #define MLX5_RSSQ_DEFAULT_NUM 16
117 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
118 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
119 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
120 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
121 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
122 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
124 /* Pattern inner Layer bits. */
125 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
126 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
127 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
128 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
129 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
130 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
132 /* Pattern tunnel Layer bits. */
133 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
134 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
135 #define MLX5_FLOW_LAYER_GRE (1u << 14)
136 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
137 /* List of tunnel Layer bits continued below. */
139 /* General pattern items bits. */
140 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
141 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
142 #define MLX5_FLOW_ITEM_TAG (1u << 18)
143 #define MLX5_FLOW_ITEM_MARK (1u << 19)
145 /* Pattern MISC bits. */
146 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
147 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
148 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
150 /* Pattern tunnel Layer bits (continued). */
151 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
152 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
153 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
154 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
157 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
159 /* Pattern tunnel Layer bits (continued). */
160 #define MLX5_FLOW_LAYER_GTP (1u << 28)
162 /* Pattern eCPRI Layer bit. */
163 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
165 /* IPv6 Fragment Extension Header bit. */
166 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
167 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
169 /* Pattern tunnel Layer bits (continued). */
170 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
171 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
173 /* INTEGRITY item bits */
174 #define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34)
175 #define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35)
176 #define MLX5_FLOW_ITEM_INTEGRITY \
177 (MLX5_FLOW_ITEM_OUTER_INTEGRITY | MLX5_FLOW_ITEM_INNER_INTEGRITY)
179 /* Conntrack item. */
180 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36)
183 #define MLX5_FLOW_ITEM_OUTER_FLEX (UINT64_C(1) << 36)
184 #define MLX5_FLOW_ITEM_INNER_FLEX (UINT64_C(1) << 37)
185 #define MLX5_FLOW_ITEM_FLEX_TUNNEL (UINT64_C(1) << 38)
188 #define MLX5_FLOW_LAYER_OUTER_L3 \
189 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
190 #define MLX5_FLOW_LAYER_OUTER_L4 \
191 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
192 #define MLX5_FLOW_LAYER_OUTER \
193 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
194 MLX5_FLOW_LAYER_OUTER_L4)
197 #define MLX5_FLOW_LAYER_TUNNEL \
198 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
199 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
200 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
201 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP | \
202 MLX5_FLOW_ITEM_FLEX_TUNNEL)
205 #define MLX5_FLOW_LAYER_INNER_L3 \
206 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
207 #define MLX5_FLOW_LAYER_INNER_L4 \
208 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
209 #define MLX5_FLOW_LAYER_INNER \
210 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
211 MLX5_FLOW_LAYER_INNER_L4)
214 #define MLX5_FLOW_LAYER_L2 \
215 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
216 #define MLX5_FLOW_LAYER_L3_IPV4 \
217 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
218 #define MLX5_FLOW_LAYER_L3_IPV6 \
219 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
220 #define MLX5_FLOW_LAYER_L3 \
221 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
222 #define MLX5_FLOW_LAYER_L4 \
223 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
226 #define MLX5_FLOW_ACTION_DROP (1u << 0)
227 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
228 #define MLX5_FLOW_ACTION_RSS (1u << 2)
229 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
230 #define MLX5_FLOW_ACTION_MARK (1u << 4)
231 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
232 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
233 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
234 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
235 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
236 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
237 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
238 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
239 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
240 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
241 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
242 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
243 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
244 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
245 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
246 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
247 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
248 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
249 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
250 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
251 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
252 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
253 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
254 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
255 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
256 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
257 #define MLX5_FLOW_ACTION_METER (1ull << 31)
258 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
259 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
260 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
261 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
262 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
263 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
264 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
265 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
266 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
267 #define MLX5_FLOW_ACTION_CT (1ull << 41)
269 #define MLX5_FLOW_FATE_ACTIONS \
270 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
271 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
272 MLX5_FLOW_ACTION_DEFAULT_MISS | \
273 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
275 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
276 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
277 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
279 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
280 MLX5_FLOW_ACTION_SET_IPV4_DST | \
281 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
282 MLX5_FLOW_ACTION_SET_IPV6_DST | \
283 MLX5_FLOW_ACTION_SET_TP_SRC | \
284 MLX5_FLOW_ACTION_SET_TP_DST | \
285 MLX5_FLOW_ACTION_SET_TTL | \
286 MLX5_FLOW_ACTION_DEC_TTL | \
287 MLX5_FLOW_ACTION_SET_MAC_SRC | \
288 MLX5_FLOW_ACTION_SET_MAC_DST | \
289 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
290 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
291 MLX5_FLOW_ACTION_INC_TCP_ACK | \
292 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
293 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
294 MLX5_FLOW_ACTION_SET_TAG | \
295 MLX5_FLOW_ACTION_MARK_EXT | \
296 MLX5_FLOW_ACTION_SET_META | \
297 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
298 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
299 MLX5_FLOW_ACTION_MODIFY_FIELD)
301 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
302 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
304 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
307 #define IPPROTO_MPLS 137
310 /* UDP port number for MPLS */
311 #define MLX5_UDP_PORT_MPLS 6635
313 /* UDP port numbers for VxLAN. */
314 #define MLX5_UDP_PORT_VXLAN 4789
315 #define MLX5_UDP_PORT_VXLAN_GPE 4790
317 /* UDP port numbers for GENEVE. */
318 #define MLX5_UDP_PORT_GENEVE 6081
320 /* Lowest priority indicator. */
321 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
324 * Max priority for ingress\egress flow groups
325 * greater than 0 and for any transfer flow group.
326 * From user configation: 0 - 21843.
328 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
331 * Number of sub priorities.
332 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
333 * matching on the NIC (firmware dependent) L4 most have the higher priority
334 * followed by L3 and ending with L2.
336 #define MLX5_PRIORITY_MAP_L2 2
337 #define MLX5_PRIORITY_MAP_L3 1
338 #define MLX5_PRIORITY_MAP_L4 0
339 #define MLX5_PRIORITY_MAP_MAX 3
341 /* Valid layer type for IPV4 RSS. */
342 #define MLX5_IPV4_LAYER_TYPES \
343 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \
344 RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
345 RTE_ETH_RSS_NONFRAG_IPV4_OTHER)
347 /* IBV hash source bits for IPV4. */
348 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
350 /* Valid layer type for IPV6 RSS. */
351 #define MLX5_IPV6_LAYER_TYPES \
352 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
353 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | \
354 RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER)
356 /* IBV hash source bits for IPV6. */
357 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
359 /* IBV hash bits for L3 SRC. */
360 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
362 /* IBV hash bits for L3 DST. */
363 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
365 /* IBV hash bits for TCP. */
366 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
367 IBV_RX_HASH_DST_PORT_TCP)
369 /* IBV hash bits for UDP. */
370 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
371 IBV_RX_HASH_DST_PORT_UDP)
373 /* IBV hash bits for L4 SRC. */
374 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
375 IBV_RX_HASH_SRC_PORT_UDP)
377 /* IBV hash bits for L4 DST. */
378 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
379 IBV_RX_HASH_DST_PORT_UDP)
381 /* Geneve header first 16Bit */
382 #define MLX5_GENEVE_VER_MASK 0x3
383 #define MLX5_GENEVE_VER_SHIFT 14
384 #define MLX5_GENEVE_VER_VAL(a) \
385 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
386 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
387 #define MLX5_GENEVE_OPTLEN_SHIFT 8
388 #define MLX5_GENEVE_OPTLEN_VAL(a) \
389 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
390 #define MLX5_GENEVE_OAMF_MASK 0x1
391 #define MLX5_GENEVE_OAMF_SHIFT 7
392 #define MLX5_GENEVE_OAMF_VAL(a) \
393 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
394 #define MLX5_GENEVE_CRITO_MASK 0x1
395 #define MLX5_GENEVE_CRITO_SHIFT 6
396 #define MLX5_GENEVE_CRITO_VAL(a) \
397 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
398 #define MLX5_GENEVE_RSVD_MASK 0x3F
399 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
401 * The length of the Geneve options fields, expressed in four byte multiples,
402 * not including the eight byte fixed tunnel.
404 #define MLX5_GENEVE_OPT_LEN_0 14
405 #define MLX5_GENEVE_OPT_LEN_1 63
407 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
408 sizeof(struct rte_ipv4_hdr))
409 /* GTP extension header flag. */
410 #define MLX5_GTP_EXT_HEADER_FLAG 4
412 /* GTP extension header PDU type shift. */
413 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
415 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
416 #define MLX5_IPV4_FRAG_OFFSET_MASK \
417 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
419 /* Specific item's fields can accept a range of values (using spec and last). */
420 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
421 #define MLX5_ITEM_RANGE_ACCEPTED true
423 /* Software header modify action numbers of a flow. */
424 #define MLX5_ACT_NUM_MDF_IPV4 1
425 #define MLX5_ACT_NUM_MDF_IPV6 4
426 #define MLX5_ACT_NUM_MDF_MAC 2
427 #define MLX5_ACT_NUM_MDF_VID 1
428 #define MLX5_ACT_NUM_MDF_PORT 2
429 #define MLX5_ACT_NUM_MDF_TTL 1
430 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
431 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
432 #define MLX5_ACT_NUM_MDF_TCPACK 1
433 #define MLX5_ACT_NUM_SET_REG 1
434 #define MLX5_ACT_NUM_SET_TAG 1
435 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
436 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
437 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
438 #define MLX5_ACT_NUM_SET_DSCP 1
440 /* Maximum number of fields to modify in MODIFY_FIELD */
441 #define MLX5_ACT_MAX_MOD_FIELDS 5
443 /* Syndrome bits definition for connection tracking. */
444 #define MLX5_CT_SYNDROME_VALID (0x0 << 6)
445 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6)
446 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6)
447 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1)
448 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0)
450 enum mlx5_flow_drv_type {
453 MLX5_FLOW_TYPE_VERBS,
457 /* Fate action type. */
458 enum mlx5_flow_fate_type {
459 MLX5_FLOW_FATE_NONE, /* Egress flow. */
460 MLX5_FLOW_FATE_QUEUE,
462 MLX5_FLOW_FATE_PORT_ID,
464 MLX5_FLOW_FATE_DEFAULT_MISS,
465 MLX5_FLOW_FATE_SHARED_RSS,
470 /* Matcher PRM representation */
471 struct mlx5_flow_dv_match_params {
473 /**< Size of match value. Do NOT split size and key! */
474 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
475 /**< Matcher value. This value is used as the mask or as a key. */
478 /* Matcher structure. */
479 struct mlx5_flow_dv_matcher {
480 struct mlx5_list_entry entry; /**< Pointer to the next element. */
481 struct mlx5_flow_tbl_resource *tbl;
482 /**< Pointer to the table(group) the matcher associated with. */
483 void *matcher_object; /**< Pointer to DV matcher */
484 uint16_t crc; /**< CRC of key. */
485 uint16_t priority; /**< Priority of matcher. */
486 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
489 #define MLX5_ENCAP_MAX_LEN 132
491 /* Encap/decap resource structure. */
492 struct mlx5_flow_dv_encap_decap_resource {
493 struct mlx5_list_entry entry;
494 /* Pointer to next element. */
495 uint32_t refcnt; /**< Reference counter. */
497 /**< Encap/decap action object. */
498 uint8_t buf[MLX5_ENCAP_MAX_LEN];
500 uint8_t reformat_type;
502 uint64_t flags; /**< Flags for RDMA API. */
503 uint32_t idx; /**< Index for the index memory pool. */
506 /* Tag resource structure. */
507 struct mlx5_flow_dv_tag_resource {
508 struct mlx5_list_entry entry;
509 /**< hash list entry for tag resource, tag value as the key. */
511 /**< Tag action object. */
512 uint32_t refcnt; /**< Reference counter. */
513 uint32_t idx; /**< Index for the index memory pool. */
514 uint32_t tag_id; /**< Tag ID. */
517 /* Modify resource structure */
518 struct mlx5_flow_dv_modify_hdr_resource {
519 struct mlx5_list_entry entry;
520 void *action; /**< Modify header action object. */
522 /* Key area for hash list matching: */
523 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
524 uint8_t actions_num; /**< Number of modification actions. */
525 bool root; /**< Whether action is in root table. */
526 struct mlx5_modification_cmd actions[];
527 /**< Modification actions. */
530 /* Modify resource key of the hash organization. */
531 union mlx5_flow_modify_hdr_key {
533 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
534 uint32_t actions_num:5; /**< Number of modification actions. */
535 uint32_t group:19; /**< Flow group id. */
536 uint32_t cksum; /**< Actions check sum. */
538 uint64_t v64; /**< full 64bits value of key */
541 /* Jump action resource structure. */
542 struct mlx5_flow_dv_jump_tbl_resource {
543 void *action; /**< Pointer to the rdma core action. */
546 /* Port ID resource structure. */
547 struct mlx5_flow_dv_port_id_action_resource {
548 struct mlx5_list_entry entry;
549 void *action; /**< Action object. */
550 uint32_t port_id; /**< Port ID value. */
551 uint32_t idx; /**< Indexed pool memory index. */
554 /* Push VLAN action resource structure */
555 struct mlx5_flow_dv_push_vlan_action_resource {
556 struct mlx5_list_entry entry; /* Cache entry. */
557 void *action; /**< Action object. */
558 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
559 rte_be32_t vlan_tag; /**< VLAN tag value. */
560 uint32_t idx; /**< Indexed pool memory index. */
563 /* Metadata register copy table entry. */
564 struct mlx5_flow_mreg_copy_resource {
566 * Hash list entry for copy table.
567 * - Key is 32/64-bit MARK action ID.
568 * - MUST be the first entry.
570 struct mlx5_list_entry hlist_ent;
571 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
572 /* List entry for device flows. */
574 uint32_t rix_flow; /* Built flow for copy. */
578 /* Table tunnel parameter. */
579 struct mlx5_flow_tbl_tunnel_prm {
580 const struct mlx5_flow_tunnel *tunnel;
585 /* Table data structure of the hash organization. */
586 struct mlx5_flow_tbl_data_entry {
587 struct mlx5_list_entry entry;
588 /**< hash list entry, 64-bits key inside. */
589 struct mlx5_flow_tbl_resource tbl;
590 /**< flow table resource. */
591 struct mlx5_list *matchers;
592 /**< matchers' header associated with the flow table. */
593 struct mlx5_flow_dv_jump_tbl_resource jump;
594 /**< jump resource, at most one for each table created. */
595 uint32_t idx; /**< index for the indexed mempool. */
596 /**< tunnel offload */
597 const struct mlx5_flow_tunnel *tunnel;
600 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
601 uint32_t is_egress:1; /**< Egress table. */
602 uint32_t is_transfer:1; /**< Transfer table. */
603 uint32_t dummy:1; /**< DR table. */
604 uint32_t id:22; /**< Table ID. */
605 uint32_t reserve:5; /**< Reserved to future using. */
606 uint32_t level; /**< Table level. */
609 /* Sub rdma-core actions list. */
610 struct mlx5_flow_sub_actions_list {
611 uint32_t actions_num; /**< Number of sample actions. */
612 uint64_t action_flags;
613 void *dr_queue_action;
616 void *dr_port_id_action;
617 void *dr_encap_action;
618 void *dr_jump_action;
621 /* Sample sub-actions resource list. */
622 struct mlx5_flow_sub_actions_idx {
623 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
624 uint32_t rix_tag; /**< Index to the tag action. */
625 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
626 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
627 uint32_t rix_jump; /**< Index to the jump action resource. */
630 /* Sample action resource structure. */
631 struct mlx5_flow_dv_sample_resource {
632 struct mlx5_list_entry entry; /**< Cache entry. */
634 void *verbs_action; /**< Verbs sample action object. */
635 void **sub_actions; /**< Sample sub-action array. */
637 struct rte_eth_dev *dev; /**< Device registers the action. */
638 uint32_t idx; /** Sample object index. */
639 uint8_t ft_type; /** Flow Table Type */
640 uint32_t ft_id; /** Flow Table Level */
641 uint32_t ratio; /** Sample Ratio */
642 uint64_t set_action; /** Restore reg_c0 value */
643 void *normal_path_tbl; /** Flow Table pointer */
644 struct mlx5_flow_sub_actions_idx sample_idx;
645 /**< Action index resources. */
646 struct mlx5_flow_sub_actions_list sample_act;
647 /**< Action resources. */
650 #define MLX5_MAX_DEST_NUM 2
652 /* Destination array action resource structure. */
653 struct mlx5_flow_dv_dest_array_resource {
654 struct mlx5_list_entry entry; /**< Cache entry. */
655 uint32_t idx; /** Destination array action object index. */
656 uint8_t ft_type; /** Flow Table Type */
657 uint8_t num_of_dest; /**< Number of destination actions. */
658 struct rte_eth_dev *dev; /**< Device registers the action. */
659 void *action; /**< Pointer to the rdma core action. */
660 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
661 /**< Action index resources. */
662 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
663 /**< Action resources. */
666 /* PMD flow priority for tunnel */
667 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
668 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
671 /** Device flow handle structure for DV mode only. */
672 struct mlx5_flow_handle_dv {
674 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
675 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
676 /**< Pointer to modify header resource in cache. */
677 uint32_t rix_encap_decap;
678 /**< Index to encap/decap resource in cache. */
679 uint32_t rix_push_vlan;
680 /**< Index to push VLAN action resource in cache. */
682 /**< Index to the tag action. */
684 /**< Index to sample action resource in cache. */
685 uint32_t rix_dest_array;
686 /**< Index to destination array resource in cache. */
689 /** Device flow handle structure: used both for creating & destroying. */
690 struct mlx5_flow_handle {
691 SILIST_ENTRY(uint32_t)next;
692 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
693 /**< Index to next device flow handle. */
695 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
696 void *drv_flow; /**< pointer to driver flow object. */
697 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
698 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
699 uint32_t mark:1; /**< Metadate rxq mark flag. */
700 uint32_t fate_action:3; /**< Fate action type. */
701 uint32_t flex_item; /**< referenced Flex Item bitmask. */
703 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
704 uint32_t rix_jump; /**< Index to the jump action resource. */
705 uint32_t rix_port_id_action;
706 /**< Index to port ID action resource. */
708 /**< Generic value indicates the fate action. */
709 uint32_t rix_default_fate;
710 /**< Indicates default miss fate action. */
712 /**< Indicates shared RSS fate action. */
714 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
715 struct mlx5_flow_handle_dv dvh;
720 * Size for Verbs device flow handle structure only. Do not use the DV only
721 * structure in Verbs. No DV flows attributes will be accessed.
722 * Macro offsetof() could also be used here.
724 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
725 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
726 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
728 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
731 /** Device flow structure only for DV flow creation. */
732 struct mlx5_flow_dv_workspace {
733 uint32_t group; /**< The group index. */
734 uint32_t table_id; /**< Flow table identifier. */
735 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
736 int actions_n; /**< number of actions. */
737 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
738 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
739 /**< Pointer to encap/decap resource in cache. */
740 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
741 /**< Pointer to push VLAN action resource in cache. */
742 struct mlx5_flow_dv_tag_resource *tag_resource;
743 /**< pointer to the tag action. */
744 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
745 /**< Pointer to port ID action resource. */
746 struct mlx5_flow_dv_jump_tbl_resource *jump;
747 /**< Pointer to the jump action resource. */
748 struct mlx5_flow_dv_match_params value;
749 /**< Holds the value that the packet is compared to. */
750 struct mlx5_flow_dv_sample_resource *sample_res;
751 /**< Pointer to the sample action resource. */
752 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
753 /**< Pointer to the destination array resource. */
756 #ifdef HAVE_INFINIBAND_VERBS_H
758 * Maximal Verbs flow specifications & actions size.
759 * Some elements are mutually exclusive, but enough space should be allocated.
760 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
761 * 2. One tunnel header (exception: GRE + MPLS),
762 * SPEC length: GRE == tunnel.
763 * Actions: 1. 1 Mark OR Flag.
764 * 2. 1 Drop (if any).
765 * 3. No limitation for counters, but it makes no sense to support too
766 * many counters in a single device flow.
768 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
769 #define MLX5_VERBS_MAX_SPEC_SIZE \
771 (2 * (sizeof(struct ibv_flow_spec_eth) + \
772 sizeof(struct ibv_flow_spec_ipv6) + \
773 sizeof(struct ibv_flow_spec_tcp_udp)) + \
774 sizeof(struct ibv_flow_spec_gre) + \
775 sizeof(struct ibv_flow_spec_mpls)) \
778 #define MLX5_VERBS_MAX_SPEC_SIZE \
780 (2 * (sizeof(struct ibv_flow_spec_eth) + \
781 sizeof(struct ibv_flow_spec_ipv6) + \
782 sizeof(struct ibv_flow_spec_tcp_udp)) + \
783 sizeof(struct ibv_flow_spec_tunnel)) \
787 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
788 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
789 #define MLX5_VERBS_MAX_ACT_SIZE \
791 sizeof(struct ibv_flow_spec_action_tag) + \
792 sizeof(struct ibv_flow_spec_action_drop) + \
793 sizeof(struct ibv_flow_spec_counter_action) * 4 \
796 #define MLX5_VERBS_MAX_ACT_SIZE \
798 sizeof(struct ibv_flow_spec_action_tag) + \
799 sizeof(struct ibv_flow_spec_action_drop) \
803 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
804 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
806 /** Device flow structure only for Verbs flow creation. */
807 struct mlx5_flow_verbs_workspace {
808 unsigned int size; /**< Size of the attribute. */
809 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
810 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
811 /**< Specifications & actions buffer of verbs flow. */
813 #endif /* HAVE_INFINIBAND_VERBS_H */
815 #define MLX5_SCALE_FLOW_GROUP_BIT 0
816 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
818 /** Maximal number of device sub-flows supported. */
819 #define MLX5_NUM_MAX_DEV_FLOWS 32
822 * tunnel offload rules type
824 enum mlx5_tof_rule_type {
825 MLX5_TUNNEL_OFFLOAD_NONE = 0,
826 MLX5_TUNNEL_OFFLOAD_SET_RULE,
827 MLX5_TUNNEL_OFFLOAD_MATCH_RULE,
828 MLX5_TUNNEL_OFFLOAD_MISS_RULE,
831 /** Device flow structure. */
834 struct rte_flow *flow; /**< Pointer to the main flow. */
835 uint32_t flow_idx; /**< The memory pool index to the main flow. */
836 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
838 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
839 bool external; /**< true if the flow is created external to PMD. */
840 uint8_t ingress:1; /**< 1 if the flow is ingress. */
841 uint8_t skip_scale:2;
843 * Each Bit be set to 1 if Skip the scale the flow group with factor.
844 * If bit0 be set to 1, then skip the scale the original flow group;
845 * If bit1 be set to 1, then skip the scale the jump flow group if
846 * having jump action.
847 * 00: Enable scale in a flow, default value.
848 * 01: Skip scale the flow group with factor, enable scale the group
850 * 10: Enable scale the group with factor, skip scale the group of
852 * 11: Skip scale the table with factor both for flow group and jump
856 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
857 struct mlx5_flow_dv_workspace dv;
859 #ifdef HAVE_INFINIBAND_VERBS_H
860 struct mlx5_flow_verbs_workspace verbs;
863 struct mlx5_flow_handle *handle;
864 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
865 const struct mlx5_flow_tunnel *tunnel;
866 enum mlx5_tof_rule_type tof_type;
869 /* Flow meter state. */
870 #define MLX5_FLOW_METER_DISABLE 0
871 #define MLX5_FLOW_METER_ENABLE 1
873 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
874 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
876 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
878 #define MLX5_MAN_WIDTH 8
879 /* Legacy Meter parameter structure. */
880 struct mlx5_legacy_flow_meter {
881 struct mlx5_flow_meter_info fm;
882 /* Must be the first in struct. */
883 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
884 /**< Pointer to the next flow meter structure. */
886 /* Index to meter object. */
889 #define MLX5_MAX_TUNNELS 256
890 #define MLX5_TNL_MISS_RULE_PRIORITY 3
891 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
894 * When tunnel offload is active, all JUMP group ids are converted
895 * using the same method. That conversion is applied both to tunnel and
896 * regular rule types.
897 * Group ids used in tunnel rules are relative to it's tunnel (!).
898 * Application can create number of steer rules, using the same
899 * tunnel, with different group id in each rule.
900 * Each tunnel stores its groups internally in PMD tunnel object.
901 * Groups used in regular rules do not belong to any tunnel and are stored
905 struct mlx5_flow_tunnel {
906 LIST_ENTRY(mlx5_flow_tunnel) chain;
907 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
908 uint32_t tunnel_id; /** unique tunnel ID */
910 struct rte_flow_action action;
911 struct rte_flow_item item;
912 struct mlx5_hlist *groups; /** tunnel groups */
915 /** PMD tunnel related context */
916 struct mlx5_flow_tunnel_hub {
918 * Access to the list MUST be MT protected
920 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
921 /* protect access to the tunnels list */
923 struct mlx5_hlist *groups; /** non tunnel groups */
926 /* convert jump group to flow table ID in tunnel rules */
927 struct tunnel_tbl_entry {
928 struct mlx5_list_entry hash;
934 static inline uint32_t
935 tunnel_id_to_flow_tbl(uint32_t id)
937 return id | (1u << 16);
940 static inline uint32_t
941 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
943 return flow_tbl & ~(1u << 16);
946 union tunnel_tbl_key {
954 static inline struct mlx5_flow_tunnel_hub *
955 mlx5_tunnel_hub(struct rte_eth_dev *dev)
957 struct mlx5_priv *priv = dev->data->dev_private;
958 return priv->sh->tunnel_hub;
962 is_tunnel_offload_active(const struct rte_eth_dev *dev)
964 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
965 const struct mlx5_priv *priv = dev->data->dev_private;
966 return !!priv->config.dv_miss_info;
974 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type)
976 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE;
980 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type)
982 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE;
985 static inline const struct mlx5_flow_tunnel *
986 flow_actions_to_tunnel(const struct rte_flow_action actions[])
988 return actions[0].conf;
991 static inline const struct mlx5_flow_tunnel *
992 flow_items_to_tunnel(const struct rte_flow_item items[])
994 return items[0].spec;
997 /* Flow structure. */
999 uint32_t dev_handles;
1000 /**< Device flow handles that are part of the flow. */
1002 uint32_t drv_type:2; /**< Driver type. */
1004 uint32_t meter:24; /**< Holds flow meter id. */
1005 uint32_t indirect_type:2; /**< Indirect action type. */
1006 uint32_t rix_mreg_copy;
1007 /**< Index to metadata register copy table resource. */
1008 uint32_t counter; /**< Holds flow counter. */
1009 uint32_t tunnel_id; /**< Tunnel id */
1011 uint32_t age; /**< Holds ASO age bit index. */
1012 uint32_t ct; /**< Holds ASO CT index. */
1014 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1018 * Define list of valid combinations of RX Hash fields
1019 * (see enum ibv_rx_hash_fields).
1021 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1022 #define MLX5_RSS_HASH_IPV4_TCP \
1023 (MLX5_RSS_HASH_IPV4 | \
1024 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1025 #define MLX5_RSS_HASH_IPV4_UDP \
1026 (MLX5_RSS_HASH_IPV4 | \
1027 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1028 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1029 #define MLX5_RSS_HASH_IPV6_TCP \
1030 (MLX5_RSS_HASH_IPV6 | \
1031 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1032 #define MLX5_RSS_HASH_IPV6_UDP \
1033 (MLX5_RSS_HASH_IPV6 | \
1034 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1035 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1036 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1037 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1038 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1039 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1040 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1041 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1042 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1043 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1044 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1045 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1046 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1047 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1048 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1049 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1050 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1051 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1052 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1053 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1054 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1055 #define MLX5_RSS_HASH_NONE 0ULL
1058 /* extract next protocol type from Ethernet & VLAN headers */
1059 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1060 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1061 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1062 (_prt) = rte_be_to_cpu_16((_prt)); \
1065 /* array of valid combinations of RX Hash fields for RSS */
1066 static const uint64_t mlx5_rss_hash_fields[] = {
1068 MLX5_RSS_HASH_IPV4_TCP,
1069 MLX5_RSS_HASH_IPV4_UDP,
1071 MLX5_RSS_HASH_IPV6_TCP,
1072 MLX5_RSS_HASH_IPV6_UDP,
1076 /* Shared RSS action structure */
1077 struct mlx5_shared_action_rss {
1078 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1079 uint32_t refcnt; /**< Atomically accessed refcnt. */
1080 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1081 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1082 struct mlx5_ind_table_obj *ind_tbl;
1083 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1084 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1085 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1086 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1089 struct rte_flow_action_handle {
1093 /* Thread specific flow workspace intermediate data. */
1094 struct mlx5_flow_workspace {
1095 /* If creating another flow in same thread, push new as stack. */
1096 struct mlx5_flow_workspace *prev;
1097 struct mlx5_flow_workspace *next;
1098 uint32_t inuse; /* can't create new flow with current. */
1099 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1100 struct mlx5_flow_rss_desc rss_desc;
1101 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1102 uint32_t flow_idx; /* Intermediate device flow index. */
1103 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1104 struct mlx5_flow_meter_policy *policy;
1105 /* The meter policy used by meter in flow. */
1106 struct mlx5_flow_meter_policy *final_policy;
1107 /* The final policy when meter policy is hierarchy. */
1108 uint32_t skip_matcher_reg:1;
1109 /* Indicates if need to skip matcher register in translate. */
1112 struct mlx5_flow_split_info {
1114 /**< True if flow is created by request external to PMD. */
1115 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1116 uint32_t flow_idx; /**< This memory pool index to the flow. */
1117 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1118 uint64_t prefix_layers; /**< Prefix subflow layers. */
1119 uint32_t table_id; /**< Flow table identifier. */
1122 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1123 const struct rte_flow_attr *attr,
1124 const struct rte_flow_item items[],
1125 const struct rte_flow_action actions[],
1128 struct rte_flow_error *error);
1129 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1130 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1131 const struct rte_flow_item items[],
1132 const struct rte_flow_action actions[], struct rte_flow_error *error);
1133 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1134 struct mlx5_flow *dev_flow,
1135 const struct rte_flow_attr *attr,
1136 const struct rte_flow_item items[],
1137 const struct rte_flow_action actions[],
1138 struct rte_flow_error *error);
1139 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1140 struct rte_flow_error *error);
1141 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1142 struct rte_flow *flow);
1143 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1144 struct rte_flow *flow);
1145 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1146 struct rte_flow *flow,
1147 const struct rte_flow_action *actions,
1149 struct rte_flow_error *error);
1150 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1151 struct mlx5_flow_meter_info *fm,
1153 uint8_t domain_bitmap);
1154 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1155 struct mlx5_flow_meter_info *fm);
1156 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1157 typedef struct mlx5_flow_meter_sub_policy *
1158 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1159 (struct rte_eth_dev *dev,
1160 struct mlx5_flow_meter_policy *mtr_policy,
1161 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1162 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t)
1163 (struct rte_eth_dev *dev,
1164 struct mlx5_flow_meter_info *fm,
1166 const struct rte_flow_item *item,
1167 struct rte_flow_error *error);
1168 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t)
1169 (struct rte_eth_dev *dev,
1170 struct mlx5_flow_meter_policy *mtr_policy);
1171 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1172 (struct rte_eth_dev *dev);
1173 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1175 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1176 (struct rte_eth_dev *dev);
1177 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1179 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1181 bool clear, uint64_t *pkts,
1183 typedef int (*mlx5_flow_get_aged_flows_t)
1184 (struct rte_eth_dev *dev,
1186 uint32_t nb_contexts,
1187 struct rte_flow_error *error);
1188 typedef int (*mlx5_flow_action_validate_t)
1189 (struct rte_eth_dev *dev,
1190 const struct rte_flow_indir_action_conf *conf,
1191 const struct rte_flow_action *action,
1192 struct rte_flow_error *error);
1193 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1194 (struct rte_eth_dev *dev,
1195 const struct rte_flow_indir_action_conf *conf,
1196 const struct rte_flow_action *action,
1197 struct rte_flow_error *error);
1198 typedef int (*mlx5_flow_action_destroy_t)
1199 (struct rte_eth_dev *dev,
1200 struct rte_flow_action_handle *action,
1201 struct rte_flow_error *error);
1202 typedef int (*mlx5_flow_action_update_t)
1203 (struct rte_eth_dev *dev,
1204 struct rte_flow_action_handle *action,
1206 struct rte_flow_error *error);
1207 typedef int (*mlx5_flow_action_query_t)
1208 (struct rte_eth_dev *dev,
1209 const struct rte_flow_action_handle *action,
1211 struct rte_flow_error *error);
1212 typedef int (*mlx5_flow_sync_domain_t)
1213 (struct rte_eth_dev *dev,
1216 typedef int (*mlx5_flow_validate_mtr_acts_t)
1217 (struct rte_eth_dev *dev,
1218 const struct rte_flow_action *actions[RTE_COLORS],
1219 struct rte_flow_attr *attr,
1221 uint8_t *domain_bitmap,
1222 uint8_t *policy_mode,
1223 struct rte_mtr_error *error);
1224 typedef int (*mlx5_flow_create_mtr_acts_t)
1225 (struct rte_eth_dev *dev,
1226 struct mlx5_flow_meter_policy *mtr_policy,
1227 const struct rte_flow_action *actions[RTE_COLORS],
1228 struct rte_mtr_error *error);
1229 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1230 (struct rte_eth_dev *dev,
1231 struct mlx5_flow_meter_policy *mtr_policy);
1232 typedef int (*mlx5_flow_create_policy_rules_t)
1233 (struct rte_eth_dev *dev,
1234 struct mlx5_flow_meter_policy *mtr_policy);
1235 typedef void (*mlx5_flow_destroy_policy_rules_t)
1236 (struct rte_eth_dev *dev,
1237 struct mlx5_flow_meter_policy *mtr_policy);
1238 typedef int (*mlx5_flow_create_def_policy_t)
1239 (struct rte_eth_dev *dev);
1240 typedef void (*mlx5_flow_destroy_def_policy_t)
1241 (struct rte_eth_dev *dev);
1242 typedef int (*mlx5_flow_discover_priorities_t)
1243 (struct rte_eth_dev *dev,
1244 const uint16_t *vprio, int vprio_n);
1245 typedef struct rte_flow_item_flex_handle *(*mlx5_flow_item_create_t)
1246 (struct rte_eth_dev *dev,
1247 const struct rte_flow_item_flex_conf *conf,
1248 struct rte_flow_error *error);
1249 typedef int (*mlx5_flow_item_release_t)
1250 (struct rte_eth_dev *dev,
1251 const struct rte_flow_item_flex_handle *handle,
1252 struct rte_flow_error *error);
1253 typedef int (*mlx5_flow_item_update_t)
1254 (struct rte_eth_dev *dev,
1255 const struct rte_flow_item_flex_handle *handle,
1256 const struct rte_flow_item_flex_conf *conf,
1257 struct rte_flow_error *error);
1259 struct mlx5_flow_driver_ops {
1260 mlx5_flow_validate_t validate;
1261 mlx5_flow_prepare_t prepare;
1262 mlx5_flow_translate_t translate;
1263 mlx5_flow_apply_t apply;
1264 mlx5_flow_remove_t remove;
1265 mlx5_flow_destroy_t destroy;
1266 mlx5_flow_query_t query;
1267 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1268 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1269 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1270 mlx5_flow_mtr_alloc_t create_meter;
1271 mlx5_flow_mtr_free_t free_meter;
1272 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1273 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1274 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1275 mlx5_flow_create_policy_rules_t create_policy_rules;
1276 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1277 mlx5_flow_create_def_policy_t create_def_policy;
1278 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1279 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1280 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create;
1281 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq;
1282 mlx5_flow_counter_alloc_t counter_alloc;
1283 mlx5_flow_counter_free_t counter_free;
1284 mlx5_flow_counter_query_t counter_query;
1285 mlx5_flow_get_aged_flows_t get_aged_flows;
1286 mlx5_flow_action_validate_t action_validate;
1287 mlx5_flow_action_create_t action_create;
1288 mlx5_flow_action_destroy_t action_destroy;
1289 mlx5_flow_action_update_t action_update;
1290 mlx5_flow_action_query_t action_query;
1291 mlx5_flow_sync_domain_t sync_domain;
1292 mlx5_flow_discover_priorities_t discover_priorities;
1293 mlx5_flow_item_create_t item_create;
1294 mlx5_flow_item_release_t item_release;
1295 mlx5_flow_item_update_t item_update;
1300 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1302 struct flow_grp_info {
1303 uint64_t external:1;
1304 uint64_t transfer:1;
1305 uint64_t fdb_def_rule:1;
1306 /* force standard group translation */
1307 uint64_t std_tbl_fix:1;
1308 uint64_t skip_scale:2;
1312 tunnel_use_standard_attr_group_translate
1313 (const struct rte_eth_dev *dev,
1314 const struct rte_flow_attr *attr,
1315 const struct mlx5_flow_tunnel *tunnel,
1316 enum mlx5_tof_rule_type tof_rule_type)
1320 if (!is_tunnel_offload_active(dev))
1321 /* no tunnel offload API */
1325 * OvS will use jump to group 0 in tunnel steer rule.
1326 * If tunnel steer rule starts from group 0 (attr.group == 0)
1327 * that 0 group must be translated with standard method.
1328 * attr.group == 0 in tunnel match rule translated with tunnel
1331 verdict = !attr->group &&
1332 is_flow_tunnel_steer_rule(tof_rule_type);
1335 * non-tunnel group translation uses standard method for
1336 * root group only: attr.group == 0
1338 verdict = !attr->group;
1345 * Get DV flow aso meter by index.
1348 * Pointer to the Ethernet device structure.
1350 * mlx5 flow aso meter index in the container.
1352 * mlx5 flow aso meter pool in the container,
1355 * Pointer to the aso meter, NULL otherwise.
1357 static inline struct mlx5_aso_mtr *
1358 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1360 struct mlx5_aso_mtr_pool *pool;
1361 struct mlx5_aso_mtr_pools_mng *pools_mng =
1362 &priv->sh->mtrmng->pools_mng;
1364 /* Decrease to original index. */
1366 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1367 rte_rwlock_read_lock(&pools_mng->resize_mtrwl);
1368 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1369 rte_rwlock_read_unlock(&pools_mng->resize_mtrwl);
1370 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1373 static __rte_always_inline const struct rte_flow_item *
1374 mlx5_find_end_item(const struct rte_flow_item *item)
1376 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1380 static __rte_always_inline bool
1381 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1383 struct rte_flow_item_integrity test = *item;
1386 test.ipv4_csum_ok = 0;
1387 test.l4_csum_ok = 0;
1388 return (test.value == 0);
1392 * Get ASO CT action by device and index.
1395 * Pointer to the Ethernet device structure.
1397 * Index to the ASO CT action.
1400 * The specified ASO CT action pointer.
1402 static inline struct mlx5_aso_ct_action *
1403 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx)
1405 struct mlx5_priv *priv = dev->data->dev_private;
1406 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
1407 struct mlx5_aso_ct_pool *pool;
1410 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n);
1411 /* Bit operation AND could be used. */
1412 rte_rwlock_read_lock(&mng->resize_rwl);
1413 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL];
1414 rte_rwlock_read_unlock(&mng->resize_rwl);
1415 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];
1419 * Get ASO CT action by owner & index.
1422 * Pointer to the Ethernet device structure.
1424 * Index to the ASO CT action and owner port combination.
1427 * The specified ASO CT action pointer.
1429 static inline struct mlx5_aso_ct_action *
1430 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx)
1432 struct mlx5_priv *priv = dev->data->dev_private;
1433 struct mlx5_aso_ct_action *ct;
1434 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
1435 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
1437 if (owner == PORT_ID(priv)) {
1438 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
1440 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
1442 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
1443 if (dev->data->dev_started != 1)
1445 ct = flow_aso_ct_get_by_dev_idx(owndev, idx);
1446 if (ct->peer != PORT_ID(priv))
1452 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1453 const struct mlx5_flow_tunnel *tunnel,
1454 uint32_t group, uint32_t *table,
1455 const struct flow_grp_info *flags,
1456 struct rte_flow_error *error);
1457 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1458 int tunnel, uint64_t layer_types,
1459 uint64_t hash_fields);
1460 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1461 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1462 uint32_t subpriority);
1463 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1464 const struct rte_flow_attr *attr);
1465 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1466 const struct rte_flow_attr *attr,
1467 uint32_t subpriority, bool external);
1468 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1469 enum mlx5_feature_name feature,
1471 struct rte_flow_error *error);
1472 const struct rte_flow_action *mlx5_flow_find_action
1473 (const struct rte_flow_action *actions,
1474 enum rte_flow_action_type action);
1475 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1476 const struct rte_flow_action *action,
1477 struct rte_flow_error *error);
1478 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1479 const struct rte_flow_attr *attr,
1480 struct rte_flow_error *error);
1481 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1482 const struct rte_flow_attr *attr,
1483 struct rte_flow_error *error);
1484 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1485 const struct rte_flow_attr *attr,
1486 struct rte_flow_error *error);
1487 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1488 uint64_t action_flags,
1489 const struct rte_flow_attr *attr,
1490 struct rte_flow_error *error);
1491 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1492 uint64_t action_flags,
1493 struct rte_eth_dev *dev,
1494 const struct rte_flow_attr *attr,
1495 struct rte_flow_error *error);
1496 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1497 uint64_t action_flags,
1498 struct rte_eth_dev *dev,
1499 const struct rte_flow_attr *attr,
1500 uint64_t item_flags,
1501 struct rte_flow_error *error);
1502 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1503 const struct rte_flow_attr *attr,
1504 struct rte_flow_error *error);
1505 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1506 const struct rte_flow_attr *attributes,
1507 struct rte_flow_error *error);
1508 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1509 const uint8_t *mask,
1510 const uint8_t *nic_mask,
1512 bool range_accepted,
1513 struct rte_flow_error *error);
1514 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1515 uint64_t item_flags, bool ext_vlan_sup,
1516 struct rte_flow_error *error);
1517 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1518 uint64_t item_flags,
1519 uint8_t target_protocol,
1520 struct rte_flow_error *error);
1521 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1522 uint64_t item_flags,
1523 const struct rte_flow_item *gre_item,
1524 struct rte_flow_error *error);
1525 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1526 uint64_t item_flags,
1528 uint16_t ether_type,
1529 const struct rte_flow_item_ipv4 *acc_mask,
1530 bool range_accepted,
1531 struct rte_flow_error *error);
1532 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1533 uint64_t item_flags,
1535 uint16_t ether_type,
1536 const struct rte_flow_item_ipv6 *acc_mask,
1537 struct rte_flow_error *error);
1538 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1539 const struct rte_flow_item *item,
1540 uint64_t item_flags,
1541 uint64_t prev_layer,
1542 struct rte_flow_error *error);
1543 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1544 uint64_t item_flags,
1545 uint8_t target_protocol,
1546 const struct rte_flow_item_tcp *flow_mask,
1547 struct rte_flow_error *error);
1548 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1549 uint64_t item_flags,
1550 uint8_t target_protocol,
1551 struct rte_flow_error *error);
1552 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1553 uint64_t item_flags,
1554 struct rte_eth_dev *dev,
1555 struct rte_flow_error *error);
1556 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev,
1558 const struct rte_flow_item *item,
1559 uint64_t item_flags,
1560 const struct rte_flow_attr *attr,
1561 struct rte_flow_error *error);
1562 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1563 uint64_t item_flags,
1564 struct rte_eth_dev *dev,
1565 struct rte_flow_error *error);
1566 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1567 uint64_t item_flags,
1568 uint8_t target_protocol,
1569 struct rte_flow_error *error);
1570 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1571 uint64_t item_flags,
1572 uint8_t target_protocol,
1573 struct rte_flow_error *error);
1574 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1575 uint64_t item_flags,
1576 uint8_t target_protocol,
1577 struct rte_flow_error *error);
1578 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1579 uint64_t item_flags,
1580 struct rte_eth_dev *dev,
1581 struct rte_flow_error *error);
1582 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1584 const struct rte_flow_item *geneve_item,
1585 struct rte_eth_dev *dev,
1586 struct rte_flow_error *error);
1587 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1588 uint64_t item_flags,
1590 uint16_t ether_type,
1591 const struct rte_flow_item_ecpri *acc_mask,
1592 struct rte_flow_error *error);
1593 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1594 struct mlx5_flow_meter_info *fm,
1596 uint8_t domain_bitmap);
1597 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1598 struct mlx5_flow_meter_info *fm);
1599 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1600 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1601 (struct rte_eth_dev *dev,
1602 struct mlx5_flow_meter_policy *mtr_policy,
1603 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1604 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
1605 struct mlx5_flow_meter_policy *mtr_policy);
1606 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1607 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev);
1608 int mlx5_action_handle_attach(struct rte_eth_dev *dev);
1609 int mlx5_action_handle_detach(struct rte_eth_dev *dev);
1610 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1611 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1612 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1614 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx);
1615 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1617 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1618 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx,
1619 struct mlx5_list_entry *oentry,
1621 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1622 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1623 uint32_t table_level, uint8_t egress, uint8_t transfer,
1624 bool external, const struct mlx5_flow_tunnel *tunnel,
1625 uint32_t group_id, uint8_t dummy,
1626 uint32_t table_id, struct rte_flow_error *error);
1628 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx);
1629 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1631 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1632 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx,
1633 struct mlx5_list_entry *oentry,
1635 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1637 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1639 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx);
1640 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1641 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx,
1642 struct mlx5_list_entry *oentry,
1644 void flow_dv_modify_clone_free_cb(void *tool_ctx,
1645 struct mlx5_list_entry *entry);
1647 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx);
1648 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1650 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1651 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx,
1652 struct mlx5_list_entry *entry,
1654 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1656 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1658 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx,
1660 void flow_dv_encap_decap_remove_cb(void *tool_ctx,
1661 struct mlx5_list_entry *entry);
1662 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx,
1663 struct mlx5_list_entry *entry,
1665 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx,
1666 struct mlx5_list_entry *entry);
1668 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1670 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx);
1671 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1673 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1675 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx);
1676 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1677 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx,
1678 struct mlx5_list_entry *entry, void *cb_ctx);
1679 void flow_dv_port_id_clone_free_cb(void *tool_ctx,
1680 struct mlx5_list_entry *entry);
1682 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1684 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx,
1686 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1687 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx,
1688 struct mlx5_list_entry *entry, void *cb_ctx);
1689 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx,
1690 struct mlx5_list_entry *entry);
1692 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1694 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx);
1695 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1696 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx,
1697 struct mlx5_list_entry *entry, void *cb_ctx);
1698 void flow_dv_sample_clone_free_cb(void *tool_ctx,
1699 struct mlx5_list_entry *entry);
1701 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1703 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx,
1705 void flow_dv_dest_array_remove_cb(void *tool_ctx,
1706 struct mlx5_list_entry *entry);
1707 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx,
1708 struct mlx5_list_entry *entry, void *cb_ctx);
1709 void flow_dv_dest_array_clone_free_cb(void *tool_ctx,
1710 struct mlx5_list_entry *entry);
1711 int flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
1712 void **action, struct rte_flow_error *error);
1714 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
1715 struct rte_flow_error *error);
1717 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1719 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1720 const struct rte_flow_item *item,
1721 struct rte_flow_error *error);
1722 void flow_release_workspace(void *data);
1723 int mlx5_flow_os_init_workspace_once(void);
1724 void *mlx5_flow_os_get_specific_workspace(void);
1725 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1726 void mlx5_flow_os_release_workspace(void);
1727 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1728 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1729 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1730 const struct rte_flow_action *actions[RTE_COLORS],
1731 struct rte_flow_attr *attr,
1733 uint8_t *domain_bitmap,
1734 uint8_t *policy_mode,
1735 struct rte_mtr_error *error);
1736 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1737 struct mlx5_flow_meter_policy *mtr_policy);
1738 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1739 struct mlx5_flow_meter_policy *mtr_policy,
1740 const struct rte_flow_action *actions[RTE_COLORS],
1741 struct rte_mtr_error *error);
1742 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1743 struct mlx5_flow_meter_policy *mtr_policy);
1744 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1745 struct mlx5_flow_meter_policy *mtr_policy);
1746 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1747 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1748 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1749 struct mlx5_flow_handle *dev_handle);
1750 const struct mlx5_flow_tunnel *
1751 mlx5_get_tof(const struct rte_flow_item *items,
1752 const struct rte_flow_action *actions,
1753 enum mlx5_tof_rule_type *rule_type);
1754 #endif /* RTE_PMD_MLX5_FLOW_H_ */