1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* Private rte flow items. */
22 enum mlx5_rte_flow_item_type {
23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
24 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
30 /* Private (internal) rte flow actions. */
31 enum mlx5_rte_flow_action_type {
32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
34 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
38 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
39 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
40 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
43 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
46 MLX5_INDIRECT_ACTION_TYPE_RSS,
47 MLX5_INDIRECT_ACTION_TYPE_AGE,
48 MLX5_INDIRECT_ACTION_TYPE_COUNT,
49 MLX5_INDIRECT_ACTION_TYPE_CT,
52 /* Matches on selected register. */
53 struct mlx5_rte_flow_item_tag {
58 /* Modify selected register. */
59 struct mlx5_rte_flow_action_set_tag {
66 struct mlx5_flow_action_copy_mreg {
71 /* Matches on source queue. */
72 struct mlx5_rte_flow_item_tx_queue {
76 /* Feature name to allocate metadata register. */
77 enum mlx5_feature_name {
92 /* Default queue number. */
93 #define MLX5_RSSQ_DEFAULT_NUM 16
95 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
96 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
97 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
98 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
99 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
100 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
102 /* Pattern inner Layer bits. */
103 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
104 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
105 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
106 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
107 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
108 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
110 /* Pattern tunnel Layer bits. */
111 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
112 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
113 #define MLX5_FLOW_LAYER_GRE (1u << 14)
114 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
115 /* List of tunnel Layer bits continued below. */
117 /* General pattern items bits. */
118 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
119 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
120 #define MLX5_FLOW_ITEM_TAG (1u << 18)
121 #define MLX5_FLOW_ITEM_MARK (1u << 19)
123 /* Pattern MISC bits. */
124 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
125 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
126 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
128 /* Pattern tunnel Layer bits (continued). */
129 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
130 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
131 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
132 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
135 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
137 /* Pattern tunnel Layer bits (continued). */
138 #define MLX5_FLOW_LAYER_GTP (1u << 28)
140 /* Pattern eCPRI Layer bit. */
141 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
143 /* IPv6 Fragment Extension Header bit. */
144 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
145 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
147 /* Pattern tunnel Layer bits (continued). */
148 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
149 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
151 /* INTEGRITY item bit */
152 #define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34)
154 /* Conntrack item. */
155 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 35)
158 #define MLX5_FLOW_LAYER_OUTER_L3 \
159 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
160 #define MLX5_FLOW_LAYER_OUTER_L4 \
161 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
162 #define MLX5_FLOW_LAYER_OUTER \
163 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
164 MLX5_FLOW_LAYER_OUTER_L4)
167 #define MLX5_FLOW_LAYER_TUNNEL \
168 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
169 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
170 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
171 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
174 #define MLX5_FLOW_LAYER_INNER_L3 \
175 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
176 #define MLX5_FLOW_LAYER_INNER_L4 \
177 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
178 #define MLX5_FLOW_LAYER_INNER \
179 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
180 MLX5_FLOW_LAYER_INNER_L4)
183 #define MLX5_FLOW_LAYER_L2 \
184 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
185 #define MLX5_FLOW_LAYER_L3_IPV4 \
186 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
187 #define MLX5_FLOW_LAYER_L3_IPV6 \
188 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
189 #define MLX5_FLOW_LAYER_L3 \
190 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
191 #define MLX5_FLOW_LAYER_L4 \
192 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
195 #define MLX5_FLOW_ACTION_DROP (1u << 0)
196 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
197 #define MLX5_FLOW_ACTION_RSS (1u << 2)
198 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
199 #define MLX5_FLOW_ACTION_MARK (1u << 4)
200 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
201 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
202 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
203 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
204 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
205 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
206 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
207 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
208 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
209 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
210 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
211 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
212 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
213 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
214 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
215 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
216 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
217 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
218 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
219 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
220 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
221 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
222 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
223 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
224 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
225 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
226 #define MLX5_FLOW_ACTION_METER (1ull << 31)
227 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
228 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
229 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
230 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
231 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
232 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
233 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
234 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
235 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
236 #define MLX5_FLOW_ACTION_CT (1ull << 41)
238 #define MLX5_FLOW_FATE_ACTIONS \
239 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
240 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
241 MLX5_FLOW_ACTION_DEFAULT_MISS | \
242 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
244 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
245 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
246 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
248 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
249 MLX5_FLOW_ACTION_SET_IPV4_DST | \
250 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
251 MLX5_FLOW_ACTION_SET_IPV6_DST | \
252 MLX5_FLOW_ACTION_SET_TP_SRC | \
253 MLX5_FLOW_ACTION_SET_TP_DST | \
254 MLX5_FLOW_ACTION_SET_TTL | \
255 MLX5_FLOW_ACTION_DEC_TTL | \
256 MLX5_FLOW_ACTION_SET_MAC_SRC | \
257 MLX5_FLOW_ACTION_SET_MAC_DST | \
258 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
259 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
260 MLX5_FLOW_ACTION_INC_TCP_ACK | \
261 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
262 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
263 MLX5_FLOW_ACTION_SET_TAG | \
264 MLX5_FLOW_ACTION_MARK_EXT | \
265 MLX5_FLOW_ACTION_SET_META | \
266 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
267 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
268 MLX5_FLOW_ACTION_MODIFY_FIELD)
270 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
271 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
273 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
276 #define IPPROTO_MPLS 137
279 /* UDP port number for MPLS */
280 #define MLX5_UDP_PORT_MPLS 6635
282 /* UDP port numbers for VxLAN. */
283 #define MLX5_UDP_PORT_VXLAN 4789
284 #define MLX5_UDP_PORT_VXLAN_GPE 4790
286 /* UDP port numbers for GENEVE. */
287 #define MLX5_UDP_PORT_GENEVE 6081
289 /* Lowest priority indicator. */
290 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
293 * Max priority for ingress\egress flow groups
294 * greater than 0 and for any transfer flow group.
295 * From user configation: 0 - 21843.
297 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
300 * Number of sub priorities.
301 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
302 * matching on the NIC (firmware dependent) L4 most have the higher priority
303 * followed by L3 and ending with L2.
305 #define MLX5_PRIORITY_MAP_L2 2
306 #define MLX5_PRIORITY_MAP_L3 1
307 #define MLX5_PRIORITY_MAP_L4 0
308 #define MLX5_PRIORITY_MAP_MAX 3
310 /* Valid layer type for IPV4 RSS. */
311 #define MLX5_IPV4_LAYER_TYPES \
312 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
313 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
314 ETH_RSS_NONFRAG_IPV4_OTHER)
316 /* IBV hash source bits for IPV4. */
317 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
319 /* Valid layer type for IPV6 RSS. */
320 #define MLX5_IPV6_LAYER_TYPES \
321 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
322 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
323 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
325 /* IBV hash source bits for IPV6. */
326 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
328 /* IBV hash bits for L3 SRC. */
329 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
331 /* IBV hash bits for L3 DST. */
332 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
334 /* IBV hash bits for TCP. */
335 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
336 IBV_RX_HASH_DST_PORT_TCP)
338 /* IBV hash bits for UDP. */
339 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
340 IBV_RX_HASH_DST_PORT_UDP)
342 /* IBV hash bits for L4 SRC. */
343 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
344 IBV_RX_HASH_SRC_PORT_UDP)
346 /* IBV hash bits for L4 DST. */
347 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
348 IBV_RX_HASH_DST_PORT_UDP)
350 /* Geneve header first 16Bit */
351 #define MLX5_GENEVE_VER_MASK 0x3
352 #define MLX5_GENEVE_VER_SHIFT 14
353 #define MLX5_GENEVE_VER_VAL(a) \
354 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
355 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
356 #define MLX5_GENEVE_OPTLEN_SHIFT 8
357 #define MLX5_GENEVE_OPTLEN_VAL(a) \
358 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
359 #define MLX5_GENEVE_OAMF_MASK 0x1
360 #define MLX5_GENEVE_OAMF_SHIFT 7
361 #define MLX5_GENEVE_OAMF_VAL(a) \
362 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
363 #define MLX5_GENEVE_CRITO_MASK 0x1
364 #define MLX5_GENEVE_CRITO_SHIFT 6
365 #define MLX5_GENEVE_CRITO_VAL(a) \
366 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
367 #define MLX5_GENEVE_RSVD_MASK 0x3F
368 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
370 * The length of the Geneve options fields, expressed in four byte multiples,
371 * not including the eight byte fixed tunnel.
373 #define MLX5_GENEVE_OPT_LEN_0 14
374 #define MLX5_GENEVE_OPT_LEN_1 63
376 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
377 sizeof(struct rte_ipv4_hdr))
378 /* GTP extension header flag. */
379 #define MLX5_GTP_EXT_HEADER_FLAG 4
381 /* GTP extension header max PDU type value. */
382 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
384 /* GTP extension header PDU type shift. */
385 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
387 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
388 #define MLX5_IPV4_FRAG_OFFSET_MASK \
389 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
391 /* Specific item's fields can accept a range of values (using spec and last). */
392 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
393 #define MLX5_ITEM_RANGE_ACCEPTED true
395 /* Software header modify action numbers of a flow. */
396 #define MLX5_ACT_NUM_MDF_IPV4 1
397 #define MLX5_ACT_NUM_MDF_IPV6 4
398 #define MLX5_ACT_NUM_MDF_MAC 2
399 #define MLX5_ACT_NUM_MDF_VID 1
400 #define MLX5_ACT_NUM_MDF_PORT 2
401 #define MLX5_ACT_NUM_MDF_TTL 1
402 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
403 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
404 #define MLX5_ACT_NUM_MDF_TCPACK 1
405 #define MLX5_ACT_NUM_SET_REG 1
406 #define MLX5_ACT_NUM_SET_TAG 1
407 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
408 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
409 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
410 #define MLX5_ACT_NUM_SET_DSCP 1
412 /* Maximum number of fields to modify in MODIFY_FIELD */
413 #define MLX5_ACT_MAX_MOD_FIELDS 5
415 /* Syndrome bits definition for connection tracking. */
416 #define MLX5_CT_SYNDROME_VALID (0x0 << 6)
417 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6)
418 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6)
419 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1)
420 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0)
422 enum mlx5_flow_drv_type {
425 MLX5_FLOW_TYPE_VERBS,
429 /* Fate action type. */
430 enum mlx5_flow_fate_type {
431 MLX5_FLOW_FATE_NONE, /* Egress flow. */
432 MLX5_FLOW_FATE_QUEUE,
434 MLX5_FLOW_FATE_PORT_ID,
436 MLX5_FLOW_FATE_DEFAULT_MISS,
437 MLX5_FLOW_FATE_SHARED_RSS,
441 /* Matcher PRM representation */
442 struct mlx5_flow_dv_match_params {
444 /**< Size of match value. Do NOT split size and key! */
445 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
446 /**< Matcher value. This value is used as the mask or as a key. */
449 /* Matcher structure. */
450 struct mlx5_flow_dv_matcher {
451 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
452 struct mlx5_flow_tbl_resource *tbl;
453 /**< Pointer to the table(group) the matcher associated with. */
454 void *matcher_object; /**< Pointer to DV matcher */
455 uint16_t crc; /**< CRC of key. */
456 uint16_t priority; /**< Priority of matcher. */
457 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
460 #define MLX5_ENCAP_MAX_LEN 132
462 /* Encap/decap resource structure. */
463 struct mlx5_flow_dv_encap_decap_resource {
464 struct mlx5_hlist_entry entry;
465 /* Pointer to next element. */
466 uint32_t refcnt; /**< Reference counter. */
468 /**< Encap/decap action object. */
469 uint8_t buf[MLX5_ENCAP_MAX_LEN];
471 uint8_t reformat_type;
473 uint64_t flags; /**< Flags for RDMA API. */
474 uint32_t idx; /**< Index for the index memory pool. */
477 /* Tag resource structure. */
478 struct mlx5_flow_dv_tag_resource {
479 struct mlx5_hlist_entry entry;
480 /**< hash list entry for tag resource, tag value as the key. */
482 /**< Tag action object. */
483 uint32_t refcnt; /**< Reference counter. */
484 uint32_t idx; /**< Index for the index memory pool. */
485 uint32_t tag_id; /**< Tag ID. */
489 * Number of modification commands.
490 * The maximal actions amount in FW is some constant, and it is 16 in the
491 * latest releases. In some old releases, it will be limited to 8.
492 * Since there is no interface to query the capacity, the maximal value should
493 * be used to allow PMD to create the flow. The validation will be done in the
494 * lower driver layer or FW. A failure will be returned if exceeds the maximal
495 * supported actions number on the root table.
496 * On non-root tables, there is no limitation, but 32 is enough right now.
498 #define MLX5_MAX_MODIFY_NUM 32
499 #define MLX5_ROOT_TBL_MODIFY_NUM 16
501 /* Modify resource structure */
502 struct mlx5_flow_dv_modify_hdr_resource {
503 struct mlx5_hlist_entry entry;
504 void *action; /**< Modify header action object. */
505 /* Key area for hash list matching: */
506 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
507 uint32_t actions_num; /**< Number of modification actions. */
508 uint64_t flags; /**< Flags for RDMA API. */
509 struct mlx5_modification_cmd actions[];
510 /**< Modification actions. */
513 /* Modify resource key of the hash organization. */
514 union mlx5_flow_modify_hdr_key {
516 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
517 uint32_t actions_num:5; /**< Number of modification actions. */
518 uint32_t group:19; /**< Flow group id. */
519 uint32_t cksum; /**< Actions check sum. */
521 uint64_t v64; /**< full 64bits value of key */
524 /* Jump action resource structure. */
525 struct mlx5_flow_dv_jump_tbl_resource {
526 void *action; /**< Pointer to the rdma core action. */
529 /* Port ID resource structure. */
530 struct mlx5_flow_dv_port_id_action_resource {
531 struct mlx5_cache_entry entry;
532 void *action; /**< Action object. */
533 uint32_t port_id; /**< Port ID value. */
534 uint32_t idx; /**< Indexed pool memory index. */
537 /* Push VLAN action resource structure */
538 struct mlx5_flow_dv_push_vlan_action_resource {
539 struct mlx5_cache_entry entry; /* Cache entry. */
540 void *action; /**< Action object. */
541 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
542 rte_be32_t vlan_tag; /**< VLAN tag value. */
543 uint32_t idx; /**< Indexed pool memory index. */
546 /* Metadata register copy table entry. */
547 struct mlx5_flow_mreg_copy_resource {
549 * Hash list entry for copy table.
550 * - Key is 32/64-bit MARK action ID.
551 * - MUST be the first entry.
553 struct mlx5_hlist_entry hlist_ent;
554 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
555 /* List entry for device flows. */
557 uint32_t rix_flow; /* Built flow for copy. */
561 /* Table tunnel parameter. */
562 struct mlx5_flow_tbl_tunnel_prm {
563 const struct mlx5_flow_tunnel *tunnel;
568 /* Table data structure of the hash organization. */
569 struct mlx5_flow_tbl_data_entry {
570 struct mlx5_hlist_entry entry;
571 /**< hash list entry, 64-bits key inside. */
572 struct mlx5_flow_tbl_resource tbl;
573 /**< flow table resource. */
574 struct mlx5_cache_list matchers;
575 /**< matchers' header associated with the flow table. */
576 struct mlx5_flow_dv_jump_tbl_resource jump;
577 /**< jump resource, at most one for each table created. */
578 uint32_t idx; /**< index for the indexed mempool. */
579 /**< tunnel offload */
580 const struct mlx5_flow_tunnel *tunnel;
583 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
584 uint32_t is_egress:1; /**< Egress table. */
585 uint32_t is_transfer:1; /**< Transfer table. */
586 uint32_t dummy:1; /**< DR table. */
587 uint32_t id:22; /**< Table ID. */
588 uint32_t reserve:5; /**< Reserved to future using. */
589 uint32_t level; /**< Table level. */
592 /* Sub rdma-core actions list. */
593 struct mlx5_flow_sub_actions_list {
594 uint32_t actions_num; /**< Number of sample actions. */
595 uint64_t action_flags;
596 void *dr_queue_action;
599 void *dr_port_id_action;
600 void *dr_encap_action;
601 void *dr_jump_action;
604 /* Sample sub-actions resource list. */
605 struct mlx5_flow_sub_actions_idx {
606 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
607 uint32_t rix_tag; /**< Index to the tag action. */
608 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
609 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
610 uint32_t rix_jump; /**< Index to the jump action resource. */
613 /* Sample action resource structure. */
614 struct mlx5_flow_dv_sample_resource {
615 struct mlx5_cache_entry entry; /**< Cache entry. */
617 void *verbs_action; /**< Verbs sample action object. */
618 void **sub_actions; /**< Sample sub-action array. */
620 struct rte_eth_dev *dev; /**< Device registers the action. */
621 uint32_t idx; /** Sample object index. */
622 uint8_t ft_type; /** Flow Table Type */
623 uint32_t ft_id; /** Flow Table Level */
624 uint32_t ratio; /** Sample Ratio */
625 uint64_t set_action; /** Restore reg_c0 value */
626 void *normal_path_tbl; /** Flow Table pointer */
627 struct mlx5_flow_sub_actions_idx sample_idx;
628 /**< Action index resources. */
629 struct mlx5_flow_sub_actions_list sample_act;
630 /**< Action resources. */
633 #define MLX5_MAX_DEST_NUM 2
635 /* Destination array action resource structure. */
636 struct mlx5_flow_dv_dest_array_resource {
637 struct mlx5_cache_entry entry; /**< Cache entry. */
638 uint32_t idx; /** Destination array action object index. */
639 uint8_t ft_type; /** Flow Table Type */
640 uint8_t num_of_dest; /**< Number of destination actions. */
641 struct rte_eth_dev *dev; /**< Device registers the action. */
642 void *action; /**< Pointer to the rdma core action. */
643 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
644 /**< Action index resources. */
645 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
646 /**< Action resources. */
649 /* PMD flow priority for tunnel */
650 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
651 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
654 /** Device flow handle structure for DV mode only. */
655 struct mlx5_flow_handle_dv {
657 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
658 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
659 /**< Pointer to modify header resource in cache. */
660 uint32_t rix_encap_decap;
661 /**< Index to encap/decap resource in cache. */
662 uint32_t rix_push_vlan;
663 /**< Index to push VLAN action resource in cache. */
665 /**< Index to the tag action. */
667 /**< Index to sample action resource in cache. */
668 uint32_t rix_dest_array;
669 /**< Index to destination array resource in cache. */
672 /** Device flow handle structure: used both for creating & destroying. */
673 struct mlx5_flow_handle {
674 SILIST_ENTRY(uint32_t)next;
675 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
676 /**< Index to next device flow handle. */
678 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
679 void *drv_flow; /**< pointer to driver flow object. */
680 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
681 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
682 uint32_t mark:1; /**< Metadate rxq mark flag. */
683 uint32_t fate_action:3; /**< Fate action type. */
685 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
686 uint32_t rix_jump; /**< Index to the jump action resource. */
687 uint32_t rix_port_id_action;
688 /**< Index to port ID action resource. */
690 /**< Generic value indicates the fate action. */
691 uint32_t rix_default_fate;
692 /**< Indicates default miss fate action. */
694 /**< Indicates shared RSS fate action. */
696 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
697 struct mlx5_flow_handle_dv dvh;
702 * Size for Verbs device flow handle structure only. Do not use the DV only
703 * structure in Verbs. No DV flows attributes will be accessed.
704 * Macro offsetof() could also be used here.
706 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
707 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
708 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
710 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
713 /** Device flow structure only for DV flow creation. */
714 struct mlx5_flow_dv_workspace {
715 uint32_t group; /**< The group index. */
716 uint32_t table_id; /**< Flow table identifier. */
717 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
718 int actions_n; /**< number of actions. */
719 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
720 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
721 /**< Pointer to encap/decap resource in cache. */
722 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
723 /**< Pointer to push VLAN action resource in cache. */
724 struct mlx5_flow_dv_tag_resource *tag_resource;
725 /**< pointer to the tag action. */
726 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
727 /**< Pointer to port ID action resource. */
728 struct mlx5_flow_dv_jump_tbl_resource *jump;
729 /**< Pointer to the jump action resource. */
730 struct mlx5_flow_dv_match_params value;
731 /**< Holds the value that the packet is compared to. */
732 struct mlx5_flow_dv_sample_resource *sample_res;
733 /**< Pointer to the sample action resource. */
734 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
735 /**< Pointer to the destination array resource. */
738 #ifdef HAVE_INFINIBAND_VERBS_H
740 * Maximal Verbs flow specifications & actions size.
741 * Some elements are mutually exclusive, but enough space should be allocated.
742 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
743 * 2. One tunnel header (exception: GRE + MPLS),
744 * SPEC length: GRE == tunnel.
745 * Actions: 1. 1 Mark OR Flag.
746 * 2. 1 Drop (if any).
747 * 3. No limitation for counters, but it makes no sense to support too
748 * many counters in a single device flow.
750 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
751 #define MLX5_VERBS_MAX_SPEC_SIZE \
753 (2 * (sizeof(struct ibv_flow_spec_eth) + \
754 sizeof(struct ibv_flow_spec_ipv6) + \
755 sizeof(struct ibv_flow_spec_tcp_udp)) + \
756 sizeof(struct ibv_flow_spec_gre) + \
757 sizeof(struct ibv_flow_spec_mpls)) \
760 #define MLX5_VERBS_MAX_SPEC_SIZE \
762 (2 * (sizeof(struct ibv_flow_spec_eth) + \
763 sizeof(struct ibv_flow_spec_ipv6) + \
764 sizeof(struct ibv_flow_spec_tcp_udp)) + \
765 sizeof(struct ibv_flow_spec_tunnel)) \
769 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
770 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
771 #define MLX5_VERBS_MAX_ACT_SIZE \
773 sizeof(struct ibv_flow_spec_action_tag) + \
774 sizeof(struct ibv_flow_spec_action_drop) + \
775 sizeof(struct ibv_flow_spec_counter_action) * 4 \
778 #define MLX5_VERBS_MAX_ACT_SIZE \
780 sizeof(struct ibv_flow_spec_action_tag) + \
781 sizeof(struct ibv_flow_spec_action_drop) \
785 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
786 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
788 /** Device flow structure only for Verbs flow creation. */
789 struct mlx5_flow_verbs_workspace {
790 unsigned int size; /**< Size of the attribute. */
791 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
792 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
793 /**< Specifications & actions buffer of verbs flow. */
795 #endif /* HAVE_INFINIBAND_VERBS_H */
797 #define MLX5_SCALE_FLOW_GROUP_BIT 0
798 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
800 /** Maximal number of device sub-flows supported. */
801 #define MLX5_NUM_MAX_DEV_FLOWS 32
803 /** Device flow structure. */
806 struct rte_flow *flow; /**< Pointer to the main flow. */
807 uint32_t flow_idx; /**< The memory pool index to the main flow. */
808 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
810 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
811 bool external; /**< true if the flow is created external to PMD. */
812 uint8_t ingress:1; /**< 1 if the flow is ingress. */
813 uint8_t skip_scale:2;
815 * Each Bit be set to 1 if Skip the scale the flow group with factor.
816 * If bit0 be set to 1, then skip the scale the original flow group;
817 * If bit1 be set to 1, then skip the scale the jump flow group if
818 * having jump action.
819 * 00: Enable scale in a flow, default value.
820 * 01: Skip scale the flow group with factor, enable scale the group
822 * 10: Enable scale the group with factor, skip scale the group of
824 * 11: Skip scale the table with factor both for flow group and jump
828 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
829 struct mlx5_flow_dv_workspace dv;
831 #ifdef HAVE_INFINIBAND_VERBS_H
832 struct mlx5_flow_verbs_workspace verbs;
835 struct mlx5_flow_handle *handle;
836 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
837 const struct mlx5_flow_tunnel *tunnel;
840 /* Flow meter state. */
841 #define MLX5_FLOW_METER_DISABLE 0
842 #define MLX5_FLOW_METER_ENABLE 1
844 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
845 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
847 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
849 #define MLX5_MAN_WIDTH 8
850 /* Legacy Meter parameter structure. */
851 struct mlx5_legacy_flow_meter {
852 struct mlx5_flow_meter_info fm;
853 /* Must be the first in struct. */
854 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
855 /**< Pointer to the next flow meter structure. */
857 /* Index to meter object. */
860 #define MLX5_MAX_TUNNELS 256
861 #define MLX5_TNL_MISS_RULE_PRIORITY 3
862 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
865 * When tunnel offload is active, all JUMP group ids are converted
866 * using the same method. That conversion is applied both to tunnel and
867 * regular rule types.
868 * Group ids used in tunnel rules are relative to it's tunnel (!).
869 * Application can create number of steer rules, using the same
870 * tunnel, with different group id in each rule.
871 * Each tunnel stores its groups internally in PMD tunnel object.
872 * Groups used in regular rules do not belong to any tunnel and are stored
876 struct mlx5_flow_tunnel {
877 LIST_ENTRY(mlx5_flow_tunnel) chain;
878 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
879 uint32_t tunnel_id; /** unique tunnel ID */
881 struct rte_flow_action action;
882 struct rte_flow_item item;
883 struct mlx5_hlist *groups; /** tunnel groups */
886 /** PMD tunnel related context */
887 struct mlx5_flow_tunnel_hub {
889 * Access to the list MUST be MT protected
891 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
892 /* protect access to the tunnels list */
894 struct mlx5_hlist *groups; /** non tunnel groups */
897 /* convert jump group to flow table ID in tunnel rules */
898 struct tunnel_tbl_entry {
899 struct mlx5_hlist_entry hash;
905 static inline uint32_t
906 tunnel_id_to_flow_tbl(uint32_t id)
908 return id | (1u << 16);
911 static inline uint32_t
912 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
914 return flow_tbl & ~(1u << 16);
917 union tunnel_tbl_key {
925 static inline struct mlx5_flow_tunnel_hub *
926 mlx5_tunnel_hub(struct rte_eth_dev *dev)
928 struct mlx5_priv *priv = dev->data->dev_private;
929 return priv->sh->tunnel_hub;
933 is_tunnel_offload_active(struct rte_eth_dev *dev)
935 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
936 struct mlx5_priv *priv = dev->data->dev_private;
937 return !!priv->config.dv_miss_info;
945 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
946 __rte_unused const struct rte_flow_attr *attr,
947 __rte_unused const struct rte_flow_item items[],
948 __rte_unused const struct rte_flow_action actions[])
950 return (items[0].type == (typeof(items[0].type))
951 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
955 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
956 __rte_unused const struct rte_flow_attr *attr,
957 __rte_unused const struct rte_flow_item items[],
958 __rte_unused const struct rte_flow_action actions[])
960 return (actions[0].type == (typeof(actions[0].type))
961 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
964 static inline const struct mlx5_flow_tunnel *
965 flow_actions_to_tunnel(const struct rte_flow_action actions[])
967 return actions[0].conf;
970 static inline const struct mlx5_flow_tunnel *
971 flow_items_to_tunnel(const struct rte_flow_item items[])
973 return items[0].spec;
976 /* Flow structure. */
978 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
979 uint32_t dev_handles;
980 /**< Device flow handles that are part of the flow. */
981 uint32_t drv_type:2; /**< Driver type. */
983 uint32_t meter:24; /**< Holds flow meter id. */
984 uint32_t indirect_type:2; /**< Indirect action type. */
985 uint32_t rix_mreg_copy;
986 /**< Index to metadata register copy table resource. */
987 uint32_t counter; /**< Holds flow counter. */
988 uint32_t tunnel_id; /**< Tunnel id */
990 uint32_t age; /**< Holds ASO age bit index. */
991 uint32_t ct; /**< Holds ASO CT index. */
993 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
997 * Define list of valid combinations of RX Hash fields
998 * (see enum ibv_rx_hash_fields).
1000 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1001 #define MLX5_RSS_HASH_IPV4_TCP \
1002 (MLX5_RSS_HASH_IPV4 | \
1003 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1004 #define MLX5_RSS_HASH_IPV4_UDP \
1005 (MLX5_RSS_HASH_IPV4 | \
1006 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1007 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1008 #define MLX5_RSS_HASH_IPV6_TCP \
1009 (MLX5_RSS_HASH_IPV6 | \
1010 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1011 #define MLX5_RSS_HASH_IPV6_UDP \
1012 (MLX5_RSS_HASH_IPV6 | \
1013 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1014 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1015 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1016 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1017 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1018 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1019 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1020 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1021 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1022 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1023 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1024 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1025 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1026 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1027 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1028 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1029 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1030 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1031 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1032 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1033 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1034 #define MLX5_RSS_HASH_NONE 0ULL
1037 /* extract next protocol type from Ethernet & VLAN headers */
1038 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1039 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1040 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1041 (_prt) = rte_be_to_cpu_16((_prt)); \
1044 /* array of valid combinations of RX Hash fields for RSS */
1045 static const uint64_t mlx5_rss_hash_fields[] = {
1047 MLX5_RSS_HASH_IPV4_TCP,
1048 MLX5_RSS_HASH_IPV4_UDP,
1050 MLX5_RSS_HASH_IPV6_TCP,
1051 MLX5_RSS_HASH_IPV6_UDP,
1055 /* Shared RSS action structure */
1056 struct mlx5_shared_action_rss {
1057 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1058 uint32_t refcnt; /**< Atomically accessed refcnt. */
1059 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1060 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1061 struct mlx5_ind_table_obj *ind_tbl;
1062 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1063 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1064 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1065 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1068 struct rte_flow_action_handle {
1072 /* Thread specific flow workspace intermediate data. */
1073 struct mlx5_flow_workspace {
1074 /* If creating another flow in same thread, push new as stack. */
1075 struct mlx5_flow_workspace *prev;
1076 struct mlx5_flow_workspace *next;
1077 uint32_t inuse; /* can't create new flow with current. */
1078 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1079 struct mlx5_flow_rss_desc rss_desc;
1080 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1081 uint32_t flow_idx; /* Intermediate device flow index. */
1082 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1083 uint32_t skip_matcher_reg:1;
1084 /* Indicates if need to skip matcher register in translate. */
1087 struct mlx5_flow_split_info {
1089 /**< True if flow is created by request external to PMD. */
1090 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1091 uint32_t flow_idx; /**< This memory pool index to the flow. */
1092 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1093 uint64_t prefix_layers; /**< Prefix subflow layers. */
1094 uint32_t table_id; /**< Flow table identifier. */
1097 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1098 const struct rte_flow_attr *attr,
1099 const struct rte_flow_item items[],
1100 const struct rte_flow_action actions[],
1103 struct rte_flow_error *error);
1104 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1105 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1106 const struct rte_flow_item items[],
1107 const struct rte_flow_action actions[], struct rte_flow_error *error);
1108 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1109 struct mlx5_flow *dev_flow,
1110 const struct rte_flow_attr *attr,
1111 const struct rte_flow_item items[],
1112 const struct rte_flow_action actions[],
1113 struct rte_flow_error *error);
1114 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1115 struct rte_flow_error *error);
1116 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1117 struct rte_flow *flow);
1118 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1119 struct rte_flow *flow);
1120 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1121 struct rte_flow *flow,
1122 const struct rte_flow_action *actions,
1124 struct rte_flow_error *error);
1125 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1126 struct mlx5_flow_meter_info *fm,
1128 uint8_t domain_bitmap);
1129 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1130 struct mlx5_flow_meter_info *fm);
1131 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1132 typedef struct mlx5_flow_meter_sub_policy *
1133 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1134 (struct rte_eth_dev *dev,
1135 struct mlx5_flow_meter_policy *mtr_policy,
1136 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1137 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1138 (struct rte_eth_dev *dev);
1139 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1141 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1142 (struct rte_eth_dev *dev);
1143 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1145 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1147 bool clear, uint64_t *pkts,
1149 typedef int (*mlx5_flow_get_aged_flows_t)
1150 (struct rte_eth_dev *dev,
1152 uint32_t nb_contexts,
1153 struct rte_flow_error *error);
1154 typedef int (*mlx5_flow_action_validate_t)
1155 (struct rte_eth_dev *dev,
1156 const struct rte_flow_indir_action_conf *conf,
1157 const struct rte_flow_action *action,
1158 struct rte_flow_error *error);
1159 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1160 (struct rte_eth_dev *dev,
1161 const struct rte_flow_indir_action_conf *conf,
1162 const struct rte_flow_action *action,
1163 struct rte_flow_error *error);
1164 typedef int (*mlx5_flow_action_destroy_t)
1165 (struct rte_eth_dev *dev,
1166 struct rte_flow_action_handle *action,
1167 struct rte_flow_error *error);
1168 typedef int (*mlx5_flow_action_update_t)
1169 (struct rte_eth_dev *dev,
1170 struct rte_flow_action_handle *action,
1172 struct rte_flow_error *error);
1173 typedef int (*mlx5_flow_action_query_t)
1174 (struct rte_eth_dev *dev,
1175 const struct rte_flow_action_handle *action,
1177 struct rte_flow_error *error);
1178 typedef int (*mlx5_flow_sync_domain_t)
1179 (struct rte_eth_dev *dev,
1182 typedef int (*mlx5_flow_validate_mtr_acts_t)
1183 (struct rte_eth_dev *dev,
1184 const struct rte_flow_action *actions[RTE_COLORS],
1185 struct rte_flow_attr *attr,
1187 uint8_t *domain_bitmap,
1188 bool *is_def_policy,
1189 struct rte_mtr_error *error);
1190 typedef int (*mlx5_flow_create_mtr_acts_t)
1191 (struct rte_eth_dev *dev,
1192 struct mlx5_flow_meter_policy *mtr_policy,
1193 const struct rte_flow_action *actions[RTE_COLORS],
1194 struct rte_mtr_error *error);
1195 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1196 (struct rte_eth_dev *dev,
1197 struct mlx5_flow_meter_policy *mtr_policy);
1198 typedef int (*mlx5_flow_create_policy_rules_t)
1199 (struct rte_eth_dev *dev,
1200 struct mlx5_flow_meter_policy *mtr_policy);
1201 typedef void (*mlx5_flow_destroy_policy_rules_t)
1202 (struct rte_eth_dev *dev,
1203 struct mlx5_flow_meter_policy *mtr_policy);
1204 typedef int (*mlx5_flow_create_def_policy_t)
1205 (struct rte_eth_dev *dev);
1206 typedef void (*mlx5_flow_destroy_def_policy_t)
1207 (struct rte_eth_dev *dev);
1209 struct mlx5_flow_driver_ops {
1210 mlx5_flow_validate_t validate;
1211 mlx5_flow_prepare_t prepare;
1212 mlx5_flow_translate_t translate;
1213 mlx5_flow_apply_t apply;
1214 mlx5_flow_remove_t remove;
1215 mlx5_flow_destroy_t destroy;
1216 mlx5_flow_query_t query;
1217 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1218 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1219 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1220 mlx5_flow_mtr_alloc_t create_meter;
1221 mlx5_flow_mtr_free_t free_meter;
1222 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1223 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1224 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1225 mlx5_flow_create_policy_rules_t create_policy_rules;
1226 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1227 mlx5_flow_create_def_policy_t create_def_policy;
1228 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1229 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1230 mlx5_flow_counter_alloc_t counter_alloc;
1231 mlx5_flow_counter_free_t counter_free;
1232 mlx5_flow_counter_query_t counter_query;
1233 mlx5_flow_get_aged_flows_t get_aged_flows;
1234 mlx5_flow_action_validate_t action_validate;
1235 mlx5_flow_action_create_t action_create;
1236 mlx5_flow_action_destroy_t action_destroy;
1237 mlx5_flow_action_update_t action_update;
1238 mlx5_flow_action_query_t action_query;
1239 mlx5_flow_sync_domain_t sync_domain;
1244 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1246 struct flow_grp_info {
1247 uint64_t external:1;
1248 uint64_t transfer:1;
1249 uint64_t fdb_def_rule:1;
1250 /* force standard group translation */
1251 uint64_t std_tbl_fix:1;
1252 uint64_t skip_scale:2;
1256 tunnel_use_standard_attr_group_translate
1257 (struct rte_eth_dev *dev,
1258 const struct mlx5_flow_tunnel *tunnel,
1259 const struct rte_flow_attr *attr,
1260 const struct rte_flow_item items[],
1261 const struct rte_flow_action actions[])
1265 if (!is_tunnel_offload_active(dev))
1266 /* no tunnel offload API */
1270 * OvS will use jump to group 0 in tunnel steer rule.
1271 * If tunnel steer rule starts from group 0 (attr.group == 0)
1272 * that 0 group must be translated with standard method.
1273 * attr.group == 0 in tunnel match rule translated with tunnel
1276 verdict = !attr->group &&
1277 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1280 * non-tunnel group translation uses standard method for
1281 * root group only: attr.group == 0
1283 verdict = !attr->group;
1290 * Get DV flow aso meter by index.
1293 * Pointer to the Ethernet device structure.
1295 * mlx5 flow aso meter index in the container.
1297 * mlx5 flow aso meter pool in the container,
1300 * Pointer to the aso meter, NULL otherwise.
1302 static inline struct mlx5_aso_mtr *
1303 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1305 struct mlx5_aso_mtr_pool *pool;
1306 struct mlx5_aso_mtr_pools_mng *pools_mng =
1307 &priv->sh->mtrmng->pools_mng;
1309 /* Decrease to original index. */
1311 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1312 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1313 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1316 static __rte_always_inline const struct rte_flow_item *
1317 mlx5_find_end_item(const struct rte_flow_item *item)
1319 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1323 static __rte_always_inline bool
1324 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1326 struct rte_flow_item_integrity test = *item;
1329 test.ipv4_csum_ok = 0;
1330 test.l4_csum_ok = 0;
1331 return (test.value == 0);
1335 * Get ASO CT action by index.
1338 * Pointer to the Ethernet device structure.
1340 * Index to the ASO CT action.
1343 * The specified ASO CT action pointer.
1345 static inline struct mlx5_aso_ct_action *
1346 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t idx)
1348 struct mlx5_priv *priv = dev->data->dev_private;
1349 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
1350 struct mlx5_aso_ct_pool *pool;
1353 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n);
1354 /* Bit operation AND could be used. */
1355 rte_rwlock_read_lock(&mng->resize_rwl);
1356 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL];
1357 rte_rwlock_read_unlock(&mng->resize_rwl);
1358 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];
1361 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1362 const struct mlx5_flow_tunnel *tunnel,
1363 uint32_t group, uint32_t *table,
1364 const struct flow_grp_info *flags,
1365 struct rte_flow_error *error);
1366 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1367 int tunnel, uint64_t layer_types,
1368 uint64_t hash_fields);
1369 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1370 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1371 uint32_t subpriority);
1372 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1373 const struct rte_flow_attr *attr);
1374 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1375 const struct rte_flow_attr *attr,
1376 uint32_t subpriority);
1377 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1378 enum mlx5_feature_name feature,
1380 struct rte_flow_error *error);
1381 const struct rte_flow_action *mlx5_flow_find_action
1382 (const struct rte_flow_action *actions,
1383 enum rte_flow_action_type action);
1384 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1385 const struct rte_flow_action *action,
1386 struct rte_flow_error *error);
1387 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1388 const struct rte_flow_attr *attr,
1389 struct rte_flow_error *error);
1390 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1391 const struct rte_flow_attr *attr,
1392 struct rte_flow_error *error);
1393 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1394 const struct rte_flow_attr *attr,
1395 struct rte_flow_error *error);
1396 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1397 uint64_t action_flags,
1398 const struct rte_flow_attr *attr,
1399 struct rte_flow_error *error);
1400 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1401 uint64_t action_flags,
1402 struct rte_eth_dev *dev,
1403 const struct rte_flow_attr *attr,
1404 struct rte_flow_error *error);
1405 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1406 uint64_t action_flags,
1407 struct rte_eth_dev *dev,
1408 const struct rte_flow_attr *attr,
1409 uint64_t item_flags,
1410 struct rte_flow_error *error);
1411 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1412 const struct rte_flow_attr *attr,
1413 struct rte_flow_error *error);
1414 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1415 const struct rte_flow_attr *attributes,
1416 struct rte_flow_error *error);
1417 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1418 const uint8_t *mask,
1419 const uint8_t *nic_mask,
1421 bool range_accepted,
1422 struct rte_flow_error *error);
1423 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1424 uint64_t item_flags, bool ext_vlan_sup,
1425 struct rte_flow_error *error);
1426 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1427 uint64_t item_flags,
1428 uint8_t target_protocol,
1429 struct rte_flow_error *error);
1430 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1431 uint64_t item_flags,
1432 const struct rte_flow_item *gre_item,
1433 struct rte_flow_error *error);
1434 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1435 uint64_t item_flags,
1437 uint16_t ether_type,
1438 const struct rte_flow_item_ipv4 *acc_mask,
1439 bool range_accepted,
1440 struct rte_flow_error *error);
1441 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1442 uint64_t item_flags,
1444 uint16_t ether_type,
1445 const struct rte_flow_item_ipv6 *acc_mask,
1446 struct rte_flow_error *error);
1447 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1448 const struct rte_flow_item *item,
1449 uint64_t item_flags,
1450 uint64_t prev_layer,
1451 struct rte_flow_error *error);
1452 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1453 uint64_t item_flags,
1454 uint8_t target_protocol,
1455 const struct rte_flow_item_tcp *flow_mask,
1456 struct rte_flow_error *error);
1457 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1458 uint64_t item_flags,
1459 uint8_t target_protocol,
1460 struct rte_flow_error *error);
1461 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1462 uint64_t item_flags,
1463 struct rte_eth_dev *dev,
1464 struct rte_flow_error *error);
1465 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1466 uint64_t item_flags,
1467 struct rte_flow_error *error);
1468 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1469 uint64_t item_flags,
1470 struct rte_eth_dev *dev,
1471 struct rte_flow_error *error);
1472 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1473 uint64_t item_flags,
1474 uint8_t target_protocol,
1475 struct rte_flow_error *error);
1476 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1477 uint64_t item_flags,
1478 uint8_t target_protocol,
1479 struct rte_flow_error *error);
1480 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1481 uint64_t item_flags,
1482 uint8_t target_protocol,
1483 struct rte_flow_error *error);
1484 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1485 uint64_t item_flags,
1486 struct rte_eth_dev *dev,
1487 struct rte_flow_error *error);
1488 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1490 const struct rte_flow_item *geneve_item,
1491 struct rte_eth_dev *dev,
1492 struct rte_flow_error *error);
1493 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1494 uint64_t item_flags,
1496 uint16_t ether_type,
1497 const struct rte_flow_item_ecpri *acc_mask,
1498 struct rte_flow_error *error);
1499 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1500 struct mlx5_flow_meter_info *fm,
1502 uint8_t domain_bitmap);
1503 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1504 struct mlx5_flow_meter_info *fm);
1505 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1506 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1507 (struct rte_eth_dev *dev,
1508 struct mlx5_flow_meter_policy *mtr_policy,
1509 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1510 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1511 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1512 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1513 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1515 /* Hash list callbacks for flow tables: */
1516 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1517 uint64_t key, void *entry_ctx);
1518 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1519 struct mlx5_hlist_entry *entry, uint64_t key,
1521 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1522 struct mlx5_hlist_entry *entry);
1523 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1524 uint32_t table_level, uint8_t egress, uint8_t transfer,
1525 bool external, const struct mlx5_flow_tunnel *tunnel,
1526 uint32_t group_id, uint8_t dummy,
1527 uint32_t table_id, struct rte_flow_error *error);
1529 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1530 uint64_t key, void *cb_ctx);
1531 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1532 struct mlx5_hlist_entry *entry, uint64_t key,
1534 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1535 struct mlx5_hlist_entry *entry);
1537 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1538 struct mlx5_hlist_entry *entry,
1539 uint64_t key, void *cb_ctx);
1540 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1541 uint64_t key, void *ctx);
1542 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1543 struct mlx5_hlist_entry *entry);
1545 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1546 uint64_t key, void *ctx);
1547 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1548 struct mlx5_hlist_entry *entry, uint64_t key,
1550 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1551 struct mlx5_hlist_entry *entry);
1553 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1554 struct mlx5_hlist_entry *entry,
1555 uint64_t key, void *cb_ctx);
1556 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1557 uint64_t key, void *cb_ctx);
1558 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1559 struct mlx5_hlist_entry *entry);
1561 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1562 struct mlx5_cache_entry *entry, void *ctx);
1563 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1564 struct mlx5_cache_entry *entry, void *ctx);
1565 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1566 struct mlx5_cache_entry *entry);
1568 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1569 struct mlx5_cache_entry *entry, void *cb_ctx);
1570 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1571 struct mlx5_cache_entry *entry, void *cb_ctx);
1572 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1573 struct mlx5_cache_entry *entry);
1575 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1576 struct mlx5_cache_entry *entry, void *cb_ctx);
1577 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1578 (struct mlx5_cache_list *list,
1579 struct mlx5_cache_entry *entry, void *cb_ctx);
1580 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1581 struct mlx5_cache_entry *entry);
1583 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1584 struct mlx5_cache_entry *entry, void *cb_ctx);
1585 struct mlx5_cache_entry *flow_dv_sample_create_cb
1586 (struct mlx5_cache_list *list,
1587 struct mlx5_cache_entry *entry, void *cb_ctx);
1588 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1589 struct mlx5_cache_entry *entry);
1591 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1592 struct mlx5_cache_entry *entry, void *cb_ctx);
1593 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1594 (struct mlx5_cache_list *list,
1595 struct mlx5_cache_entry *entry, void *cb_ctx);
1596 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1597 struct mlx5_cache_entry *entry);
1598 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1600 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1601 const struct rte_flow_item *item,
1602 struct rte_flow_error *error);
1603 void flow_release_workspace(void *data);
1604 int mlx5_flow_os_init_workspace_once(void);
1605 void *mlx5_flow_os_get_specific_workspace(void);
1606 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1607 void mlx5_flow_os_release_workspace(void);
1608 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1609 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1610 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1611 const struct rte_flow_action *actions[RTE_COLORS],
1612 struct rte_flow_attr *attr,
1614 uint8_t *domain_bitmap,
1615 bool *is_def_policy,
1616 struct rte_mtr_error *error);
1617 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1618 struct mlx5_flow_meter_policy *mtr_policy);
1619 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1620 struct mlx5_flow_meter_policy *mtr_policy,
1621 const struct rte_flow_action *actions[RTE_COLORS],
1622 struct rte_mtr_error *error);
1623 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1624 struct mlx5_flow_meter_policy *mtr_policy);
1625 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1626 struct mlx5_flow_meter_policy *mtr_policy);
1627 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1628 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1629 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1630 struct mlx5_flow_handle *dev_handle);
1631 #endif /* RTE_PMD_MLX5_FLOW_H_ */