1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* Private rte flow items. */
22 enum mlx5_rte_flow_item_type {
23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
24 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
30 /* Private (internal) rte flow actions. */
31 enum mlx5_rte_flow_action_type {
32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
34 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
38 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
39 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
40 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
43 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
46 MLX5_INDIRECT_ACTION_TYPE_RSS,
47 MLX5_INDIRECT_ACTION_TYPE_AGE,
48 MLX5_INDIRECT_ACTION_TYPE_COUNT,
51 /* Matches on selected register. */
52 struct mlx5_rte_flow_item_tag {
57 /* Modify selected register. */
58 struct mlx5_rte_flow_action_set_tag {
65 struct mlx5_flow_action_copy_mreg {
70 /* Matches on source queue. */
71 struct mlx5_rte_flow_item_tx_queue {
75 /* Feature name to allocate metadata register. */
76 enum mlx5_feature_name {
90 /* Default queue number. */
91 #define MLX5_RSSQ_DEFAULT_NUM 16
93 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
94 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
95 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
96 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
97 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
98 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
100 /* Pattern inner Layer bits. */
101 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
102 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
103 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
104 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
105 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
106 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
108 /* Pattern tunnel Layer bits. */
109 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
110 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
111 #define MLX5_FLOW_LAYER_GRE (1u << 14)
112 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
113 /* List of tunnel Layer bits continued below. */
115 /* General pattern items bits. */
116 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
117 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
118 #define MLX5_FLOW_ITEM_TAG (1u << 18)
119 #define MLX5_FLOW_ITEM_MARK (1u << 19)
121 /* Pattern MISC bits. */
122 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
123 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
124 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
126 /* Pattern tunnel Layer bits (continued). */
127 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
128 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
129 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
130 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
133 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
135 /* Pattern tunnel Layer bits (continued). */
136 #define MLX5_FLOW_LAYER_GTP (1u << 28)
138 /* Pattern eCPRI Layer bit. */
139 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
141 /* IPv6 Fragment Extension Header bit. */
142 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
143 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
145 /* Pattern tunnel Layer bits (continued). */
146 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
147 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
150 #define MLX5_FLOW_LAYER_OUTER_L3 \
151 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
152 #define MLX5_FLOW_LAYER_OUTER_L4 \
153 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
154 #define MLX5_FLOW_LAYER_OUTER \
155 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
156 MLX5_FLOW_LAYER_OUTER_L4)
159 #define MLX5_FLOW_LAYER_TUNNEL \
160 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
161 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
162 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
163 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
166 #define MLX5_FLOW_LAYER_INNER_L3 \
167 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
168 #define MLX5_FLOW_LAYER_INNER_L4 \
169 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
170 #define MLX5_FLOW_LAYER_INNER \
171 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
172 MLX5_FLOW_LAYER_INNER_L4)
175 #define MLX5_FLOW_LAYER_L2 \
176 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
177 #define MLX5_FLOW_LAYER_L3_IPV4 \
178 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
179 #define MLX5_FLOW_LAYER_L3_IPV6 \
180 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
181 #define MLX5_FLOW_LAYER_L3 \
182 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
183 #define MLX5_FLOW_LAYER_L4 \
184 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
187 #define MLX5_FLOW_ACTION_DROP (1u << 0)
188 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
189 #define MLX5_FLOW_ACTION_RSS (1u << 2)
190 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
191 #define MLX5_FLOW_ACTION_MARK (1u << 4)
192 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
193 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
194 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
195 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
196 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
197 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
198 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
199 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
200 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
201 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
202 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
203 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
204 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
205 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
206 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
207 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
208 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
209 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
210 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
211 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
212 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
213 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
214 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
215 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
216 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
217 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
218 #define MLX5_FLOW_ACTION_METER (1ull << 31)
219 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
220 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
221 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
222 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
223 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
224 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
225 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
226 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
227 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
229 #define MLX5_FLOW_FATE_ACTIONS \
230 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
231 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
232 MLX5_FLOW_ACTION_DEFAULT_MISS | \
233 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
235 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
236 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
237 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
239 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
240 MLX5_FLOW_ACTION_SET_IPV4_DST | \
241 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
242 MLX5_FLOW_ACTION_SET_IPV6_DST | \
243 MLX5_FLOW_ACTION_SET_TP_SRC | \
244 MLX5_FLOW_ACTION_SET_TP_DST | \
245 MLX5_FLOW_ACTION_SET_TTL | \
246 MLX5_FLOW_ACTION_DEC_TTL | \
247 MLX5_FLOW_ACTION_SET_MAC_SRC | \
248 MLX5_FLOW_ACTION_SET_MAC_DST | \
249 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
250 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
251 MLX5_FLOW_ACTION_INC_TCP_ACK | \
252 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
253 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
254 MLX5_FLOW_ACTION_SET_TAG | \
255 MLX5_FLOW_ACTION_MARK_EXT | \
256 MLX5_FLOW_ACTION_SET_META | \
257 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
258 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
259 MLX5_FLOW_ACTION_MODIFY_FIELD)
261 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
262 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
264 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
267 #define IPPROTO_MPLS 137
270 /* UDP port number for MPLS */
271 #define MLX5_UDP_PORT_MPLS 6635
273 /* UDP port numbers for VxLAN. */
274 #define MLX5_UDP_PORT_VXLAN 4789
275 #define MLX5_UDP_PORT_VXLAN_GPE 4790
277 /* UDP port numbers for GENEVE. */
278 #define MLX5_UDP_PORT_GENEVE 6081
280 /* Lowest priority indicator. */
281 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
284 * Max priority for ingress\egress flow groups
285 * greater than 0 and for any transfer flow group.
286 * From user configation: 0 - 21843.
288 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
291 * Number of sub priorities.
292 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
293 * matching on the NIC (firmware dependent) L4 most have the higher priority
294 * followed by L3 and ending with L2.
296 #define MLX5_PRIORITY_MAP_L2 2
297 #define MLX5_PRIORITY_MAP_L3 1
298 #define MLX5_PRIORITY_MAP_L4 0
299 #define MLX5_PRIORITY_MAP_MAX 3
301 /* Valid layer type for IPV4 RSS. */
302 #define MLX5_IPV4_LAYER_TYPES \
303 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
304 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
305 ETH_RSS_NONFRAG_IPV4_OTHER)
307 /* IBV hash source bits for IPV4. */
308 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
310 /* Valid layer type for IPV6 RSS. */
311 #define MLX5_IPV6_LAYER_TYPES \
312 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
313 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
314 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
316 /* IBV hash source bits for IPV6. */
317 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
319 /* IBV hash bits for L3 SRC. */
320 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
322 /* IBV hash bits for L3 DST. */
323 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
325 /* IBV hash bits for TCP. */
326 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
327 IBV_RX_HASH_DST_PORT_TCP)
329 /* IBV hash bits for UDP. */
330 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
331 IBV_RX_HASH_DST_PORT_UDP)
333 /* IBV hash bits for L4 SRC. */
334 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
335 IBV_RX_HASH_SRC_PORT_UDP)
337 /* IBV hash bits for L4 DST. */
338 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
339 IBV_RX_HASH_DST_PORT_UDP)
341 /* Geneve header first 16Bit */
342 #define MLX5_GENEVE_VER_MASK 0x3
343 #define MLX5_GENEVE_VER_SHIFT 14
344 #define MLX5_GENEVE_VER_VAL(a) \
345 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
346 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
347 #define MLX5_GENEVE_OPTLEN_SHIFT 8
348 #define MLX5_GENEVE_OPTLEN_VAL(a) \
349 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
350 #define MLX5_GENEVE_OAMF_MASK 0x1
351 #define MLX5_GENEVE_OAMF_SHIFT 7
352 #define MLX5_GENEVE_OAMF_VAL(a) \
353 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
354 #define MLX5_GENEVE_CRITO_MASK 0x1
355 #define MLX5_GENEVE_CRITO_SHIFT 6
356 #define MLX5_GENEVE_CRITO_VAL(a) \
357 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
358 #define MLX5_GENEVE_RSVD_MASK 0x3F
359 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
361 * The length of the Geneve options fields, expressed in four byte multiples,
362 * not including the eight byte fixed tunnel.
364 #define MLX5_GENEVE_OPT_LEN_0 14
365 #define MLX5_GENEVE_OPT_LEN_1 63
367 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
368 sizeof(struct rte_ipv4_hdr))
369 /* GTP extension header flag. */
370 #define MLX5_GTP_EXT_HEADER_FLAG 4
372 /* GTP extension header max PDU type value. */
373 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
375 /* GTP extension header PDU type shift. */
376 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
378 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
379 #define MLX5_IPV4_FRAG_OFFSET_MASK \
380 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
382 /* Specific item's fields can accept a range of values (using spec and last). */
383 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
384 #define MLX5_ITEM_RANGE_ACCEPTED true
386 /* Software header modify action numbers of a flow. */
387 #define MLX5_ACT_NUM_MDF_IPV4 1
388 #define MLX5_ACT_NUM_MDF_IPV6 4
389 #define MLX5_ACT_NUM_MDF_MAC 2
390 #define MLX5_ACT_NUM_MDF_VID 1
391 #define MLX5_ACT_NUM_MDF_PORT 2
392 #define MLX5_ACT_NUM_MDF_TTL 1
393 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
394 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
395 #define MLX5_ACT_NUM_MDF_TCPACK 1
396 #define MLX5_ACT_NUM_SET_REG 1
397 #define MLX5_ACT_NUM_SET_TAG 1
398 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
399 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
400 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
401 #define MLX5_ACT_NUM_SET_DSCP 1
403 /* Maximum number of fields to modify in MODIFY_FIELD */
404 #define MLX5_ACT_MAX_MOD_FIELDS 5
406 enum mlx5_flow_drv_type {
409 MLX5_FLOW_TYPE_VERBS,
413 /* Fate action type. */
414 enum mlx5_flow_fate_type {
415 MLX5_FLOW_FATE_NONE, /* Egress flow. */
416 MLX5_FLOW_FATE_QUEUE,
418 MLX5_FLOW_FATE_PORT_ID,
420 MLX5_FLOW_FATE_DEFAULT_MISS,
421 MLX5_FLOW_FATE_SHARED_RSS,
425 /* Matcher PRM representation */
426 struct mlx5_flow_dv_match_params {
428 /**< Size of match value. Do NOT split size and key! */
429 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
430 /**< Matcher value. This value is used as the mask or as a key. */
433 /* Matcher structure. */
434 struct mlx5_flow_dv_matcher {
435 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
436 struct mlx5_flow_tbl_resource *tbl;
437 /**< Pointer to the table(group) the matcher associated with. */
438 void *matcher_object; /**< Pointer to DV matcher */
439 uint16_t crc; /**< CRC of key. */
440 uint16_t priority; /**< Priority of matcher. */
441 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
444 #define MLX5_ENCAP_MAX_LEN 132
446 /* Encap/decap resource structure. */
447 struct mlx5_flow_dv_encap_decap_resource {
448 struct mlx5_hlist_entry entry;
449 /* Pointer to next element. */
450 uint32_t refcnt; /**< Reference counter. */
452 /**< Encap/decap action object. */
453 uint8_t buf[MLX5_ENCAP_MAX_LEN];
455 uint8_t reformat_type;
457 uint64_t flags; /**< Flags for RDMA API. */
458 uint32_t idx; /**< Index for the index memory pool. */
461 /* Tag resource structure. */
462 struct mlx5_flow_dv_tag_resource {
463 struct mlx5_hlist_entry entry;
464 /**< hash list entry for tag resource, tag value as the key. */
466 /**< Tag action object. */
467 uint32_t refcnt; /**< Reference counter. */
468 uint32_t idx; /**< Index for the index memory pool. */
469 uint32_t tag_id; /**< Tag ID. */
473 * Number of modification commands.
474 * The maximal actions amount in FW is some constant, and it is 16 in the
475 * latest releases. In some old releases, it will be limited to 8.
476 * Since there is no interface to query the capacity, the maximal value should
477 * be used to allow PMD to create the flow. The validation will be done in the
478 * lower driver layer or FW. A failure will be returned if exceeds the maximal
479 * supported actions number on the root table.
480 * On non-root tables, there is no limitation, but 32 is enough right now.
482 #define MLX5_MAX_MODIFY_NUM 32
483 #define MLX5_ROOT_TBL_MODIFY_NUM 16
485 /* Modify resource structure */
486 struct mlx5_flow_dv_modify_hdr_resource {
487 struct mlx5_hlist_entry entry;
488 void *action; /**< Modify header action object. */
489 /* Key area for hash list matching: */
490 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
491 uint32_t actions_num; /**< Number of modification actions. */
492 uint64_t flags; /**< Flags for RDMA API. */
493 struct mlx5_modification_cmd actions[];
494 /**< Modification actions. */
497 /* Modify resource key of the hash organization. */
498 union mlx5_flow_modify_hdr_key {
500 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
501 uint32_t actions_num:5; /**< Number of modification actions. */
502 uint32_t group:19; /**< Flow group id. */
503 uint32_t cksum; /**< Actions check sum. */
505 uint64_t v64; /**< full 64bits value of key */
508 /* Jump action resource structure. */
509 struct mlx5_flow_dv_jump_tbl_resource {
510 void *action; /**< Pointer to the rdma core action. */
513 /* Port ID resource structure. */
514 struct mlx5_flow_dv_port_id_action_resource {
515 struct mlx5_cache_entry entry;
516 void *action; /**< Action object. */
517 uint32_t port_id; /**< Port ID value. */
518 uint32_t idx; /**< Indexed pool memory index. */
521 /* Push VLAN action resource structure */
522 struct mlx5_flow_dv_push_vlan_action_resource {
523 struct mlx5_cache_entry entry; /* Cache entry. */
524 void *action; /**< Action object. */
525 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
526 rte_be32_t vlan_tag; /**< VLAN tag value. */
527 uint32_t idx; /**< Indexed pool memory index. */
530 /* Metadata register copy table entry. */
531 struct mlx5_flow_mreg_copy_resource {
533 * Hash list entry for copy table.
534 * - Key is 32/64-bit MARK action ID.
535 * - MUST be the first entry.
537 struct mlx5_hlist_entry hlist_ent;
538 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
539 /* List entry for device flows. */
541 uint32_t rix_flow; /* Built flow for copy. */
545 /* Table tunnel parameter. */
546 struct mlx5_flow_tbl_tunnel_prm {
547 const struct mlx5_flow_tunnel *tunnel;
552 /* Table data structure of the hash organization. */
553 struct mlx5_flow_tbl_data_entry {
554 struct mlx5_hlist_entry entry;
555 /**< hash list entry, 64-bits key inside. */
556 struct mlx5_flow_tbl_resource tbl;
557 /**< flow table resource. */
558 struct mlx5_cache_list matchers;
559 /**< matchers' header associated with the flow table. */
560 struct mlx5_flow_dv_jump_tbl_resource jump;
561 /**< jump resource, at most one for each table created. */
562 uint32_t idx; /**< index for the indexed mempool. */
563 /**< tunnel offload */
564 const struct mlx5_flow_tunnel *tunnel;
567 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
568 uint32_t is_egress:1; /**< Egress table. */
569 uint32_t is_transfer:1; /**< Transfer table. */
570 uint32_t dummy:1; /**< DR table. */
571 uint32_t id:22; /**< Table ID. */
572 uint32_t reserve:5; /**< Reserved to future using. */
573 uint32_t level; /**< Table level. */
576 /* Sub rdma-core actions list. */
577 struct mlx5_flow_sub_actions_list {
578 uint32_t actions_num; /**< Number of sample actions. */
579 uint64_t action_flags;
580 void *dr_queue_action;
583 void *dr_port_id_action;
584 void *dr_encap_action;
585 void *dr_jump_action;
588 /* Sample sub-actions resource list. */
589 struct mlx5_flow_sub_actions_idx {
590 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
591 uint32_t rix_tag; /**< Index to the tag action. */
592 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
593 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
594 uint32_t rix_jump; /**< Index to the jump action resource. */
597 /* Sample action resource structure. */
598 struct mlx5_flow_dv_sample_resource {
599 struct mlx5_cache_entry entry; /**< Cache entry. */
601 void *verbs_action; /**< Verbs sample action object. */
602 void **sub_actions; /**< Sample sub-action array. */
604 struct rte_eth_dev *dev; /**< Device registers the action. */
605 uint32_t idx; /** Sample object index. */
606 uint8_t ft_type; /** Flow Table Type */
607 uint32_t ft_id; /** Flow Table Level */
608 uint32_t ratio; /** Sample Ratio */
609 uint64_t set_action; /** Restore reg_c0 value */
610 void *normal_path_tbl; /** Flow Table pointer */
611 struct mlx5_flow_sub_actions_idx sample_idx;
612 /**< Action index resources. */
613 struct mlx5_flow_sub_actions_list sample_act;
614 /**< Action resources. */
617 #define MLX5_MAX_DEST_NUM 2
619 /* Destination array action resource structure. */
620 struct mlx5_flow_dv_dest_array_resource {
621 struct mlx5_cache_entry entry; /**< Cache entry. */
622 uint32_t idx; /** Destination array action object index. */
623 uint8_t ft_type; /** Flow Table Type */
624 uint8_t num_of_dest; /**< Number of destination actions. */
625 struct rte_eth_dev *dev; /**< Device registers the action. */
626 void *action; /**< Pointer to the rdma core action. */
627 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
628 /**< Action index resources. */
629 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
630 /**< Action resources. */
633 /* PMD flow priority for tunnel */
634 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
635 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
638 /** Device flow handle structure for DV mode only. */
639 struct mlx5_flow_handle_dv {
641 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
642 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
643 /**< Pointer to modify header resource in cache. */
644 uint32_t rix_encap_decap;
645 /**< Index to encap/decap resource in cache. */
646 uint32_t rix_push_vlan;
647 /**< Index to push VLAN action resource in cache. */
649 /**< Index to the tag action. */
651 /**< Index to sample action resource in cache. */
652 uint32_t rix_dest_array;
653 /**< Index to destination array resource in cache. */
656 /** Device flow handle structure: used both for creating & destroying. */
657 struct mlx5_flow_handle {
658 SILIST_ENTRY(uint32_t)next;
659 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
660 /**< Index to next device flow handle. */
662 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
663 void *drv_flow; /**< pointer to driver flow object. */
664 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
665 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
666 uint32_t mark:1; /**< Metadate rxq mark flag. */
667 uint32_t fate_action:3; /**< Fate action type. */
669 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
670 uint32_t rix_jump; /**< Index to the jump action resource. */
671 uint32_t rix_port_id_action;
672 /**< Index to port ID action resource. */
674 /**< Generic value indicates the fate action. */
675 uint32_t rix_default_fate;
676 /**< Indicates default miss fate action. */
678 /**< Indicates shared RSS fate action. */
680 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
681 struct mlx5_flow_handle_dv dvh;
686 * Size for Verbs device flow handle structure only. Do not use the DV only
687 * structure in Verbs. No DV flows attributes will be accessed.
688 * Macro offsetof() could also be used here.
690 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
691 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
692 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
694 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
697 /** Device flow structure only for DV flow creation. */
698 struct mlx5_flow_dv_workspace {
699 uint32_t group; /**< The group index. */
700 uint32_t table_id; /**< Flow table identifier. */
701 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
702 int actions_n; /**< number of actions. */
703 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
704 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
705 /**< Pointer to encap/decap resource in cache. */
706 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
707 /**< Pointer to push VLAN action resource in cache. */
708 struct mlx5_flow_dv_tag_resource *tag_resource;
709 /**< pointer to the tag action. */
710 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
711 /**< Pointer to port ID action resource. */
712 struct mlx5_flow_dv_jump_tbl_resource *jump;
713 /**< Pointer to the jump action resource. */
714 struct mlx5_flow_dv_match_params value;
715 /**< Holds the value that the packet is compared to. */
716 struct mlx5_flow_dv_sample_resource *sample_res;
717 /**< Pointer to the sample action resource. */
718 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
719 /**< Pointer to the destination array resource. */
722 #ifdef HAVE_INFINIBAND_VERBS_H
724 * Maximal Verbs flow specifications & actions size.
725 * Some elements are mutually exclusive, but enough space should be allocated.
726 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
727 * 2. One tunnel header (exception: GRE + MPLS),
728 * SPEC length: GRE == tunnel.
729 * Actions: 1. 1 Mark OR Flag.
730 * 2. 1 Drop (if any).
731 * 3. No limitation for counters, but it makes no sense to support too
732 * many counters in a single device flow.
734 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
735 #define MLX5_VERBS_MAX_SPEC_SIZE \
737 (2 * (sizeof(struct ibv_flow_spec_eth) + \
738 sizeof(struct ibv_flow_spec_ipv6) + \
739 sizeof(struct ibv_flow_spec_tcp_udp)) + \
740 sizeof(struct ibv_flow_spec_gre) + \
741 sizeof(struct ibv_flow_spec_mpls)) \
744 #define MLX5_VERBS_MAX_SPEC_SIZE \
746 (2 * (sizeof(struct ibv_flow_spec_eth) + \
747 sizeof(struct ibv_flow_spec_ipv6) + \
748 sizeof(struct ibv_flow_spec_tcp_udp)) + \
749 sizeof(struct ibv_flow_spec_tunnel)) \
753 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
754 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
755 #define MLX5_VERBS_MAX_ACT_SIZE \
757 sizeof(struct ibv_flow_spec_action_tag) + \
758 sizeof(struct ibv_flow_spec_action_drop) + \
759 sizeof(struct ibv_flow_spec_counter_action) * 4 \
762 #define MLX5_VERBS_MAX_ACT_SIZE \
764 sizeof(struct ibv_flow_spec_action_tag) + \
765 sizeof(struct ibv_flow_spec_action_drop) \
769 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
770 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
772 /** Device flow structure only for Verbs flow creation. */
773 struct mlx5_flow_verbs_workspace {
774 unsigned int size; /**< Size of the attribute. */
775 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
776 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
777 /**< Specifications & actions buffer of verbs flow. */
779 #endif /* HAVE_INFINIBAND_VERBS_H */
781 #define MLX5_SCALE_FLOW_GROUP_BIT 0
782 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
784 /** Maximal number of device sub-flows supported. */
785 #define MLX5_NUM_MAX_DEV_FLOWS 32
787 /** Device flow structure. */
790 struct rte_flow *flow; /**< Pointer to the main flow. */
791 uint32_t flow_idx; /**< The memory pool index to the main flow. */
792 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
794 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
795 bool external; /**< true if the flow is created external to PMD. */
796 uint8_t ingress:1; /**< 1 if the flow is ingress. */
797 uint8_t skip_scale:2;
799 * Each Bit be set to 1 if Skip the scale the flow group with factor.
800 * If bit0 be set to 1, then skip the scale the original flow group;
801 * If bit1 be set to 1, then skip the scale the jump flow group if
802 * having jump action.
803 * 00: Enable scale in a flow, default value.
804 * 01: Skip scale the flow group with factor, enable scale the group
806 * 10: Enable scale the group with factor, skip scale the group of
808 * 11: Skip scale the table with factor both for flow group and jump
812 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
813 struct mlx5_flow_dv_workspace dv;
815 #ifdef HAVE_INFINIBAND_VERBS_H
816 struct mlx5_flow_verbs_workspace verbs;
819 struct mlx5_flow_handle *handle;
820 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
821 const struct mlx5_flow_tunnel *tunnel;
824 /* Flow meter state. */
825 #define MLX5_FLOW_METER_DISABLE 0
826 #define MLX5_FLOW_METER_ENABLE 1
828 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
829 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
831 #define MLX5_MAN_WIDTH 8
832 /* Legacy Meter parameter structure. */
833 struct mlx5_legacy_flow_meter {
834 struct mlx5_flow_meter_info fm;
835 /* Must be the first in struct. */
836 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
837 /**< Pointer to the next flow meter structure. */
839 /* Index to meter object. */
842 #define MLX5_MAX_TUNNELS 256
843 #define MLX5_TNL_MISS_RULE_PRIORITY 3
844 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
847 * When tunnel offload is active, all JUMP group ids are converted
848 * using the same method. That conversion is applied both to tunnel and
849 * regular rule types.
850 * Group ids used in tunnel rules are relative to it's tunnel (!).
851 * Application can create number of steer rules, using the same
852 * tunnel, with different group id in each rule.
853 * Each tunnel stores its groups internally in PMD tunnel object.
854 * Groups used in regular rules do not belong to any tunnel and are stored
858 struct mlx5_flow_tunnel {
859 LIST_ENTRY(mlx5_flow_tunnel) chain;
860 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
861 uint32_t tunnel_id; /** unique tunnel ID */
863 struct rte_flow_action action;
864 struct rte_flow_item item;
865 struct mlx5_hlist *groups; /** tunnel groups */
868 /** PMD tunnel related context */
869 struct mlx5_flow_tunnel_hub {
871 * Access to the list MUST be MT protected
873 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
874 /* protect access to the tunnels list */
876 struct mlx5_hlist *groups; /** non tunnel groups */
879 /* convert jump group to flow table ID in tunnel rules */
880 struct tunnel_tbl_entry {
881 struct mlx5_hlist_entry hash;
887 static inline uint32_t
888 tunnel_id_to_flow_tbl(uint32_t id)
890 return id | (1u << 16);
893 static inline uint32_t
894 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
896 return flow_tbl & ~(1u << 16);
899 union tunnel_tbl_key {
907 static inline struct mlx5_flow_tunnel_hub *
908 mlx5_tunnel_hub(struct rte_eth_dev *dev)
910 struct mlx5_priv *priv = dev->data->dev_private;
911 return priv->sh->tunnel_hub;
915 is_tunnel_offload_active(struct rte_eth_dev *dev)
917 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
918 struct mlx5_priv *priv = dev->data->dev_private;
919 return !!priv->config.dv_miss_info;
927 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
928 __rte_unused const struct rte_flow_attr *attr,
929 __rte_unused const struct rte_flow_item items[],
930 __rte_unused const struct rte_flow_action actions[])
932 return (items[0].type == (typeof(items[0].type))
933 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
937 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
938 __rte_unused const struct rte_flow_attr *attr,
939 __rte_unused const struct rte_flow_item items[],
940 __rte_unused const struct rte_flow_action actions[])
942 return (actions[0].type == (typeof(actions[0].type))
943 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
946 static inline const struct mlx5_flow_tunnel *
947 flow_actions_to_tunnel(const struct rte_flow_action actions[])
949 return actions[0].conf;
952 static inline const struct mlx5_flow_tunnel *
953 flow_items_to_tunnel(const struct rte_flow_item items[])
955 return items[0].spec;
958 /* Flow structure. */
960 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
961 uint32_t dev_handles;
962 /**< Device flow handles that are part of the flow. */
963 uint32_t drv_type:2; /**< Driver type. */
965 uint32_t meter:24; /**< Holds flow meter id. */
966 uint32_t rix_mreg_copy;
967 /**< Index to metadata register copy table resource. */
968 uint32_t counter; /**< Holds flow counter. */
969 uint32_t tunnel_id; /**< Tunnel id */
970 uint32_t age; /**< Holds ASO age bit index. */
971 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
975 * Define list of valid combinations of RX Hash fields
976 * (see enum ibv_rx_hash_fields).
978 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
979 #define MLX5_RSS_HASH_IPV4_TCP \
980 (MLX5_RSS_HASH_IPV4 | \
981 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
982 #define MLX5_RSS_HASH_IPV4_UDP \
983 (MLX5_RSS_HASH_IPV4 | \
984 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
985 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
986 #define MLX5_RSS_HASH_IPV6_TCP \
987 (MLX5_RSS_HASH_IPV6 | \
988 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
989 #define MLX5_RSS_HASH_IPV6_UDP \
990 (MLX5_RSS_HASH_IPV6 | \
991 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
992 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
993 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
994 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
995 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
996 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
997 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
998 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
999 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1000 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1001 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1002 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1003 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1004 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1005 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1006 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1007 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1008 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1009 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1010 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1011 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1012 #define MLX5_RSS_HASH_NONE 0ULL
1014 /* array of valid combinations of RX Hash fields for RSS */
1015 static const uint64_t mlx5_rss_hash_fields[] = {
1017 MLX5_RSS_HASH_IPV4_TCP,
1018 MLX5_RSS_HASH_IPV4_UDP,
1020 MLX5_RSS_HASH_IPV6_TCP,
1021 MLX5_RSS_HASH_IPV6_UDP,
1025 /* Shared RSS action structure */
1026 struct mlx5_shared_action_rss {
1027 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1028 uint32_t refcnt; /**< Atomically accessed refcnt. */
1029 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1030 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1031 struct mlx5_ind_table_obj *ind_tbl;
1032 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1033 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1034 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1035 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1038 struct rte_flow_action_handle {
1042 /* Thread specific flow workspace intermediate data. */
1043 struct mlx5_flow_workspace {
1044 /* If creating another flow in same thread, push new as stack. */
1045 struct mlx5_flow_workspace *prev;
1046 struct mlx5_flow_workspace *next;
1047 uint32_t inuse; /* can't create new flow with current. */
1048 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1049 struct mlx5_flow_rss_desc rss_desc;
1050 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1051 uint32_t flow_idx; /* Intermediate device flow index. */
1052 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1053 uint32_t skip_matcher_reg:1;
1054 /* Indicates if need to skip matcher register in translate. */
1057 struct mlx5_flow_split_info {
1059 /**< True if flow is created by request external to PMD. */
1060 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1061 uint32_t flow_idx; /**< This memory pool index to the flow. */
1062 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1063 uint64_t prefix_layers; /**< Prefix subflow layers. */
1064 uint32_t table_id; /**< Flow table identifier. */
1067 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1068 const struct rte_flow_attr *attr,
1069 const struct rte_flow_item items[],
1070 const struct rte_flow_action actions[],
1073 struct rte_flow_error *error);
1074 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1075 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1076 const struct rte_flow_item items[],
1077 const struct rte_flow_action actions[], struct rte_flow_error *error);
1078 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1079 struct mlx5_flow *dev_flow,
1080 const struct rte_flow_attr *attr,
1081 const struct rte_flow_item items[],
1082 const struct rte_flow_action actions[],
1083 struct rte_flow_error *error);
1084 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1085 struct rte_flow_error *error);
1086 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1087 struct rte_flow *flow);
1088 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1089 struct rte_flow *flow);
1090 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1091 struct rte_flow *flow,
1092 const struct rte_flow_action *actions,
1094 struct rte_flow_error *error);
1095 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1096 struct mlx5_flow_meter_info *fm,
1098 uint8_t domain_bitmap);
1099 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1100 struct mlx5_flow_meter_info *fm);
1101 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1102 typedef struct mlx5_flow_meter_sub_policy *
1103 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1104 (struct rte_eth_dev *dev,
1105 struct mlx5_flow_meter_policy *mtr_policy,
1106 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1107 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1108 (struct rte_eth_dev *dev);
1109 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1111 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1112 (struct rte_eth_dev *dev);
1113 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1115 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1117 bool clear, uint64_t *pkts,
1119 typedef int (*mlx5_flow_get_aged_flows_t)
1120 (struct rte_eth_dev *dev,
1122 uint32_t nb_contexts,
1123 struct rte_flow_error *error);
1124 typedef int (*mlx5_flow_action_validate_t)
1125 (struct rte_eth_dev *dev,
1126 const struct rte_flow_indir_action_conf *conf,
1127 const struct rte_flow_action *action,
1128 struct rte_flow_error *error);
1129 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1130 (struct rte_eth_dev *dev,
1131 const struct rte_flow_indir_action_conf *conf,
1132 const struct rte_flow_action *action,
1133 struct rte_flow_error *error);
1134 typedef int (*mlx5_flow_action_destroy_t)
1135 (struct rte_eth_dev *dev,
1136 struct rte_flow_action_handle *action,
1137 struct rte_flow_error *error);
1138 typedef int (*mlx5_flow_action_update_t)
1139 (struct rte_eth_dev *dev,
1140 struct rte_flow_action_handle *action,
1142 struct rte_flow_error *error);
1143 typedef int (*mlx5_flow_action_query_t)
1144 (struct rte_eth_dev *dev,
1145 const struct rte_flow_action_handle *action,
1147 struct rte_flow_error *error);
1148 typedef int (*mlx5_flow_sync_domain_t)
1149 (struct rte_eth_dev *dev,
1152 typedef int (*mlx5_flow_validate_mtr_acts_t)
1153 (struct rte_eth_dev *dev,
1154 const struct rte_flow_action *actions[RTE_COLORS],
1155 struct rte_flow_attr *attr,
1157 uint8_t *domain_bitmap,
1158 bool *is_def_policy,
1159 struct rte_mtr_error *error);
1160 typedef int (*mlx5_flow_create_mtr_acts_t)
1161 (struct rte_eth_dev *dev,
1162 struct mlx5_flow_meter_policy *mtr_policy,
1163 const struct rte_flow_action *actions[RTE_COLORS],
1164 struct rte_mtr_error *error);
1165 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1166 (struct rte_eth_dev *dev,
1167 struct mlx5_flow_meter_policy *mtr_policy);
1168 typedef int (*mlx5_flow_create_policy_rules_t)
1169 (struct rte_eth_dev *dev,
1170 struct mlx5_flow_meter_policy *mtr_policy);
1171 typedef void (*mlx5_flow_destroy_policy_rules_t)
1172 (struct rte_eth_dev *dev,
1173 struct mlx5_flow_meter_policy *mtr_policy);
1174 typedef int (*mlx5_flow_create_def_policy_t)
1175 (struct rte_eth_dev *dev);
1176 typedef void (*mlx5_flow_destroy_def_policy_t)
1177 (struct rte_eth_dev *dev);
1179 struct mlx5_flow_driver_ops {
1180 mlx5_flow_validate_t validate;
1181 mlx5_flow_prepare_t prepare;
1182 mlx5_flow_translate_t translate;
1183 mlx5_flow_apply_t apply;
1184 mlx5_flow_remove_t remove;
1185 mlx5_flow_destroy_t destroy;
1186 mlx5_flow_query_t query;
1187 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1188 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1189 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1190 mlx5_flow_mtr_alloc_t create_meter;
1191 mlx5_flow_mtr_free_t free_meter;
1192 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1193 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1194 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1195 mlx5_flow_create_policy_rules_t create_policy_rules;
1196 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1197 mlx5_flow_create_def_policy_t create_def_policy;
1198 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1199 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1200 mlx5_flow_counter_alloc_t counter_alloc;
1201 mlx5_flow_counter_free_t counter_free;
1202 mlx5_flow_counter_query_t counter_query;
1203 mlx5_flow_get_aged_flows_t get_aged_flows;
1204 mlx5_flow_action_validate_t action_validate;
1205 mlx5_flow_action_create_t action_create;
1206 mlx5_flow_action_destroy_t action_destroy;
1207 mlx5_flow_action_update_t action_update;
1208 mlx5_flow_action_query_t action_query;
1209 mlx5_flow_sync_domain_t sync_domain;
1214 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1216 struct flow_grp_info {
1217 uint64_t external:1;
1218 uint64_t transfer:1;
1219 uint64_t fdb_def_rule:1;
1220 /* force standard group translation */
1221 uint64_t std_tbl_fix:1;
1222 uint64_t skip_scale:2;
1226 tunnel_use_standard_attr_group_translate
1227 (struct rte_eth_dev *dev,
1228 const struct mlx5_flow_tunnel *tunnel,
1229 const struct rte_flow_attr *attr,
1230 const struct rte_flow_item items[],
1231 const struct rte_flow_action actions[])
1235 if (!is_tunnel_offload_active(dev))
1236 /* no tunnel offload API */
1240 * OvS will use jump to group 0 in tunnel steer rule.
1241 * If tunnel steer rule starts from group 0 (attr.group == 0)
1242 * that 0 group must be translated with standard method.
1243 * attr.group == 0 in tunnel match rule translated with tunnel
1246 verdict = !attr->group &&
1247 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1250 * non-tunnel group translation uses standard method for
1251 * root group only: attr.group == 0
1253 verdict = !attr->group;
1260 * Get DV flow aso meter by index.
1263 * Pointer to the Ethernet device structure.
1265 * mlx5 flow aso meter index in the container.
1267 * mlx5 flow aso meter pool in the container,
1270 * Pointer to the aso meter, NULL otherwise.
1272 static inline struct mlx5_aso_mtr *
1273 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1275 struct mlx5_aso_mtr_pool *pool;
1276 struct mlx5_aso_mtr_pools_mng *pools_mng =
1277 &priv->sh->mtrmng->pools_mng;
1279 /* Decrease to original index. */
1281 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1282 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1283 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1286 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1287 const struct mlx5_flow_tunnel *tunnel,
1288 uint32_t group, uint32_t *table,
1289 const struct flow_grp_info *flags,
1290 struct rte_flow_error *error);
1291 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1292 int tunnel, uint64_t layer_types,
1293 uint64_t hash_fields);
1294 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1295 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1296 uint32_t subpriority);
1297 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1298 const struct rte_flow_attr *attr);
1299 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1300 const struct rte_flow_attr *attr,
1301 uint32_t subpriority);
1302 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1303 enum mlx5_feature_name feature,
1305 struct rte_flow_error *error);
1306 const struct rte_flow_action *mlx5_flow_find_action
1307 (const struct rte_flow_action *actions,
1308 enum rte_flow_action_type action);
1309 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1310 const struct rte_flow_action *action,
1311 struct rte_flow_error *error);
1312 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1313 const struct rte_flow_attr *attr,
1314 struct rte_flow_error *error);
1315 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1316 const struct rte_flow_attr *attr,
1317 struct rte_flow_error *error);
1318 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1319 const struct rte_flow_attr *attr,
1320 struct rte_flow_error *error);
1321 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1322 uint64_t action_flags,
1323 const struct rte_flow_attr *attr,
1324 struct rte_flow_error *error);
1325 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1326 uint64_t action_flags,
1327 struct rte_eth_dev *dev,
1328 const struct rte_flow_attr *attr,
1329 struct rte_flow_error *error);
1330 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1331 uint64_t action_flags,
1332 struct rte_eth_dev *dev,
1333 const struct rte_flow_attr *attr,
1334 uint64_t item_flags,
1335 struct rte_flow_error *error);
1336 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1337 const struct rte_flow_attr *attr,
1338 struct rte_flow_error *error);
1339 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1340 const struct rte_flow_attr *attributes,
1341 struct rte_flow_error *error);
1342 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1343 const uint8_t *mask,
1344 const uint8_t *nic_mask,
1346 bool range_accepted,
1347 struct rte_flow_error *error);
1348 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1349 uint64_t item_flags, bool ext_vlan_sup,
1350 struct rte_flow_error *error);
1351 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1352 uint64_t item_flags,
1353 uint8_t target_protocol,
1354 struct rte_flow_error *error);
1355 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1356 uint64_t item_flags,
1357 const struct rte_flow_item *gre_item,
1358 struct rte_flow_error *error);
1359 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1360 uint64_t item_flags,
1362 uint16_t ether_type,
1363 const struct rte_flow_item_ipv4 *acc_mask,
1364 bool range_accepted,
1365 struct rte_flow_error *error);
1366 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1367 uint64_t item_flags,
1369 uint16_t ether_type,
1370 const struct rte_flow_item_ipv6 *acc_mask,
1371 struct rte_flow_error *error);
1372 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1373 const struct rte_flow_item *item,
1374 uint64_t item_flags,
1375 uint64_t prev_layer,
1376 struct rte_flow_error *error);
1377 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1378 uint64_t item_flags,
1379 uint8_t target_protocol,
1380 const struct rte_flow_item_tcp *flow_mask,
1381 struct rte_flow_error *error);
1382 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1383 uint64_t item_flags,
1384 uint8_t target_protocol,
1385 struct rte_flow_error *error);
1386 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1387 uint64_t item_flags,
1388 struct rte_eth_dev *dev,
1389 struct rte_flow_error *error);
1390 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1391 uint64_t item_flags,
1392 struct rte_flow_error *error);
1393 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1394 uint64_t item_flags,
1395 struct rte_eth_dev *dev,
1396 struct rte_flow_error *error);
1397 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1398 uint64_t item_flags,
1399 uint8_t target_protocol,
1400 struct rte_flow_error *error);
1401 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1402 uint64_t item_flags,
1403 uint8_t target_protocol,
1404 struct rte_flow_error *error);
1405 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1406 uint64_t item_flags,
1407 uint8_t target_protocol,
1408 struct rte_flow_error *error);
1409 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1410 uint64_t item_flags,
1411 struct rte_eth_dev *dev,
1412 struct rte_flow_error *error);
1413 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1415 const struct rte_flow_item *geneve_item,
1416 struct rte_eth_dev *dev,
1417 struct rte_flow_error *error);
1418 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1419 uint64_t item_flags,
1421 uint16_t ether_type,
1422 const struct rte_flow_item_ecpri *acc_mask,
1423 struct rte_flow_error *error);
1424 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1425 struct mlx5_flow_meter_info *fm,
1427 uint8_t domain_bitmap);
1428 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1429 struct mlx5_flow_meter_info *fm);
1430 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1431 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1432 (struct rte_eth_dev *dev,
1433 struct mlx5_flow_meter_policy *mtr_policy,
1434 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1435 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1436 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1437 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1438 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1440 /* Hash list callbacks for flow tables: */
1441 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1442 uint64_t key, void *entry_ctx);
1443 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1444 struct mlx5_hlist_entry *entry, uint64_t key,
1446 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1447 struct mlx5_hlist_entry *entry);
1448 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1449 uint32_t table_level, uint8_t egress, uint8_t transfer,
1450 bool external, const struct mlx5_flow_tunnel *tunnel,
1451 uint32_t group_id, uint8_t dummy,
1452 uint32_t table_id, struct rte_flow_error *error);
1454 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1455 uint64_t key, void *cb_ctx);
1456 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1457 struct mlx5_hlist_entry *entry, uint64_t key,
1459 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1460 struct mlx5_hlist_entry *entry);
1462 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1463 struct mlx5_hlist_entry *entry,
1464 uint64_t key, void *cb_ctx);
1465 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1466 uint64_t key, void *ctx);
1467 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1468 struct mlx5_hlist_entry *entry);
1470 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1471 uint64_t key, void *ctx);
1472 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1473 struct mlx5_hlist_entry *entry, uint64_t key,
1475 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1476 struct mlx5_hlist_entry *entry);
1478 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1479 struct mlx5_hlist_entry *entry,
1480 uint64_t key, void *cb_ctx);
1481 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1482 uint64_t key, void *cb_ctx);
1483 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1484 struct mlx5_hlist_entry *entry);
1486 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1487 struct mlx5_cache_entry *entry, void *ctx);
1488 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1489 struct mlx5_cache_entry *entry, void *ctx);
1490 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1491 struct mlx5_cache_entry *entry);
1493 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1494 struct mlx5_cache_entry *entry, void *cb_ctx);
1495 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1496 struct mlx5_cache_entry *entry, void *cb_ctx);
1497 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1498 struct mlx5_cache_entry *entry);
1500 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1501 struct mlx5_cache_entry *entry, void *cb_ctx);
1502 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1503 (struct mlx5_cache_list *list,
1504 struct mlx5_cache_entry *entry, void *cb_ctx);
1505 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1506 struct mlx5_cache_entry *entry);
1508 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1509 struct mlx5_cache_entry *entry, void *cb_ctx);
1510 struct mlx5_cache_entry *flow_dv_sample_create_cb
1511 (struct mlx5_cache_list *list,
1512 struct mlx5_cache_entry *entry, void *cb_ctx);
1513 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1514 struct mlx5_cache_entry *entry);
1516 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1517 struct mlx5_cache_entry *entry, void *cb_ctx);
1518 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1519 (struct mlx5_cache_list *list,
1520 struct mlx5_cache_entry *entry, void *cb_ctx);
1521 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1522 struct mlx5_cache_entry *entry);
1523 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1525 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1526 const struct rte_flow_item *item,
1527 struct rte_flow_error *error);
1528 void flow_release_workspace(void *data);
1529 int mlx5_flow_os_init_workspace_once(void);
1530 void *mlx5_flow_os_get_specific_workspace(void);
1531 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1532 void mlx5_flow_os_release_workspace(void);
1533 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1534 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1535 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1536 const struct rte_flow_action *actions[RTE_COLORS],
1537 struct rte_flow_attr *attr,
1539 uint8_t *domain_bitmap,
1540 bool *is_def_policy,
1541 struct rte_mtr_error *error);
1542 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1543 struct mlx5_flow_meter_policy *mtr_policy);
1544 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1545 struct mlx5_flow_meter_policy *mtr_policy,
1546 const struct rte_flow_action *actions[RTE_COLORS],
1547 struct rte_mtr_error *error);
1548 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1549 struct mlx5_flow_meter_policy *mtr_policy);
1550 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1551 struct mlx5_flow_meter_policy *mtr_policy);
1552 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1553 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1554 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1555 struct mlx5_flow_handle *dev_handle);
1556 #endif /* RTE_PMD_MLX5_FLOW_H_ */