1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* E-Switch Manager port, used for rte_flow_item_port_id. */
22 #define MLX5_PORT_ESW_MGR UINT32_MAX
24 /* Private rte flow items. */
25 enum mlx5_rte_flow_item_type {
26 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
28 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
29 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
30 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
33 /* Private (internal) rte flow actions. */
34 enum mlx5_rte_flow_action_type {
35 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
36 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
37 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
38 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
39 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
41 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
43 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
44 MLX5_RTE_FLOW_ACTION_TYPE_RSS,
47 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
50 MLX5_INDIRECT_ACTION_TYPE_RSS,
51 MLX5_INDIRECT_ACTION_TYPE_AGE,
52 MLX5_INDIRECT_ACTION_TYPE_COUNT,
53 MLX5_INDIRECT_ACTION_TYPE_CT,
56 /* Now, the maximal ports will be supported is 256, action number is 4M. */
57 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100
59 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22
60 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)
62 /* 30-31: type, 22-29: owner port, 0-21: index. */
63 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \
64 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \
65 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \
66 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index))
68 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \
69 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \
70 MLX5_INDIRECT_ACT_CT_OWNER_MASK)
72 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \
73 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))
75 /* Matches on selected register. */
76 struct mlx5_rte_flow_item_tag {
81 /* Modify selected register. */
82 struct mlx5_rte_flow_action_set_tag {
89 struct mlx5_flow_action_copy_mreg {
94 /* Matches on source queue. */
95 struct mlx5_rte_flow_item_tx_queue {
99 /* Feature name to allocate metadata register. */
100 enum mlx5_feature_name {
116 /* Default queue number. */
117 #define MLX5_RSSQ_DEFAULT_NUM 16
119 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
120 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
121 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
122 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
123 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
124 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
126 /* Pattern inner Layer bits. */
127 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
128 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
129 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
130 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
131 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
132 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
134 /* Pattern tunnel Layer bits. */
135 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
136 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
137 #define MLX5_FLOW_LAYER_GRE (1u << 14)
138 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
139 /* List of tunnel Layer bits continued below. */
141 /* General pattern items bits. */
142 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
143 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
144 #define MLX5_FLOW_ITEM_TAG (1u << 18)
145 #define MLX5_FLOW_ITEM_MARK (1u << 19)
147 /* Pattern MISC bits. */
148 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
149 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
150 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
152 /* Pattern tunnel Layer bits (continued). */
153 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
154 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
155 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
156 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
159 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
161 /* Pattern tunnel Layer bits (continued). */
162 #define MLX5_FLOW_LAYER_GTP (1u << 28)
164 /* Pattern eCPRI Layer bit. */
165 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
167 /* IPv6 Fragment Extension Header bit. */
168 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
169 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
171 /* Pattern tunnel Layer bits (continued). */
172 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
173 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
175 /* INTEGRITY item bits */
176 #define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34)
177 #define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35)
178 #define MLX5_FLOW_ITEM_INTEGRITY \
179 (MLX5_FLOW_ITEM_OUTER_INTEGRITY | MLX5_FLOW_ITEM_INNER_INTEGRITY)
181 /* Conntrack item. */
182 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36)
185 #define MLX5_FLOW_ITEM_OUTER_FLEX (UINT64_C(1) << 37)
186 #define MLX5_FLOW_ITEM_INNER_FLEX (UINT64_C(1) << 38)
187 #define MLX5_FLOW_ITEM_FLEX_TUNNEL (UINT64_C(1) << 39)
190 #define MLX5_FLOW_LAYER_OUTER_L3 \
191 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
192 #define MLX5_FLOW_LAYER_OUTER_L4 \
193 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
194 #define MLX5_FLOW_LAYER_OUTER \
195 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
196 MLX5_FLOW_LAYER_OUTER_L4)
199 #define MLX5_FLOW_LAYER_TUNNEL \
200 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
201 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
202 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
203 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP | \
204 MLX5_FLOW_ITEM_FLEX_TUNNEL)
207 #define MLX5_FLOW_LAYER_INNER_L3 \
208 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
209 #define MLX5_FLOW_LAYER_INNER_L4 \
210 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
211 #define MLX5_FLOW_LAYER_INNER \
212 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
213 MLX5_FLOW_LAYER_INNER_L4)
216 #define MLX5_FLOW_LAYER_L2 \
217 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
218 #define MLX5_FLOW_LAYER_L3_IPV4 \
219 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
220 #define MLX5_FLOW_LAYER_L3_IPV6 \
221 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
222 #define MLX5_FLOW_LAYER_L3 \
223 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
224 #define MLX5_FLOW_LAYER_L4 \
225 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
228 #define MLX5_FLOW_ACTION_DROP (1u << 0)
229 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
230 #define MLX5_FLOW_ACTION_RSS (1u << 2)
231 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
232 #define MLX5_FLOW_ACTION_MARK (1u << 4)
233 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
234 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
235 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
236 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
237 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
238 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
239 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
240 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
241 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
242 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
243 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
244 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
245 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
246 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
247 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
248 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
249 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
250 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
251 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
252 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
253 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
254 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
255 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
256 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
257 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
258 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
259 #define MLX5_FLOW_ACTION_METER (1ull << 31)
260 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
261 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
262 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
263 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
264 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
265 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
266 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
267 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
268 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
269 #define MLX5_FLOW_ACTION_CT (1ull << 41)
271 #define MLX5_FLOW_FATE_ACTIONS \
272 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
273 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
274 MLX5_FLOW_ACTION_DEFAULT_MISS | \
275 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
277 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
278 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
279 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
281 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
282 MLX5_FLOW_ACTION_SET_IPV4_DST | \
283 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
284 MLX5_FLOW_ACTION_SET_IPV6_DST | \
285 MLX5_FLOW_ACTION_SET_TP_SRC | \
286 MLX5_FLOW_ACTION_SET_TP_DST | \
287 MLX5_FLOW_ACTION_SET_TTL | \
288 MLX5_FLOW_ACTION_DEC_TTL | \
289 MLX5_FLOW_ACTION_SET_MAC_SRC | \
290 MLX5_FLOW_ACTION_SET_MAC_DST | \
291 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
292 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
293 MLX5_FLOW_ACTION_INC_TCP_ACK | \
294 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
295 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
296 MLX5_FLOW_ACTION_SET_TAG | \
297 MLX5_FLOW_ACTION_MARK_EXT | \
298 MLX5_FLOW_ACTION_SET_META | \
299 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
300 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
301 MLX5_FLOW_ACTION_MODIFY_FIELD)
303 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
304 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
306 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
309 #define IPPROTO_MPLS 137
312 /* UDP port number for MPLS */
313 #define MLX5_UDP_PORT_MPLS 6635
315 /* UDP port numbers for VxLAN. */
316 #define MLX5_UDP_PORT_VXLAN 4789
317 #define MLX5_UDP_PORT_VXLAN_GPE 4790
319 /* UDP port numbers for GENEVE. */
320 #define MLX5_UDP_PORT_GENEVE 6081
322 /* Lowest priority indicator. */
323 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
326 * Max priority for ingress\egress flow groups
327 * greater than 0 and for any transfer flow group.
328 * From user configation: 0 - 21843.
330 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
333 * Number of sub priorities.
334 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
335 * matching on the NIC (firmware dependent) L4 most have the higher priority
336 * followed by L3 and ending with L2.
338 #define MLX5_PRIORITY_MAP_L2 2
339 #define MLX5_PRIORITY_MAP_L3 1
340 #define MLX5_PRIORITY_MAP_L4 0
341 #define MLX5_PRIORITY_MAP_MAX 3
343 /* Valid layer type for IPV4 RSS. */
344 #define MLX5_IPV4_LAYER_TYPES \
345 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \
346 RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
347 RTE_ETH_RSS_NONFRAG_IPV4_OTHER)
349 /* IBV hash source bits for IPV4. */
350 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
352 /* Valid layer type for IPV6 RSS. */
353 #define MLX5_IPV6_LAYER_TYPES \
354 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
355 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | \
356 RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER)
358 /* IBV hash source bits for IPV6. */
359 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
361 /* IBV hash bits for L3 SRC. */
362 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
364 /* IBV hash bits for L3 DST. */
365 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
367 /* IBV hash bits for TCP. */
368 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
369 IBV_RX_HASH_DST_PORT_TCP)
371 /* IBV hash bits for UDP. */
372 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
373 IBV_RX_HASH_DST_PORT_UDP)
375 /* IBV hash bits for L4 SRC. */
376 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
377 IBV_RX_HASH_SRC_PORT_UDP)
379 /* IBV hash bits for L4 DST. */
380 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
381 IBV_RX_HASH_DST_PORT_UDP)
383 /* Geneve header first 16Bit */
384 #define MLX5_GENEVE_VER_MASK 0x3
385 #define MLX5_GENEVE_VER_SHIFT 14
386 #define MLX5_GENEVE_VER_VAL(a) \
387 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
388 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
389 #define MLX5_GENEVE_OPTLEN_SHIFT 8
390 #define MLX5_GENEVE_OPTLEN_VAL(a) \
391 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
392 #define MLX5_GENEVE_OAMF_MASK 0x1
393 #define MLX5_GENEVE_OAMF_SHIFT 7
394 #define MLX5_GENEVE_OAMF_VAL(a) \
395 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
396 #define MLX5_GENEVE_CRITO_MASK 0x1
397 #define MLX5_GENEVE_CRITO_SHIFT 6
398 #define MLX5_GENEVE_CRITO_VAL(a) \
399 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
400 #define MLX5_GENEVE_RSVD_MASK 0x3F
401 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
403 * The length of the Geneve options fields, expressed in four byte multiples,
404 * not including the eight byte fixed tunnel.
406 #define MLX5_GENEVE_OPT_LEN_0 14
407 #define MLX5_GENEVE_OPT_LEN_1 63
409 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
410 sizeof(struct rte_ipv4_hdr))
411 /* GTP extension header flag. */
412 #define MLX5_GTP_EXT_HEADER_FLAG 4
414 /* GTP extension header PDU type shift. */
415 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
417 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
418 #define MLX5_IPV4_FRAG_OFFSET_MASK \
419 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
421 /* Specific item's fields can accept a range of values (using spec and last). */
422 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
423 #define MLX5_ITEM_RANGE_ACCEPTED true
425 /* Software header modify action numbers of a flow. */
426 #define MLX5_ACT_NUM_MDF_IPV4 1
427 #define MLX5_ACT_NUM_MDF_IPV6 4
428 #define MLX5_ACT_NUM_MDF_MAC 2
429 #define MLX5_ACT_NUM_MDF_VID 1
430 #define MLX5_ACT_NUM_MDF_PORT 2
431 #define MLX5_ACT_NUM_MDF_TTL 1
432 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
433 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
434 #define MLX5_ACT_NUM_MDF_TCPACK 1
435 #define MLX5_ACT_NUM_SET_REG 1
436 #define MLX5_ACT_NUM_SET_TAG 1
437 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
438 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
439 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
440 #define MLX5_ACT_NUM_SET_DSCP 1
442 /* Maximum number of fields to modify in MODIFY_FIELD */
443 #define MLX5_ACT_MAX_MOD_FIELDS 5
445 /* Syndrome bits definition for connection tracking. */
446 #define MLX5_CT_SYNDROME_VALID (0x0 << 6)
447 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6)
448 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6)
449 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1)
450 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0)
452 enum mlx5_flow_drv_type {
455 MLX5_FLOW_TYPE_VERBS,
460 /* Fate action type. */
461 enum mlx5_flow_fate_type {
462 MLX5_FLOW_FATE_NONE, /* Egress flow. */
463 MLX5_FLOW_FATE_QUEUE,
465 MLX5_FLOW_FATE_PORT_ID,
467 MLX5_FLOW_FATE_DEFAULT_MISS,
468 MLX5_FLOW_FATE_SHARED_RSS,
473 /* Matcher PRM representation */
474 struct mlx5_flow_dv_match_params {
476 /**< Size of match value. Do NOT split size and key! */
477 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
478 /**< Matcher value. This value is used as the mask or as a key. */
481 /* Matcher structure. */
482 struct mlx5_flow_dv_matcher {
483 struct mlx5_list_entry entry; /**< Pointer to the next element. */
484 struct mlx5_flow_tbl_resource *tbl;
485 /**< Pointer to the table(group) the matcher associated with. */
486 void *matcher_object; /**< Pointer to DV matcher */
487 uint16_t crc; /**< CRC of key. */
488 uint16_t priority; /**< Priority of matcher. */
489 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
492 #define MLX5_ENCAP_MAX_LEN 132
494 /* Encap/decap resource structure. */
495 struct mlx5_flow_dv_encap_decap_resource {
496 struct mlx5_list_entry entry;
497 /* Pointer to next element. */
498 uint32_t refcnt; /**< Reference counter. */
500 /**< Encap/decap action object. */
501 uint8_t buf[MLX5_ENCAP_MAX_LEN];
503 uint8_t reformat_type;
505 uint64_t flags; /**< Flags for RDMA API. */
506 uint32_t idx; /**< Index for the index memory pool. */
509 /* Tag resource structure. */
510 struct mlx5_flow_dv_tag_resource {
511 struct mlx5_list_entry entry;
512 /**< hash list entry for tag resource, tag value as the key. */
514 /**< Tag action object. */
515 uint32_t refcnt; /**< Reference counter. */
516 uint32_t idx; /**< Index for the index memory pool. */
517 uint32_t tag_id; /**< Tag ID. */
520 /* Modify resource structure */
521 struct mlx5_flow_dv_modify_hdr_resource {
522 struct mlx5_list_entry entry;
523 void *action; /**< Modify header action object. */
525 /* Key area for hash list matching: */
526 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
527 uint8_t actions_num; /**< Number of modification actions. */
528 bool root; /**< Whether action is in root table. */
529 struct mlx5_modification_cmd actions[];
530 /**< Modification actions. */
533 /* Modify resource key of the hash organization. */
534 union mlx5_flow_modify_hdr_key {
536 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
537 uint32_t actions_num:5; /**< Number of modification actions. */
538 uint32_t group:19; /**< Flow group id. */
539 uint32_t cksum; /**< Actions check sum. */
541 uint64_t v64; /**< full 64bits value of key */
544 /* Jump action resource structure. */
545 struct mlx5_flow_dv_jump_tbl_resource {
546 void *action; /**< Pointer to the rdma core action. */
549 /* Port ID resource structure. */
550 struct mlx5_flow_dv_port_id_action_resource {
551 struct mlx5_list_entry entry;
552 void *action; /**< Action object. */
553 uint32_t port_id; /**< Port ID value. */
554 uint32_t idx; /**< Indexed pool memory index. */
557 /* Push VLAN action resource structure */
558 struct mlx5_flow_dv_push_vlan_action_resource {
559 struct mlx5_list_entry entry; /* Cache entry. */
560 void *action; /**< Action object. */
561 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
562 rte_be32_t vlan_tag; /**< VLAN tag value. */
563 uint32_t idx; /**< Indexed pool memory index. */
566 /* Metadata register copy table entry. */
567 struct mlx5_flow_mreg_copy_resource {
569 * Hash list entry for copy table.
570 * - Key is 32/64-bit MARK action ID.
571 * - MUST be the first entry.
573 struct mlx5_list_entry hlist_ent;
574 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
575 /* List entry for device flows. */
577 uint32_t rix_flow; /* Built flow for copy. */
581 /* Table tunnel parameter. */
582 struct mlx5_flow_tbl_tunnel_prm {
583 const struct mlx5_flow_tunnel *tunnel;
588 /* Table data structure of the hash organization. */
589 struct mlx5_flow_tbl_data_entry {
590 struct mlx5_list_entry entry;
591 /**< hash list entry, 64-bits key inside. */
592 struct mlx5_flow_tbl_resource tbl;
593 /**< flow table resource. */
594 struct mlx5_list *matchers;
595 /**< matchers' header associated with the flow table. */
596 struct mlx5_flow_dv_jump_tbl_resource jump;
597 /**< jump resource, at most one for each table created. */
598 uint32_t idx; /**< index for the indexed mempool. */
599 /**< tunnel offload */
600 const struct mlx5_flow_tunnel *tunnel;
603 uint32_t tunnel_offload:1; /* Tunnel offload table or not. */
604 uint32_t is_egress:1; /**< Egress table. */
605 uint32_t is_transfer:1; /**< Transfer table. */
606 uint32_t dummy:1; /**< DR table. */
607 uint32_t id:22; /**< Table ID. */
608 uint32_t reserve:5; /**< Reserved to future using. */
609 uint32_t level; /**< Table level. */
612 /* Sub rdma-core actions list. */
613 struct mlx5_flow_sub_actions_list {
614 uint32_t actions_num; /**< Number of sample actions. */
615 uint64_t action_flags;
616 void *dr_queue_action;
619 void *dr_port_id_action;
620 void *dr_encap_action;
621 void *dr_jump_action;
624 /* Sample sub-actions resource list. */
625 struct mlx5_flow_sub_actions_idx {
626 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
627 uint32_t rix_tag; /**< Index to the tag action. */
628 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
629 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
630 uint32_t rix_jump; /**< Index to the jump action resource. */
633 /* Sample action resource structure. */
634 struct mlx5_flow_dv_sample_resource {
635 struct mlx5_list_entry entry; /**< Cache entry. */
637 void *verbs_action; /**< Verbs sample action object. */
638 void **sub_actions; /**< Sample sub-action array. */
640 struct rte_eth_dev *dev; /**< Device registers the action. */
641 uint32_t idx; /** Sample object index. */
642 uint8_t ft_type; /** Flow Table Type */
643 uint32_t ft_id; /** Flow Table Level */
644 uint32_t ratio; /** Sample Ratio */
645 uint64_t set_action; /** Restore reg_c0 value */
646 void *normal_path_tbl; /** Flow Table pointer */
647 struct mlx5_flow_sub_actions_idx sample_idx;
648 /**< Action index resources. */
649 struct mlx5_flow_sub_actions_list sample_act;
650 /**< Action resources. */
653 #define MLX5_MAX_DEST_NUM 2
655 /* Destination array action resource structure. */
656 struct mlx5_flow_dv_dest_array_resource {
657 struct mlx5_list_entry entry; /**< Cache entry. */
658 uint32_t idx; /** Destination array action object index. */
659 uint8_t ft_type; /** Flow Table Type */
660 uint8_t num_of_dest; /**< Number of destination actions. */
661 struct rte_eth_dev *dev; /**< Device registers the action. */
662 void *action; /**< Pointer to the rdma core action. */
663 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
664 /**< Action index resources. */
665 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
666 /**< Action resources. */
669 /* PMD flow priority for tunnel */
670 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
671 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
674 /** Device flow handle structure for DV mode only. */
675 struct mlx5_flow_handle_dv {
677 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
678 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
679 /**< Pointer to modify header resource in cache. */
680 uint32_t rix_encap_decap;
681 /**< Index to encap/decap resource in cache. */
682 uint32_t rix_push_vlan;
683 /**< Index to push VLAN action resource in cache. */
685 /**< Index to the tag action. */
687 /**< Index to sample action resource in cache. */
688 uint32_t rix_dest_array;
689 /**< Index to destination array resource in cache. */
692 /** Device flow handle structure: used both for creating & destroying. */
693 struct mlx5_flow_handle {
694 SILIST_ENTRY(uint32_t)next;
695 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
696 /**< Index to next device flow handle. */
698 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
699 void *drv_flow; /**< pointer to driver flow object. */
700 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
701 uint32_t is_meter_flow_id:1; /**< Indicate if flow_id is for meter. */
702 uint32_t fate_action:3; /**< Fate action type. */
704 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
705 uint32_t rix_jump; /**< Index to the jump action resource. */
706 uint32_t rix_port_id_action;
707 /**< Index to port ID action resource. */
709 /**< Generic value indicates the fate action. */
710 uint32_t rix_default_fate;
711 /**< Indicates default miss fate action. */
713 /**< Indicates shared RSS fate action. */
715 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
716 struct mlx5_flow_handle_dv dvh;
718 uint8_t flex_item; /**< referenced Flex Item bitmask. */
722 * Size for Verbs device flow handle structure only. Do not use the DV only
723 * structure in Verbs. No DV flows attributes will be accessed.
724 * Macro offsetof() could also be used here.
726 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
727 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
728 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
730 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
733 /** Device flow structure only for DV flow creation. */
734 struct mlx5_flow_dv_workspace {
735 uint32_t group; /**< The group index. */
736 uint32_t table_id; /**< Flow table identifier. */
737 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
738 int actions_n; /**< number of actions. */
739 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
740 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
741 /**< Pointer to encap/decap resource in cache. */
742 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
743 /**< Pointer to push VLAN action resource in cache. */
744 struct mlx5_flow_dv_tag_resource *tag_resource;
745 /**< pointer to the tag action. */
746 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
747 /**< Pointer to port ID action resource. */
748 struct mlx5_flow_dv_jump_tbl_resource *jump;
749 /**< Pointer to the jump action resource. */
750 struct mlx5_flow_dv_match_params value;
751 /**< Holds the value that the packet is compared to. */
752 struct mlx5_flow_dv_sample_resource *sample_res;
753 /**< Pointer to the sample action resource. */
754 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
755 /**< Pointer to the destination array resource. */
758 #ifdef HAVE_INFINIBAND_VERBS_H
760 * Maximal Verbs flow specifications & actions size.
761 * Some elements are mutually exclusive, but enough space should be allocated.
762 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
763 * 2. One tunnel header (exception: GRE + MPLS),
764 * SPEC length: GRE == tunnel.
765 * Actions: 1. 1 Mark OR Flag.
766 * 2. 1 Drop (if any).
767 * 3. No limitation for counters, but it makes no sense to support too
768 * many counters in a single device flow.
770 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
771 #define MLX5_VERBS_MAX_SPEC_SIZE \
773 (2 * (sizeof(struct ibv_flow_spec_eth) + \
774 sizeof(struct ibv_flow_spec_ipv6) + \
775 sizeof(struct ibv_flow_spec_tcp_udp)) + \
776 sizeof(struct ibv_flow_spec_gre) + \
777 sizeof(struct ibv_flow_spec_mpls)) \
780 #define MLX5_VERBS_MAX_SPEC_SIZE \
782 (2 * (sizeof(struct ibv_flow_spec_eth) + \
783 sizeof(struct ibv_flow_spec_ipv6) + \
784 sizeof(struct ibv_flow_spec_tcp_udp)) + \
785 sizeof(struct ibv_flow_spec_tunnel)) \
789 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
790 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
791 #define MLX5_VERBS_MAX_ACT_SIZE \
793 sizeof(struct ibv_flow_spec_action_tag) + \
794 sizeof(struct ibv_flow_spec_action_drop) + \
795 sizeof(struct ibv_flow_spec_counter_action) * 4 \
798 #define MLX5_VERBS_MAX_ACT_SIZE \
800 sizeof(struct ibv_flow_spec_action_tag) + \
801 sizeof(struct ibv_flow_spec_action_drop) \
805 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
806 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
808 /** Device flow structure only for Verbs flow creation. */
809 struct mlx5_flow_verbs_workspace {
810 unsigned int size; /**< Size of the attribute. */
811 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
812 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
813 /**< Specifications & actions buffer of verbs flow. */
815 #endif /* HAVE_INFINIBAND_VERBS_H */
817 #define MLX5_SCALE_FLOW_GROUP_BIT 0
818 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
820 /** Maximal number of device sub-flows supported. */
821 #define MLX5_NUM_MAX_DEV_FLOWS 32
824 * tunnel offload rules type
826 enum mlx5_tof_rule_type {
827 MLX5_TUNNEL_OFFLOAD_NONE = 0,
828 MLX5_TUNNEL_OFFLOAD_SET_RULE,
829 MLX5_TUNNEL_OFFLOAD_MATCH_RULE,
830 MLX5_TUNNEL_OFFLOAD_MISS_RULE,
833 /** Device flow structure. */
836 struct rte_flow *flow; /**< Pointer to the main flow. */
837 uint32_t flow_idx; /**< The memory pool index to the main flow. */
838 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
840 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
841 bool external; /**< true if the flow is created external to PMD. */
842 uint8_t ingress:1; /**< 1 if the flow is ingress. */
843 uint8_t skip_scale:2;
845 * Each Bit be set to 1 if Skip the scale the flow group with factor.
846 * If bit0 be set to 1, then skip the scale the original flow group;
847 * If bit1 be set to 1, then skip the scale the jump flow group if
848 * having jump action.
849 * 00: Enable scale in a flow, default value.
850 * 01: Skip scale the flow group with factor, enable scale the group
852 * 10: Enable scale the group with factor, skip scale the group of
854 * 11: Skip scale the table with factor both for flow group and jump
858 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
859 struct mlx5_flow_dv_workspace dv;
861 #ifdef HAVE_INFINIBAND_VERBS_H
862 struct mlx5_flow_verbs_workspace verbs;
865 struct mlx5_flow_handle *handle;
866 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
867 const struct mlx5_flow_tunnel *tunnel;
868 enum mlx5_tof_rule_type tof_type;
871 /* Flow meter state. */
872 #define MLX5_FLOW_METER_DISABLE 0
873 #define MLX5_FLOW_METER_ENABLE 1
875 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
876 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
878 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
880 #define MLX5_MAN_WIDTH 8
881 /* Legacy Meter parameter structure. */
882 struct mlx5_legacy_flow_meter {
883 struct mlx5_flow_meter_info fm;
884 /* Must be the first in struct. */
885 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
886 /**< Pointer to the next flow meter structure. */
888 /* Index to meter object. */
891 #define MLX5_MAX_TUNNELS 256
892 #define MLX5_TNL_MISS_RULE_PRIORITY 3
893 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
896 * When tunnel offload is active, all JUMP group ids are converted
897 * using the same method. That conversion is applied both to tunnel and
898 * regular rule types.
899 * Group ids used in tunnel rules are relative to it's tunnel (!).
900 * Application can create number of steer rules, using the same
901 * tunnel, with different group id in each rule.
902 * Each tunnel stores its groups internally in PMD tunnel object.
903 * Groups used in regular rules do not belong to any tunnel and are stored
907 struct mlx5_flow_tunnel {
908 LIST_ENTRY(mlx5_flow_tunnel) chain;
909 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
910 uint32_t tunnel_id; /** unique tunnel ID */
912 struct rte_flow_action action;
913 struct rte_flow_item item;
914 struct mlx5_hlist *groups; /** tunnel groups */
917 /** PMD tunnel related context */
918 struct mlx5_flow_tunnel_hub {
920 * Access to the list MUST be MT protected
922 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
923 /* protect access to the tunnels list */
925 struct mlx5_hlist *groups; /** non tunnel groups */
928 /* convert jump group to flow table ID in tunnel rules */
929 struct tunnel_tbl_entry {
930 struct mlx5_list_entry hash;
936 static inline uint32_t
937 tunnel_id_to_flow_tbl(uint32_t id)
939 return id | (1u << 16);
942 static inline uint32_t
943 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
945 return flow_tbl & ~(1u << 16);
948 union tunnel_tbl_key {
956 static inline struct mlx5_flow_tunnel_hub *
957 mlx5_tunnel_hub(struct rte_eth_dev *dev)
959 struct mlx5_priv *priv = dev->data->dev_private;
960 return priv->sh->tunnel_hub;
964 is_tunnel_offload_active(const struct rte_eth_dev *dev)
966 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
967 const struct mlx5_priv *priv = dev->data->dev_private;
968 return !!priv->sh->config.dv_miss_info;
976 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type)
978 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE;
982 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type)
984 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE;
987 static inline const struct mlx5_flow_tunnel *
988 flow_actions_to_tunnel(const struct rte_flow_action actions[])
990 return actions[0].conf;
993 static inline const struct mlx5_flow_tunnel *
994 flow_items_to_tunnel(const struct rte_flow_item items[])
996 return items[0].spec;
999 /* Flow structure. */
1001 uint32_t dev_handles;
1002 /**< Device flow handles that are part of the flow. */
1004 uint32_t drv_type:2; /**< Driver type. */
1006 uint32_t meter:24; /**< Holds flow meter id. */
1007 uint32_t indirect_type:2; /**< Indirect action type. */
1008 uint32_t rix_mreg_copy;
1009 /**< Index to metadata register copy table resource. */
1010 uint32_t counter; /**< Holds flow counter. */
1011 uint32_t tunnel_id; /**< Tunnel id */
1013 uint32_t age; /**< Holds ASO age bit index. */
1014 uint32_t ct; /**< Holds ASO CT index. */
1016 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1019 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1021 /* HWS flow struct. */
1022 struct rte_flow_hw {
1023 uint32_t idx; /* Flow index from indexed pool. */
1024 uint32_t fate_type; /* Fate action type. */
1027 struct mlx5_hw_jump_action *jump;
1028 struct mlx5_hrxq *hrxq; /* TIR action. */
1030 struct rte_flow_template_table *table; /* The table flow allcated from. */
1031 struct mlx5dr_rule rule; /* HWS layer data struct. */
1034 /* rte flow action translate to DR action struct. */
1035 struct mlx5_action_construct_data {
1036 LIST_ENTRY(mlx5_action_construct_data) next;
1037 /* Ensure the action types are matched. */
1039 uint32_t idx; /* Data index. */
1040 uint16_t action_src; /* rte_flow_action src offset. */
1041 uint16_t action_dst; /* mlx5dr_rule_action dst offset. */
1044 /* encap src(item) offset. */
1046 /* encap dst data offset. */
1048 /* encap data len. */
1052 uint64_t types; /* RSS hash types. */
1053 uint32_t level; /* RSS level. */
1054 uint32_t idx; /* Shared action index. */
1059 /* Flow item template struct. */
1060 struct rte_flow_pattern_template {
1061 LIST_ENTRY(rte_flow_pattern_template) next;
1062 /* Template attributes. */
1063 struct rte_flow_pattern_template_attr attr;
1064 struct mlx5dr_match_template *mt; /* mlx5 match template. */
1065 uint64_t item_flags; /* Item layer flags. */
1066 uint32_t refcnt; /* Reference counter. */
1069 /* Flow action template struct. */
1070 struct rte_flow_actions_template {
1071 LIST_ENTRY(rte_flow_actions_template) next;
1072 /* Template attributes. */
1073 struct rte_flow_actions_template_attr attr;
1074 struct rte_flow_action *actions; /* Cached flow actions. */
1075 struct rte_flow_action *masks; /* Cached action masks.*/
1076 uint32_t refcnt; /* Reference counter. */
1079 /* Jump action struct. */
1080 struct mlx5_hw_jump_action {
1081 /* Action jump from root. */
1082 struct mlx5dr_action *root_action;
1083 /* HW steering jump action. */
1084 struct mlx5dr_action *hws_action;
1087 /* Encap decap action struct. */
1088 struct mlx5_hw_encap_decap_action {
1089 struct mlx5dr_action *action; /* Action object. */
1090 size_t data_size; /* Action metadata size. */
1091 uint8_t data[]; /* Action data. */
1094 /* The maximum actions support in the flow. */
1095 #define MLX5_HW_MAX_ACTS 16
1097 /* DR action set struct. */
1098 struct mlx5_hw_actions {
1099 /* Dynamic action list. */
1100 LIST_HEAD(act_list, mlx5_action_construct_data) act_list;
1101 struct mlx5_hw_jump_action *jump; /* Jump action. */
1102 struct mlx5_hrxq *tir; /* TIR action. */
1103 /* Encap/Decap action. */
1104 struct mlx5_hw_encap_decap_action *encap_decap;
1105 uint16_t encap_decap_pos; /* Encap/Decap action position. */
1106 uint32_t acts_num:4; /* Total action number. */
1107 uint32_t mark:1; /* Indicate the mark action. */
1108 /* Translated DR action array from action template. */
1109 struct mlx5dr_rule_action rule_acts[MLX5_HW_MAX_ACTS];
1112 /* mlx5 action template struct. */
1113 struct mlx5_hw_action_template {
1114 /* Action template pointer. */
1115 struct rte_flow_actions_template *action_template;
1116 struct mlx5_hw_actions acts; /* Template actions. */
1119 /* mlx5 flow group struct. */
1120 struct mlx5_flow_group {
1121 struct mlx5_list_entry entry;
1122 struct mlx5dr_table *tbl; /* HWS table object. */
1123 struct mlx5_hw_jump_action jump; /* Jump action. */
1124 enum mlx5dr_table_type type; /* Table type. */
1125 uint32_t group_id; /* Group id. */
1126 uint32_t idx; /* Group memory index. */
1130 #define MLX5_HW_TBL_MAX_ITEM_TEMPLATE 2
1131 #define MLX5_HW_TBL_MAX_ACTION_TEMPLATE 32
1133 struct rte_flow_template_table {
1134 LIST_ENTRY(rte_flow_template_table) next;
1135 struct mlx5_flow_group *grp; /* The group rte_flow_template_table uses. */
1136 struct mlx5dr_matcher *matcher; /* Template matcher. */
1137 /* Item templates bind to the table. */
1138 struct rte_flow_pattern_template *its[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
1139 /* Action templates bind to the table. */
1140 struct mlx5_hw_action_template ats[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
1141 struct mlx5_indexed_pool *flow; /* The table's flow ipool. */
1142 uint32_t type; /* Flow table type RX/TX/FDB. */
1143 uint8_t nb_item_templates; /* Item template number. */
1144 uint8_t nb_action_templates; /* Action template number. */
1145 uint32_t refcnt; /* Table reference counter. */
1151 * Define list of valid combinations of RX Hash fields
1152 * (see enum ibv_rx_hash_fields).
1154 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1155 #define MLX5_RSS_HASH_IPV4_TCP \
1156 (MLX5_RSS_HASH_IPV4 | \
1157 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1158 #define MLX5_RSS_HASH_IPV4_UDP \
1159 (MLX5_RSS_HASH_IPV4 | \
1160 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1161 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1162 #define MLX5_RSS_HASH_IPV6_TCP \
1163 (MLX5_RSS_HASH_IPV6 | \
1164 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1165 #define MLX5_RSS_HASH_IPV6_UDP \
1166 (MLX5_RSS_HASH_IPV6 | \
1167 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1168 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1169 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1170 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1171 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1172 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1173 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1174 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1175 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1176 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1177 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1178 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1179 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1180 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1181 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1182 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1183 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1184 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1185 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1186 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1187 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1188 #define MLX5_RSS_HASH_NONE 0ULL
1191 /* extract next protocol type from Ethernet & VLAN headers */
1192 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1193 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1194 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1195 (_prt) = rte_be_to_cpu_16((_prt)); \
1198 /* array of valid combinations of RX Hash fields for RSS */
1199 static const uint64_t mlx5_rss_hash_fields[] = {
1201 MLX5_RSS_HASH_IPV4_TCP,
1202 MLX5_RSS_HASH_IPV4_UDP,
1204 MLX5_RSS_HASH_IPV6_TCP,
1205 MLX5_RSS_HASH_IPV6_UDP,
1209 /* Shared RSS action structure */
1210 struct mlx5_shared_action_rss {
1211 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1212 uint32_t refcnt; /**< Atomically accessed refcnt. */
1213 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1214 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1215 struct mlx5_ind_table_obj *ind_tbl;
1216 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1217 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1218 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1219 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1222 struct rte_flow_action_handle {
1226 /* Thread specific flow workspace intermediate data. */
1227 struct mlx5_flow_workspace {
1228 /* If creating another flow in same thread, push new as stack. */
1229 struct mlx5_flow_workspace *prev;
1230 struct mlx5_flow_workspace *next;
1231 uint32_t inuse; /* can't create new flow with current. */
1232 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1233 struct mlx5_flow_rss_desc rss_desc;
1234 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1235 uint32_t flow_idx; /* Intermediate device flow index. */
1236 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1237 struct mlx5_flow_meter_policy *policy;
1238 /* The meter policy used by meter in flow. */
1239 struct mlx5_flow_meter_policy *final_policy;
1240 /* The final policy when meter policy is hierarchy. */
1241 uint32_t skip_matcher_reg:1;
1242 /* Indicates if need to skip matcher register in translate. */
1243 uint32_t mark:1; /* Indicates if flow contains mark action. */
1246 struct mlx5_flow_split_info {
1247 uint32_t external:1;
1248 /**< True if flow is created by request external to PMD. */
1249 uint32_t prefix_mark:1; /**< Prefix subflow mark flag. */
1250 uint32_t skip_scale:8; /**< Skip the scale the table with factor. */
1251 uint32_t flow_idx; /**< This memory pool index to the flow. */
1252 uint32_t table_id; /**< Flow table identifier. */
1253 uint64_t prefix_layers; /**< Prefix subflow layers. */
1256 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1257 const struct rte_flow_attr *attr,
1258 const struct rte_flow_item items[],
1259 const struct rte_flow_action actions[],
1262 struct rte_flow_error *error);
1263 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1264 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1265 const struct rte_flow_item items[],
1266 const struct rte_flow_action actions[], struct rte_flow_error *error);
1267 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1268 struct mlx5_flow *dev_flow,
1269 const struct rte_flow_attr *attr,
1270 const struct rte_flow_item items[],
1271 const struct rte_flow_action actions[],
1272 struct rte_flow_error *error);
1273 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1274 struct rte_flow_error *error);
1275 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1276 struct rte_flow *flow);
1277 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1278 struct rte_flow *flow);
1279 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1280 struct rte_flow *flow,
1281 const struct rte_flow_action *actions,
1283 struct rte_flow_error *error);
1284 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1285 struct mlx5_flow_meter_info *fm,
1287 uint8_t domain_bitmap);
1288 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1289 struct mlx5_flow_meter_info *fm);
1290 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1291 typedef struct mlx5_flow_meter_sub_policy *
1292 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1293 (struct rte_eth_dev *dev,
1294 struct mlx5_flow_meter_policy *mtr_policy,
1295 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1296 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t)
1297 (struct rte_eth_dev *dev,
1298 struct mlx5_flow_meter_info *fm,
1300 const struct rte_flow_item *item,
1301 struct rte_flow_error *error);
1302 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t)
1303 (struct rte_eth_dev *dev,
1304 struct mlx5_flow_meter_policy *mtr_policy);
1305 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1306 (struct rte_eth_dev *dev);
1307 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1309 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1310 (struct rte_eth_dev *dev);
1311 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1313 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1315 bool clear, uint64_t *pkts,
1316 uint64_t *bytes, void **action);
1317 typedef int (*mlx5_flow_get_aged_flows_t)
1318 (struct rte_eth_dev *dev,
1320 uint32_t nb_contexts,
1321 struct rte_flow_error *error);
1322 typedef int (*mlx5_flow_action_validate_t)
1323 (struct rte_eth_dev *dev,
1324 const struct rte_flow_indir_action_conf *conf,
1325 const struct rte_flow_action *action,
1326 struct rte_flow_error *error);
1327 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1328 (struct rte_eth_dev *dev,
1329 const struct rte_flow_indir_action_conf *conf,
1330 const struct rte_flow_action *action,
1331 struct rte_flow_error *error);
1332 typedef int (*mlx5_flow_action_destroy_t)
1333 (struct rte_eth_dev *dev,
1334 struct rte_flow_action_handle *action,
1335 struct rte_flow_error *error);
1336 typedef int (*mlx5_flow_action_update_t)
1337 (struct rte_eth_dev *dev,
1338 struct rte_flow_action_handle *action,
1340 struct rte_flow_error *error);
1341 typedef int (*mlx5_flow_action_query_t)
1342 (struct rte_eth_dev *dev,
1343 const struct rte_flow_action_handle *action,
1345 struct rte_flow_error *error);
1346 typedef int (*mlx5_flow_sync_domain_t)
1347 (struct rte_eth_dev *dev,
1350 typedef int (*mlx5_flow_validate_mtr_acts_t)
1351 (struct rte_eth_dev *dev,
1352 const struct rte_flow_action *actions[RTE_COLORS],
1353 struct rte_flow_attr *attr,
1355 uint8_t *domain_bitmap,
1356 uint8_t *policy_mode,
1357 struct rte_mtr_error *error);
1358 typedef int (*mlx5_flow_create_mtr_acts_t)
1359 (struct rte_eth_dev *dev,
1360 struct mlx5_flow_meter_policy *mtr_policy,
1361 const struct rte_flow_action *actions[RTE_COLORS],
1362 struct rte_mtr_error *error);
1363 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1364 (struct rte_eth_dev *dev,
1365 struct mlx5_flow_meter_policy *mtr_policy);
1366 typedef int (*mlx5_flow_create_policy_rules_t)
1367 (struct rte_eth_dev *dev,
1368 struct mlx5_flow_meter_policy *mtr_policy);
1369 typedef void (*mlx5_flow_destroy_policy_rules_t)
1370 (struct rte_eth_dev *dev,
1371 struct mlx5_flow_meter_policy *mtr_policy);
1372 typedef int (*mlx5_flow_create_def_policy_t)
1373 (struct rte_eth_dev *dev);
1374 typedef void (*mlx5_flow_destroy_def_policy_t)
1375 (struct rte_eth_dev *dev);
1376 typedef int (*mlx5_flow_discover_priorities_t)
1377 (struct rte_eth_dev *dev,
1378 const uint16_t *vprio, int vprio_n);
1379 typedef struct rte_flow_item_flex_handle *(*mlx5_flow_item_create_t)
1380 (struct rte_eth_dev *dev,
1381 const struct rte_flow_item_flex_conf *conf,
1382 struct rte_flow_error *error);
1383 typedef int (*mlx5_flow_item_release_t)
1384 (struct rte_eth_dev *dev,
1385 const struct rte_flow_item_flex_handle *handle,
1386 struct rte_flow_error *error);
1387 typedef int (*mlx5_flow_item_update_t)
1388 (struct rte_eth_dev *dev,
1389 const struct rte_flow_item_flex_handle *handle,
1390 const struct rte_flow_item_flex_conf *conf,
1391 struct rte_flow_error *error);
1392 typedef int (*mlx5_flow_info_get_t)
1393 (struct rte_eth_dev *dev,
1394 struct rte_flow_port_info *port_info,
1395 struct rte_flow_queue_info *queue_info,
1396 struct rte_flow_error *error);
1397 typedef int (*mlx5_flow_port_configure_t)
1398 (struct rte_eth_dev *dev,
1399 const struct rte_flow_port_attr *port_attr,
1401 const struct rte_flow_queue_attr *queue_attr[],
1402 struct rte_flow_error *err);
1403 typedef struct rte_flow_pattern_template *(*mlx5_flow_pattern_template_create_t)
1404 (struct rte_eth_dev *dev,
1405 const struct rte_flow_pattern_template_attr *attr,
1406 const struct rte_flow_item items[],
1407 struct rte_flow_error *error);
1408 typedef int (*mlx5_flow_pattern_template_destroy_t)
1409 (struct rte_eth_dev *dev,
1410 struct rte_flow_pattern_template *template,
1411 struct rte_flow_error *error);
1412 typedef struct rte_flow_actions_template *(*mlx5_flow_actions_template_create_t)
1413 (struct rte_eth_dev *dev,
1414 const struct rte_flow_actions_template_attr *attr,
1415 const struct rte_flow_action actions[],
1416 const struct rte_flow_action masks[],
1417 struct rte_flow_error *error);
1418 typedef int (*mlx5_flow_actions_template_destroy_t)
1419 (struct rte_eth_dev *dev,
1420 struct rte_flow_actions_template *template,
1421 struct rte_flow_error *error);
1422 typedef struct rte_flow_template_table *(*mlx5_flow_table_create_t)
1423 (struct rte_eth_dev *dev,
1424 const struct rte_flow_template_table_attr *attr,
1425 struct rte_flow_pattern_template *item_templates[],
1426 uint8_t nb_item_templates,
1427 struct rte_flow_actions_template *action_templates[],
1428 uint8_t nb_action_templates,
1429 struct rte_flow_error *error);
1430 typedef int (*mlx5_flow_table_destroy_t)
1431 (struct rte_eth_dev *dev,
1432 struct rte_flow_template_table *table,
1433 struct rte_flow_error *error);
1434 typedef struct rte_flow *(*mlx5_flow_async_flow_create_t)
1435 (struct rte_eth_dev *dev,
1437 const struct rte_flow_op_attr *attr,
1438 struct rte_flow_template_table *table,
1439 const struct rte_flow_item items[],
1440 uint8_t pattern_template_index,
1441 const struct rte_flow_action actions[],
1442 uint8_t action_template_index,
1444 struct rte_flow_error *error);
1445 typedef int (*mlx5_flow_async_flow_destroy_t)
1446 (struct rte_eth_dev *dev,
1448 const struct rte_flow_op_attr *attr,
1449 struct rte_flow *flow,
1451 struct rte_flow_error *error);
1452 typedef int (*mlx5_flow_pull_t)
1453 (struct rte_eth_dev *dev,
1455 struct rte_flow_op_result res[],
1457 struct rte_flow_error *error);
1458 typedef int (*mlx5_flow_push_t)
1459 (struct rte_eth_dev *dev,
1461 struct rte_flow_error *error);
1463 typedef struct rte_flow_action_handle *(*mlx5_flow_async_action_handle_create_t)
1464 (struct rte_eth_dev *dev,
1466 const struct rte_flow_op_attr *attr,
1467 const struct rte_flow_indir_action_conf *conf,
1468 const struct rte_flow_action *action,
1470 struct rte_flow_error *error);
1472 typedef int (*mlx5_flow_async_action_handle_update_t)
1473 (struct rte_eth_dev *dev,
1475 const struct rte_flow_op_attr *attr,
1476 struct rte_flow_action_handle *handle,
1479 struct rte_flow_error *error);
1481 typedef int (*mlx5_flow_async_action_handle_destroy_t)
1482 (struct rte_eth_dev *dev,
1484 const struct rte_flow_op_attr *attr,
1485 struct rte_flow_action_handle *handle,
1487 struct rte_flow_error *error);
1489 struct mlx5_flow_driver_ops {
1490 mlx5_flow_validate_t validate;
1491 mlx5_flow_prepare_t prepare;
1492 mlx5_flow_translate_t translate;
1493 mlx5_flow_apply_t apply;
1494 mlx5_flow_remove_t remove;
1495 mlx5_flow_destroy_t destroy;
1496 mlx5_flow_query_t query;
1497 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1498 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1499 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1500 mlx5_flow_mtr_alloc_t create_meter;
1501 mlx5_flow_mtr_free_t free_meter;
1502 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1503 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1504 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1505 mlx5_flow_create_policy_rules_t create_policy_rules;
1506 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1507 mlx5_flow_create_def_policy_t create_def_policy;
1508 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1509 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1510 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create;
1511 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq;
1512 mlx5_flow_counter_alloc_t counter_alloc;
1513 mlx5_flow_counter_free_t counter_free;
1514 mlx5_flow_counter_query_t counter_query;
1515 mlx5_flow_get_aged_flows_t get_aged_flows;
1516 mlx5_flow_action_validate_t action_validate;
1517 mlx5_flow_action_create_t action_create;
1518 mlx5_flow_action_destroy_t action_destroy;
1519 mlx5_flow_action_update_t action_update;
1520 mlx5_flow_action_query_t action_query;
1521 mlx5_flow_sync_domain_t sync_domain;
1522 mlx5_flow_discover_priorities_t discover_priorities;
1523 mlx5_flow_item_create_t item_create;
1524 mlx5_flow_item_release_t item_release;
1525 mlx5_flow_item_update_t item_update;
1526 mlx5_flow_info_get_t info_get;
1527 mlx5_flow_port_configure_t configure;
1528 mlx5_flow_pattern_template_create_t pattern_template_create;
1529 mlx5_flow_pattern_template_destroy_t pattern_template_destroy;
1530 mlx5_flow_actions_template_create_t actions_template_create;
1531 mlx5_flow_actions_template_destroy_t actions_template_destroy;
1532 mlx5_flow_table_create_t template_table_create;
1533 mlx5_flow_table_destroy_t template_table_destroy;
1534 mlx5_flow_async_flow_create_t async_flow_create;
1535 mlx5_flow_async_flow_destroy_t async_flow_destroy;
1536 mlx5_flow_pull_t pull;
1537 mlx5_flow_push_t push;
1538 mlx5_flow_async_action_handle_create_t async_action_create;
1539 mlx5_flow_async_action_handle_update_t async_action_update;
1540 mlx5_flow_async_action_handle_destroy_t async_action_destroy;
1545 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1547 struct flow_grp_info {
1548 uint64_t external:1;
1549 uint64_t transfer:1;
1550 uint64_t fdb_def_rule:1;
1551 /* force standard group translation */
1552 uint64_t std_tbl_fix:1;
1553 uint64_t skip_scale:2;
1557 tunnel_use_standard_attr_group_translate
1558 (const struct rte_eth_dev *dev,
1559 const struct rte_flow_attr *attr,
1560 const struct mlx5_flow_tunnel *tunnel,
1561 enum mlx5_tof_rule_type tof_rule_type)
1565 if (!is_tunnel_offload_active(dev))
1566 /* no tunnel offload API */
1570 * OvS will use jump to group 0 in tunnel steer rule.
1571 * If tunnel steer rule starts from group 0 (attr.group == 0)
1572 * that 0 group must be translated with standard method.
1573 * attr.group == 0 in tunnel match rule translated with tunnel
1576 verdict = !attr->group &&
1577 is_flow_tunnel_steer_rule(tof_rule_type);
1580 * non-tunnel group translation uses standard method for
1581 * root group only: attr.group == 0
1583 verdict = !attr->group;
1590 * Get DV flow aso meter by index.
1593 * Pointer to the Ethernet device structure.
1595 * mlx5 flow aso meter index in the container.
1597 * mlx5 flow aso meter pool in the container,
1600 * Pointer to the aso meter, NULL otherwise.
1602 static inline struct mlx5_aso_mtr *
1603 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1605 struct mlx5_aso_mtr_pool *pool;
1606 struct mlx5_aso_mtr_pools_mng *pools_mng =
1607 &priv->sh->mtrmng->pools_mng;
1609 /* Decrease to original index. */
1611 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1612 rte_rwlock_read_lock(&pools_mng->resize_mtrwl);
1613 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1614 rte_rwlock_read_unlock(&pools_mng->resize_mtrwl);
1615 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1618 static __rte_always_inline const struct rte_flow_item *
1619 mlx5_find_end_item(const struct rte_flow_item *item)
1621 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1625 static __rte_always_inline bool
1626 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1628 struct rte_flow_item_integrity test = *item;
1631 test.ipv4_csum_ok = 0;
1632 test.l4_csum_ok = 0;
1633 return (test.value == 0);
1637 * Get ASO CT action by device and index.
1640 * Pointer to the Ethernet device structure.
1642 * Index to the ASO CT action.
1645 * The specified ASO CT action pointer.
1647 static inline struct mlx5_aso_ct_action *
1648 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx)
1650 struct mlx5_priv *priv = dev->data->dev_private;
1651 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
1652 struct mlx5_aso_ct_pool *pool;
1655 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n);
1656 /* Bit operation AND could be used. */
1657 rte_rwlock_read_lock(&mng->resize_rwl);
1658 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL];
1659 rte_rwlock_read_unlock(&mng->resize_rwl);
1660 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];
1664 * Get ASO CT action by owner & index.
1667 * Pointer to the Ethernet device structure.
1669 * Index to the ASO CT action and owner port combination.
1672 * The specified ASO CT action pointer.
1674 static inline struct mlx5_aso_ct_action *
1675 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx)
1677 struct mlx5_priv *priv = dev->data->dev_private;
1678 struct mlx5_aso_ct_action *ct;
1679 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
1680 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
1682 if (owner == PORT_ID(priv)) {
1683 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
1685 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
1687 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
1688 if (dev->data->dev_started != 1)
1690 ct = flow_aso_ct_get_by_dev_idx(owndev, idx);
1691 if (ct->peer != PORT_ID(priv))
1697 static inline uint16_t
1698 mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
1700 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
1701 return RTE_ETHER_TYPE_TEB;
1702 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
1703 return RTE_ETHER_TYPE_IPV4;
1704 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
1705 return RTE_ETHER_TYPE_IPV6;
1706 else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
1707 return RTE_ETHER_TYPE_MPLS;
1711 int flow_hw_q_flow_flush(struct rte_eth_dev *dev,
1712 struct rte_flow_error *error);
1713 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1714 const struct mlx5_flow_tunnel *tunnel,
1715 uint32_t group, uint32_t *table,
1716 const struct flow_grp_info *flags,
1717 struct rte_flow_error *error);
1718 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1719 int tunnel, uint64_t layer_types,
1720 uint64_t hash_fields);
1721 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1722 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1723 uint32_t subpriority);
1724 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1725 const struct rte_flow_attr *attr);
1726 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1727 const struct rte_flow_attr *attr,
1728 uint32_t subpriority, bool external);
1729 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1730 enum mlx5_feature_name feature,
1732 struct rte_flow_error *error);
1733 const struct rte_flow_action *mlx5_flow_find_action
1734 (const struct rte_flow_action *actions,
1735 enum rte_flow_action_type action);
1736 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1737 const struct rte_flow_action *action,
1738 struct rte_flow_error *error);
1739 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1740 const struct rte_flow_attr *attr,
1741 struct rte_flow_error *error);
1742 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1743 const struct rte_flow_attr *attr,
1744 struct rte_flow_error *error);
1745 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1746 const struct rte_flow_attr *attr,
1747 struct rte_flow_error *error);
1748 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1749 uint64_t action_flags,
1750 const struct rte_flow_attr *attr,
1751 struct rte_flow_error *error);
1752 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1753 uint64_t action_flags,
1754 struct rte_eth_dev *dev,
1755 const struct rte_flow_attr *attr,
1756 struct rte_flow_error *error);
1757 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1758 uint64_t action_flags,
1759 struct rte_eth_dev *dev,
1760 const struct rte_flow_attr *attr,
1761 uint64_t item_flags,
1762 struct rte_flow_error *error);
1763 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1764 const struct rte_flow_attr *attr,
1765 struct rte_flow_error *error);
1766 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1767 const struct rte_flow_attr *attributes,
1768 struct rte_flow_error *error);
1769 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1770 const uint8_t *mask,
1771 const uint8_t *nic_mask,
1773 bool range_accepted,
1774 struct rte_flow_error *error);
1775 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1776 uint64_t item_flags, bool ext_vlan_sup,
1777 struct rte_flow_error *error);
1778 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1779 uint64_t item_flags,
1780 uint8_t target_protocol,
1781 struct rte_flow_error *error);
1782 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1783 uint64_t item_flags,
1784 const struct rte_flow_item *gre_item,
1785 struct rte_flow_error *error);
1786 int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
1787 const struct rte_flow_item *item,
1788 uint64_t item_flags,
1789 const struct rte_flow_attr *attr,
1790 const struct rte_flow_item *gre_item,
1791 struct rte_flow_error *error);
1792 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1793 uint64_t item_flags,
1795 uint16_t ether_type,
1796 const struct rte_flow_item_ipv4 *acc_mask,
1797 bool range_accepted,
1798 struct rte_flow_error *error);
1799 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1800 uint64_t item_flags,
1802 uint16_t ether_type,
1803 const struct rte_flow_item_ipv6 *acc_mask,
1804 struct rte_flow_error *error);
1805 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1806 const struct rte_flow_item *item,
1807 uint64_t item_flags,
1808 uint64_t prev_layer,
1809 struct rte_flow_error *error);
1810 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1811 uint64_t item_flags,
1812 uint8_t target_protocol,
1813 const struct rte_flow_item_tcp *flow_mask,
1814 struct rte_flow_error *error);
1815 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1816 uint64_t item_flags,
1817 uint8_t target_protocol,
1818 struct rte_flow_error *error);
1819 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1820 uint64_t item_flags,
1821 struct rte_eth_dev *dev,
1822 struct rte_flow_error *error);
1823 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev,
1825 const struct rte_flow_item *item,
1826 uint64_t item_flags,
1827 const struct rte_flow_attr *attr,
1828 struct rte_flow_error *error);
1829 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1830 uint64_t item_flags,
1831 struct rte_eth_dev *dev,
1832 struct rte_flow_error *error);
1833 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1834 uint64_t item_flags,
1835 uint8_t target_protocol,
1836 struct rte_flow_error *error);
1837 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1838 uint64_t item_flags,
1839 uint8_t target_protocol,
1840 struct rte_flow_error *error);
1841 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1842 uint64_t item_flags,
1843 uint8_t target_protocol,
1844 struct rte_flow_error *error);
1845 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1846 uint64_t item_flags,
1847 struct rte_eth_dev *dev,
1848 struct rte_flow_error *error);
1849 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1851 const struct rte_flow_item *geneve_item,
1852 struct rte_eth_dev *dev,
1853 struct rte_flow_error *error);
1854 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1855 uint64_t item_flags,
1857 uint16_t ether_type,
1858 const struct rte_flow_item_ecpri *acc_mask,
1859 struct rte_flow_error *error);
1860 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1861 struct mlx5_flow_meter_info *fm,
1863 uint8_t domain_bitmap);
1864 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1865 struct mlx5_flow_meter_info *fm);
1866 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1867 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1868 (struct rte_eth_dev *dev,
1869 struct mlx5_flow_meter_policy *mtr_policy,
1870 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1871 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
1872 struct mlx5_flow_meter_policy *mtr_policy);
1873 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1874 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev);
1875 int mlx5_action_handle_attach(struct rte_eth_dev *dev);
1876 int mlx5_action_handle_detach(struct rte_eth_dev *dev);
1877 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1878 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1879 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1881 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx);
1882 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1884 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1885 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx,
1886 struct mlx5_list_entry *oentry,
1888 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1889 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1890 uint32_t table_level, uint8_t egress, uint8_t transfer,
1891 bool external, const struct mlx5_flow_tunnel *tunnel,
1892 uint32_t group_id, uint8_t dummy,
1893 uint32_t table_id, struct rte_flow_error *error);
1895 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx);
1896 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1898 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1899 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx,
1900 struct mlx5_list_entry *oentry,
1902 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1904 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1906 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx);
1907 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1908 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx,
1909 struct mlx5_list_entry *oentry,
1911 void flow_dv_modify_clone_free_cb(void *tool_ctx,
1912 struct mlx5_list_entry *entry);
1914 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx);
1915 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1917 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1918 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx,
1919 struct mlx5_list_entry *entry,
1921 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1923 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1925 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx,
1927 void flow_dv_encap_decap_remove_cb(void *tool_ctx,
1928 struct mlx5_list_entry *entry);
1929 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx,
1930 struct mlx5_list_entry *entry,
1932 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx,
1933 struct mlx5_list_entry *entry);
1935 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1937 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx);
1938 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1940 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1942 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx);
1943 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1944 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx,
1945 struct mlx5_list_entry *entry, void *cb_ctx);
1946 void flow_dv_port_id_clone_free_cb(void *tool_ctx,
1947 struct mlx5_list_entry *entry);
1949 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1951 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx,
1953 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1954 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx,
1955 struct mlx5_list_entry *entry, void *cb_ctx);
1956 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx,
1957 struct mlx5_list_entry *entry);
1959 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1961 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx);
1962 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1963 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx,
1964 struct mlx5_list_entry *entry, void *cb_ctx);
1965 void flow_dv_sample_clone_free_cb(void *tool_ctx,
1966 struct mlx5_list_entry *entry);
1968 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1970 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx,
1972 void flow_dv_dest_array_remove_cb(void *tool_ctx,
1973 struct mlx5_list_entry *entry);
1974 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx,
1975 struct mlx5_list_entry *entry, void *cb_ctx);
1976 void flow_dv_dest_array_clone_free_cb(void *tool_ctx,
1977 struct mlx5_list_entry *entry);
1978 void flow_dv_hashfields_set(uint64_t item_flags,
1979 struct mlx5_flow_rss_desc *rss_desc,
1980 uint64_t *hash_fields);
1981 void flow_dv_action_rss_l34_hash_adjust(uint64_t rss_types,
1982 uint64_t *hash_field);
1983 uint32_t flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
1984 const uint64_t hash_fields);
1986 struct mlx5_list_entry *flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx);
1987 void flow_hw_grp_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1988 int flow_hw_grp_match_cb(void *tool_ctx,
1989 struct mlx5_list_entry *entry,
1991 struct mlx5_list_entry *flow_hw_grp_clone_cb(void *tool_ctx,
1992 struct mlx5_list_entry *oentry,
1994 void flow_hw_grp_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1996 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1998 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1999 const struct rte_flow_item *item,
2000 struct rte_flow_error *error);
2001 void flow_release_workspace(void *data);
2002 int mlx5_flow_os_init_workspace_once(void);
2003 void *mlx5_flow_os_get_specific_workspace(void);
2004 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
2005 void mlx5_flow_os_release_workspace(void);
2006 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
2007 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
2008 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
2009 const struct rte_flow_action *actions[RTE_COLORS],
2010 struct rte_flow_attr *attr,
2012 uint8_t *domain_bitmap,
2013 uint8_t *policy_mode,
2014 struct rte_mtr_error *error);
2015 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
2016 struct mlx5_flow_meter_policy *mtr_policy);
2017 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
2018 struct mlx5_flow_meter_policy *mtr_policy,
2019 const struct rte_flow_action *actions[RTE_COLORS],
2020 struct rte_mtr_error *error);
2021 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
2022 struct mlx5_flow_meter_policy *mtr_policy);
2023 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
2024 struct mlx5_flow_meter_policy *mtr_policy);
2025 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
2026 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
2027 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
2028 struct mlx5_flow_handle *dev_handle);
2029 const struct mlx5_flow_tunnel *
2030 mlx5_get_tof(const struct rte_flow_item *items,
2031 const struct rte_flow_action *actions,
2032 enum mlx5_tof_rule_type *rule_type);
2034 flow_hw_resource_release(struct rte_eth_dev *dev);
2035 int flow_dv_action_validate(struct rte_eth_dev *dev,
2036 const struct rte_flow_indir_action_conf *conf,
2037 const struct rte_flow_action *action,
2038 struct rte_flow_error *err);
2039 struct rte_flow_action_handle *flow_dv_action_create(struct rte_eth_dev *dev,
2040 const struct rte_flow_indir_action_conf *conf,
2041 const struct rte_flow_action *action,
2042 struct rte_flow_error *err);
2043 int flow_dv_action_destroy(struct rte_eth_dev *dev,
2044 struct rte_flow_action_handle *handle,
2045 struct rte_flow_error *error);
2046 int flow_dv_action_update(struct rte_eth_dev *dev,
2047 struct rte_flow_action_handle *handle,
2049 struct rte_flow_error *err);
2050 int flow_dv_action_query(struct rte_eth_dev *dev,
2051 const struct rte_flow_action_handle *handle,
2053 struct rte_flow_error *error);
2054 size_t flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type);
2055 int flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2056 size_t *size, struct rte_flow_error *error);
2057 #endif /* RTE_PMD_MLX5_FLOW_H_ */