1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
43 /* Private rte flow items. */
44 enum mlx5_rte_flow_item_type {
45 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
46 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
47 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
50 /* Private (internal) rte flow actions. */
51 enum mlx5_rte_flow_action_type {
52 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
53 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
54 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
57 /* Matches on selected register. */
58 struct mlx5_rte_flow_item_tag {
63 /* Modify selected register. */
64 struct mlx5_rte_flow_action_set_tag {
69 struct mlx5_flow_action_copy_mreg {
74 /* Matches on source queue. */
75 struct mlx5_rte_flow_item_tx_queue {
79 /* Pattern outer Layer bits. */
80 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
81 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
82 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
83 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
84 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
85 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
87 /* Pattern inner Layer bits. */
88 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
89 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
90 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
91 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
92 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
93 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
95 /* Pattern tunnel Layer bits. */
96 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
97 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
98 #define MLX5_FLOW_LAYER_GRE (1u << 14)
99 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
100 /* List of tunnel Layer bits continued below. */
102 /* General pattern items bits. */
103 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
104 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
105 #define MLX5_FLOW_ITEM_TAG (1u << 18)
107 /* Pattern MISC bits. */
108 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
109 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
110 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
112 /* Pattern tunnel Layer bits (continued). */
113 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
114 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
115 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
116 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
119 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
122 #define MLX5_FLOW_LAYER_OUTER_L3 \
123 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
124 #define MLX5_FLOW_LAYER_OUTER_L4 \
125 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
126 #define MLX5_FLOW_LAYER_OUTER \
127 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
128 MLX5_FLOW_LAYER_OUTER_L4)
130 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
131 #define MLX5_FLOW_LAYER_IPV4_LRO \
132 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
133 #define MLX5_FLOW_LAYER_IPV6_LRO \
134 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
137 #define MLX5_FLOW_LAYER_TUNNEL \
138 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
139 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
140 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
141 MLX5_FLOW_LAYER_GENEVE)
144 #define MLX5_FLOW_LAYER_INNER_L3 \
145 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
146 #define MLX5_FLOW_LAYER_INNER_L4 \
147 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
148 #define MLX5_FLOW_LAYER_INNER \
149 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
150 MLX5_FLOW_LAYER_INNER_L4)
153 #define MLX5_FLOW_LAYER_L2 \
154 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
155 #define MLX5_FLOW_LAYER_L3_IPV4 \
156 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
157 #define MLX5_FLOW_LAYER_L3_IPV6 \
158 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
159 #define MLX5_FLOW_LAYER_L3 \
160 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
161 #define MLX5_FLOW_LAYER_L4 \
162 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
165 #define MLX5_FLOW_ACTION_DROP (1u << 0)
166 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
167 #define MLX5_FLOW_ACTION_RSS (1u << 2)
168 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
169 #define MLX5_FLOW_ACTION_MARK (1u << 4)
170 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
171 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
172 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
173 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
174 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
175 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
176 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
177 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
178 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
179 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
180 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
181 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
182 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
183 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
184 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
185 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
186 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
187 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
188 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
189 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
190 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
191 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
192 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
193 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
194 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
195 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
196 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
197 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
199 #define MLX5_FLOW_FATE_ACTIONS \
200 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
201 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
203 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
204 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
205 MLX5_FLOW_ACTION_JUMP)
207 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
208 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
209 MLX5_FLOW_ACTION_RAW_ENCAP | \
210 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
212 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
213 MLX5_FLOW_ACTION_NVGRE_DECAP | \
214 MLX5_FLOW_ACTION_RAW_DECAP | \
215 MLX5_FLOW_ACTION_OF_POP_VLAN)
217 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
218 MLX5_FLOW_ACTION_SET_IPV4_DST | \
219 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
220 MLX5_FLOW_ACTION_SET_IPV6_DST | \
221 MLX5_FLOW_ACTION_SET_TP_SRC | \
222 MLX5_FLOW_ACTION_SET_TP_DST | \
223 MLX5_FLOW_ACTION_SET_TTL | \
224 MLX5_FLOW_ACTION_DEC_TTL | \
225 MLX5_FLOW_ACTION_SET_MAC_SRC | \
226 MLX5_FLOW_ACTION_SET_MAC_DST | \
227 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
228 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
229 MLX5_FLOW_ACTION_INC_TCP_ACK | \
230 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
231 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
232 MLX5_FLOW_ACTION_SET_TAG)
234 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
235 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
237 #define IPPROTO_MPLS 137
240 /* UDP port number for MPLS */
241 #define MLX5_UDP_PORT_MPLS 6635
243 /* UDP port numbers for VxLAN. */
244 #define MLX5_UDP_PORT_VXLAN 4789
245 #define MLX5_UDP_PORT_VXLAN_GPE 4790
247 /* UDP port numbers for GENEVE. */
248 #define MLX5_UDP_PORT_GENEVE 6081
250 /* Priority reserved for default flows. */
251 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
254 * Number of sub priorities.
255 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
256 * matching on the NIC (firmware dependent) L4 most have the higher priority
257 * followed by L3 and ending with L2.
259 #define MLX5_PRIORITY_MAP_L2 2
260 #define MLX5_PRIORITY_MAP_L3 1
261 #define MLX5_PRIORITY_MAP_L4 0
262 #define MLX5_PRIORITY_MAP_MAX 3
264 /* Valid layer type for IPV4 RSS. */
265 #define MLX5_IPV4_LAYER_TYPES \
266 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
267 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
268 ETH_RSS_NONFRAG_IPV4_OTHER)
270 /* IBV hash source bits for IPV4. */
271 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
273 /* Valid layer type for IPV6 RSS. */
274 #define MLX5_IPV6_LAYER_TYPES \
275 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
276 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
277 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
279 /* IBV hash source bits for IPV6. */
280 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
283 /* Geneve header first 16Bit */
284 #define MLX5_GENEVE_VER_MASK 0x3
285 #define MLX5_GENEVE_VER_SHIFT 14
286 #define MLX5_GENEVE_VER_VAL(a) \
287 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
288 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
289 #define MLX5_GENEVE_OPTLEN_SHIFT 7
290 #define MLX5_GENEVE_OPTLEN_VAL(a) \
291 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
292 #define MLX5_GENEVE_OAMF_MASK 0x1
293 #define MLX5_GENEVE_OAMF_SHIFT 7
294 #define MLX5_GENEVE_OAMF_VAL(a) \
295 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
296 #define MLX5_GENEVE_CRITO_MASK 0x1
297 #define MLX5_GENEVE_CRITO_SHIFT 6
298 #define MLX5_GENEVE_CRITO_VAL(a) \
299 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
300 #define MLX5_GENEVE_RSVD_MASK 0x3F
301 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
303 * The length of the Geneve options fields, expressed in four byte multiples,
304 * not including the eight byte fixed tunnel.
306 #define MLX5_GENEVE_OPT_LEN_0 14
307 #define MLX5_GENEVE_OPT_LEN_1 63
309 enum mlx5_flow_drv_type {
312 MLX5_FLOW_TYPE_VERBS,
316 /* Matcher PRM representation */
317 struct mlx5_flow_dv_match_params {
319 /**< Size of match value. Do NOT split size and key! */
320 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
321 /**< Matcher value. This value is used as the mask or as a key. */
324 /* Matcher structure. */
325 struct mlx5_flow_dv_matcher {
326 LIST_ENTRY(mlx5_flow_dv_matcher) next;
327 /* Pointer to the next element. */
328 rte_atomic32_t refcnt; /**< Reference counter. */
329 void *matcher_object; /**< Pointer to DV matcher */
330 uint16_t crc; /**< CRC of key. */
331 uint16_t priority; /**< Priority of matcher. */
332 uint8_t egress; /**< Egress matcher. */
333 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
334 uint32_t group; /**< The matcher group. */
335 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
338 #define MLX5_ENCAP_MAX_LEN 132
340 /* Encap/decap resource structure. */
341 struct mlx5_flow_dv_encap_decap_resource {
342 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
343 /* Pointer to next element. */
344 rte_atomic32_t refcnt; /**< Reference counter. */
346 /**< Verbs encap/decap action object. */
347 uint8_t buf[MLX5_ENCAP_MAX_LEN];
349 uint8_t reformat_type;
351 uint64_t flags; /**< Flags for RDMA API. */
354 /* Tag resource structure. */
355 struct mlx5_flow_dv_tag_resource {
356 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
357 /* Pointer to next element. */
358 rte_atomic32_t refcnt; /**< Reference counter. */
360 /**< Verbs tag action object. */
361 uint32_t tag; /**< the tag value. */
364 /* Number of modification commands. */
365 #define MLX5_MODIFY_NUM 8
367 /* Modify resource structure */
368 struct mlx5_flow_dv_modify_hdr_resource {
369 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
370 /* Pointer to next element. */
371 rte_atomic32_t refcnt; /**< Reference counter. */
372 struct ibv_flow_action *verbs_action;
373 /**< Verbs modify header action object. */
374 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
375 uint32_t actions_num; /**< Number of modification actions. */
376 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
377 /**< Modification actions. */
378 uint64_t flags; /**< Flags for RDMA API. */
381 /* Jump action resource structure. */
382 struct mlx5_flow_dv_jump_tbl_resource {
383 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
384 /* Pointer to next element. */
385 rte_atomic32_t refcnt; /**< Reference counter. */
386 void *action; /**< Pointer to the rdma core action. */
387 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
388 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
391 /* Port ID resource structure. */
392 struct mlx5_flow_dv_port_id_action_resource {
393 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
394 /* Pointer to next element. */
395 rte_atomic32_t refcnt; /**< Reference counter. */
397 /**< Verbs tag action object. */
398 uint32_t port_id; /**< Port ID value. */
401 /* Push VLAN action resource structure */
402 struct mlx5_flow_dv_push_vlan_action_resource {
403 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
404 /* Pointer to next element. */
405 rte_atomic32_t refcnt; /**< Reference counter. */
406 void *action; /**< Direct verbs action object. */
407 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
408 rte_be32_t vlan_tag; /**< VLAN tag value. */
412 * Max number of actions per DV flow.
413 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
414 * In rdma-core file providers/mlx5/verbs.c
416 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
418 /* DV flows structure. */
419 struct mlx5_flow_dv {
420 uint64_t hash_fields; /**< Fields that participate in the hash. */
421 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
423 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
424 struct mlx5_flow_dv_match_params value;
425 /**< Holds the value that the packet is compared to. */
426 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
427 /**< Pointer to encap/decap resource in cache. */
428 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
429 /**< Pointer to modify header resource in cache. */
430 struct ibv_flow *flow; /**< Installed flow. */
431 struct mlx5_flow_dv_jump_tbl_resource *jump;
432 /**< Pointer to the jump action resource. */
433 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
434 /**< Pointer to port ID action resource. */
435 struct mlx5_vf_vlan vf_vlan;
436 /**< Structure for VF VLAN workaround. */
437 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
438 /**< Pointer to push VLAN action resource in cache. */
439 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
440 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
443 int actions_n; /**< number of actions. */
446 /* Verbs specification header. */
447 struct ibv_spec_header {
448 enum ibv_flow_spec_type type;
452 /** Handles information leading to a drop fate. */
453 struct mlx5_flow_verbs {
454 LIST_ENTRY(mlx5_flow_verbs) next;
455 unsigned int size; /**< Size of the attribute. */
457 struct ibv_flow_attr *attr;
458 /**< Pointer to the Specification buffer. */
459 uint8_t *specs; /**< Pointer to the specifications. */
461 struct ibv_flow *flow; /**< Verbs flow pointer. */
462 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
463 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
464 struct mlx5_vf_vlan vf_vlan;
465 /**< Structure for VF VLAN workaround. */
468 /** Device flow structure. */
470 LIST_ENTRY(mlx5_flow) next;
471 struct rte_flow *flow; /**< Pointer to the main flow. */
473 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
475 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
477 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
478 struct mlx5_flow_dv dv;
480 struct mlx5_flow_verbs verbs;
482 bool external; /**< true if the flow is created external to PMD. */
485 /* Flow structure. */
487 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
488 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
489 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
490 struct mlx5_flow_dv_tag_resource *tag_resource;
491 /**< pointer to the tag action. */
492 struct rte_flow_action_rss rss;/**< RSS context. */
493 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
494 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
495 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
496 /**< Device flows that are part of the flow. */
497 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
498 uint8_t ingress; /**< 1 if the flow is ingress. */
499 uint32_t group; /**< The group index. */
500 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
501 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
504 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
505 const struct rte_flow_attr *attr,
506 const struct rte_flow_item items[],
507 const struct rte_flow_action actions[],
509 struct rte_flow_error *error);
510 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
511 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
512 const struct rte_flow_action actions[], struct rte_flow_error *error);
513 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
514 struct mlx5_flow *dev_flow,
515 const struct rte_flow_attr *attr,
516 const struct rte_flow_item items[],
517 const struct rte_flow_action actions[],
518 struct rte_flow_error *error);
519 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
520 struct rte_flow_error *error);
521 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
522 struct rte_flow *flow);
523 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
524 struct rte_flow *flow);
525 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
526 struct rte_flow *flow,
527 const struct rte_flow_action *actions,
529 struct rte_flow_error *error);
530 struct mlx5_flow_driver_ops {
531 mlx5_flow_validate_t validate;
532 mlx5_flow_prepare_t prepare;
533 mlx5_flow_translate_t translate;
534 mlx5_flow_apply_t apply;
535 mlx5_flow_remove_t remove;
536 mlx5_flow_destroy_t destroy;
537 mlx5_flow_query_t query;
540 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
541 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
542 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
543 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
547 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
548 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
549 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
550 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
552 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
553 bool external, uint32_t group, uint32_t *table,
554 struct rte_flow_error *error);
555 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
556 uint64_t layer_types,
557 uint64_t hash_fields);
558 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
559 uint32_t subpriority);
560 const struct rte_flow_action *mlx5_flow_find_action
561 (const struct rte_flow_action *actions,
562 enum rte_flow_action_type action);
563 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
564 const struct rte_flow_attr *attr,
565 struct rte_flow_error *error);
566 int mlx5_flow_validate_action_drop(uint64_t action_flags,
567 const struct rte_flow_attr *attr,
568 struct rte_flow_error *error);
569 int mlx5_flow_validate_action_flag(uint64_t action_flags,
570 const struct rte_flow_attr *attr,
571 struct rte_flow_error *error);
572 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
573 uint64_t action_flags,
574 const struct rte_flow_attr *attr,
575 struct rte_flow_error *error);
576 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
577 uint64_t action_flags,
578 struct rte_eth_dev *dev,
579 const struct rte_flow_attr *attr,
580 struct rte_flow_error *error);
581 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
582 uint64_t action_flags,
583 struct rte_eth_dev *dev,
584 const struct rte_flow_attr *attr,
586 struct rte_flow_error *error);
587 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
588 const struct rte_flow_attr *attributes,
589 struct rte_flow_error *error);
590 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
592 const uint8_t *nic_mask,
594 struct rte_flow_error *error);
595 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
597 struct rte_flow_error *error);
598 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
600 uint8_t target_protocol,
601 struct rte_flow_error *error);
602 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
604 const struct rte_flow_item *gre_item,
605 struct rte_flow_error *error);
606 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
610 const struct rte_flow_item_ipv4 *acc_mask,
611 struct rte_flow_error *error);
612 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
616 const struct rte_flow_item_ipv6 *acc_mask,
617 struct rte_flow_error *error);
618 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
619 const struct rte_flow_item *item,
622 struct rte_flow_error *error);
623 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
625 uint8_t target_protocol,
626 const struct rte_flow_item_tcp *flow_mask,
627 struct rte_flow_error *error);
628 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
630 uint8_t target_protocol,
631 struct rte_flow_error *error);
632 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
634 struct rte_eth_dev *dev,
635 struct rte_flow_error *error);
636 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
638 struct rte_flow_error *error);
639 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
641 struct rte_eth_dev *dev,
642 struct rte_flow_error *error);
643 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
645 uint8_t target_protocol,
646 struct rte_flow_error *error);
647 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
649 uint8_t target_protocol,
650 struct rte_flow_error *error);
651 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
653 uint8_t target_protocol,
654 struct rte_flow_error *error);
655 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
657 struct rte_eth_dev *dev,
658 struct rte_flow_error *error);
659 #endif /* RTE_PMD_MLX5_FLOW_H_ */