1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_atomic.h>
15 #include <rte_alarm.h>
18 #include <mlx5_glue.h>
23 /* Private rte flow items. */
24 enum mlx5_rte_flow_item_type {
25 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
26 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
27 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
28 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
29 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
32 /* Private (internal) rte flow actions. */
33 enum mlx5_rte_flow_action_type {
34 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
35 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
36 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
37 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
38 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
39 MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS,
40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
43 /* Matches on selected register. */
44 struct mlx5_rte_flow_item_tag {
49 /* Modify selected register. */
50 struct mlx5_rte_flow_action_set_tag {
55 struct mlx5_flow_action_copy_mreg {
60 /* Matches on source queue. */
61 struct mlx5_rte_flow_item_tx_queue {
65 /* Feature name to allocate metadata register. */
66 enum mlx5_feature_name {
79 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
80 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
81 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
82 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
83 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
84 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
86 /* Pattern inner Layer bits. */
87 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
88 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
89 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
90 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
91 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
92 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
94 /* Pattern tunnel Layer bits. */
95 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
96 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
97 #define MLX5_FLOW_LAYER_GRE (1u << 14)
98 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
99 /* List of tunnel Layer bits continued below. */
101 /* General pattern items bits. */
102 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
103 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
104 #define MLX5_FLOW_ITEM_TAG (1u << 18)
105 #define MLX5_FLOW_ITEM_MARK (1u << 19)
107 /* Pattern MISC bits. */
108 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
109 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
110 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
112 /* Pattern tunnel Layer bits (continued). */
113 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
114 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
115 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
116 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
119 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
121 /* Pattern tunnel Layer bits (continued). */
122 #define MLX5_FLOW_LAYER_GTP (1u << 28)
124 /* Pattern eCPRI Layer bit. */
125 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
127 /* IPv6 Fragment Extension Header bit. */
128 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
129 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
132 #define MLX5_FLOW_LAYER_OUTER_L3 \
133 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
134 #define MLX5_FLOW_LAYER_OUTER_L4 \
135 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
136 #define MLX5_FLOW_LAYER_OUTER \
137 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
138 MLX5_FLOW_LAYER_OUTER_L4)
141 #define MLX5_FLOW_LAYER_TUNNEL \
142 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
143 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
144 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
145 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
148 #define MLX5_FLOW_LAYER_INNER_L3 \
149 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
150 #define MLX5_FLOW_LAYER_INNER_L4 \
151 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
152 #define MLX5_FLOW_LAYER_INNER \
153 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
154 MLX5_FLOW_LAYER_INNER_L4)
157 #define MLX5_FLOW_LAYER_L2 \
158 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
159 #define MLX5_FLOW_LAYER_L3_IPV4 \
160 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
161 #define MLX5_FLOW_LAYER_L3_IPV6 \
162 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
163 #define MLX5_FLOW_LAYER_L3 \
164 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
165 #define MLX5_FLOW_LAYER_L4 \
166 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
169 #define MLX5_FLOW_ACTION_DROP (1u << 0)
170 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
171 #define MLX5_FLOW_ACTION_RSS (1u << 2)
172 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
173 #define MLX5_FLOW_ACTION_MARK (1u << 4)
174 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
175 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
176 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
177 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
178 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
179 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
180 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
181 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
182 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
183 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
184 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
185 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
186 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
187 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
188 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
189 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
190 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
191 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
192 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
193 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
194 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
195 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
196 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
197 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
198 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
199 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
200 #define MLX5_FLOW_ACTION_METER (1ull << 31)
201 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
202 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
203 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
204 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
205 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
206 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
207 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
209 #define MLX5_FLOW_FATE_ACTIONS \
210 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
211 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
212 MLX5_FLOW_ACTION_DEFAULT_MISS)
214 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
215 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
216 MLX5_FLOW_ACTION_JUMP)
219 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
220 MLX5_FLOW_ACTION_SET_IPV4_DST | \
221 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
222 MLX5_FLOW_ACTION_SET_IPV6_DST | \
223 MLX5_FLOW_ACTION_SET_TP_SRC | \
224 MLX5_FLOW_ACTION_SET_TP_DST | \
225 MLX5_FLOW_ACTION_SET_TTL | \
226 MLX5_FLOW_ACTION_DEC_TTL | \
227 MLX5_FLOW_ACTION_SET_MAC_SRC | \
228 MLX5_FLOW_ACTION_SET_MAC_DST | \
229 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
230 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
231 MLX5_FLOW_ACTION_INC_TCP_ACK | \
232 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
233 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
234 MLX5_FLOW_ACTION_SET_TAG | \
235 MLX5_FLOW_ACTION_MARK_EXT | \
236 MLX5_FLOW_ACTION_SET_META | \
237 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
238 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
240 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
241 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
243 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
246 #define IPPROTO_MPLS 137
249 /* UDP port number for MPLS */
250 #define MLX5_UDP_PORT_MPLS 6635
252 /* UDP port numbers for VxLAN. */
253 #define MLX5_UDP_PORT_VXLAN 4789
254 #define MLX5_UDP_PORT_VXLAN_GPE 4790
256 /* UDP port numbers for GENEVE. */
257 #define MLX5_UDP_PORT_GENEVE 6081
259 /* Priority reserved for default flows. */
260 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
263 * Number of sub priorities.
264 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
265 * matching on the NIC (firmware dependent) L4 most have the higher priority
266 * followed by L3 and ending with L2.
268 #define MLX5_PRIORITY_MAP_L2 2
269 #define MLX5_PRIORITY_MAP_L3 1
270 #define MLX5_PRIORITY_MAP_L4 0
271 #define MLX5_PRIORITY_MAP_MAX 3
273 /* Valid layer type for IPV4 RSS. */
274 #define MLX5_IPV4_LAYER_TYPES \
275 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
276 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
277 ETH_RSS_NONFRAG_IPV4_OTHER)
279 /* IBV hash source bits for IPV4. */
280 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
282 /* Valid layer type for IPV6 RSS. */
283 #define MLX5_IPV6_LAYER_TYPES \
284 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
285 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
286 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
288 /* IBV hash source bits for IPV6. */
289 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
291 /* IBV hash bits for L3 SRC. */
292 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
294 /* IBV hash bits for L3 DST. */
295 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
297 /* IBV hash bits for TCP. */
298 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
299 IBV_RX_HASH_DST_PORT_TCP)
301 /* IBV hash bits for UDP. */
302 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
303 IBV_RX_HASH_DST_PORT_UDP)
305 /* IBV hash bits for L4 SRC. */
306 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
307 IBV_RX_HASH_SRC_PORT_UDP)
309 /* IBV hash bits for L4 DST. */
310 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
311 IBV_RX_HASH_DST_PORT_UDP)
313 /* Geneve header first 16Bit */
314 #define MLX5_GENEVE_VER_MASK 0x3
315 #define MLX5_GENEVE_VER_SHIFT 14
316 #define MLX5_GENEVE_VER_VAL(a) \
317 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
318 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
319 #define MLX5_GENEVE_OPTLEN_SHIFT 7
320 #define MLX5_GENEVE_OPTLEN_VAL(a) \
321 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
322 #define MLX5_GENEVE_OAMF_MASK 0x1
323 #define MLX5_GENEVE_OAMF_SHIFT 7
324 #define MLX5_GENEVE_OAMF_VAL(a) \
325 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
326 #define MLX5_GENEVE_CRITO_MASK 0x1
327 #define MLX5_GENEVE_CRITO_SHIFT 6
328 #define MLX5_GENEVE_CRITO_VAL(a) \
329 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
330 #define MLX5_GENEVE_RSVD_MASK 0x3F
331 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
333 * The length of the Geneve options fields, expressed in four byte multiples,
334 * not including the eight byte fixed tunnel.
336 #define MLX5_GENEVE_OPT_LEN_0 14
337 #define MLX5_GENEVE_OPT_LEN_1 63
339 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
340 sizeof(struct rte_flow_item_ipv4))
342 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
343 #define MLX5_IPV4_FRAG_OFFSET_MASK \
344 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
346 /* Specific item's fields can accept a range of values (using spec and last). */
347 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
348 #define MLX5_ITEM_RANGE_ACCEPTED true
350 /* Software header modify action numbers of a flow. */
351 #define MLX5_ACT_NUM_MDF_IPV4 1
352 #define MLX5_ACT_NUM_MDF_IPV6 4
353 #define MLX5_ACT_NUM_MDF_MAC 2
354 #define MLX5_ACT_NUM_MDF_VID 1
355 #define MLX5_ACT_NUM_MDF_PORT 2
356 #define MLX5_ACT_NUM_MDF_TTL 1
357 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
358 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
359 #define MLX5_ACT_NUM_MDF_TCPACK 1
360 #define MLX5_ACT_NUM_SET_REG 1
361 #define MLX5_ACT_NUM_SET_TAG 1
362 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
363 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
364 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
365 #define MLX5_ACT_NUM_SET_DSCP 1
367 enum mlx5_flow_drv_type {
370 MLX5_FLOW_TYPE_VERBS,
374 /* Fate action type. */
375 enum mlx5_flow_fate_type {
376 MLX5_FLOW_FATE_NONE, /* Egress flow. */
377 MLX5_FLOW_FATE_QUEUE,
379 MLX5_FLOW_FATE_PORT_ID,
381 MLX5_FLOW_FATE_DEFAULT_MISS,
385 /* Matcher PRM representation */
386 struct mlx5_flow_dv_match_params {
388 /**< Size of match value. Do NOT split size and key! */
389 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
390 /**< Matcher value. This value is used as the mask or as a key. */
393 /* Matcher structure. */
394 struct mlx5_flow_dv_matcher {
395 LIST_ENTRY(mlx5_flow_dv_matcher) next;
396 /**< Pointer to the next element. */
397 struct mlx5_flow_tbl_resource *tbl;
398 /**< Pointer to the table(group) the matcher associated with. */
399 rte_atomic32_t refcnt; /**< Reference counter. */
400 void *matcher_object; /**< Pointer to DV matcher */
401 uint16_t crc; /**< CRC of key. */
402 uint16_t priority; /**< Priority of matcher. */
403 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
406 #define MLX5_ENCAP_MAX_LEN 132
408 /* Encap/decap resource key of the hash organization. */
409 union mlx5_flow_encap_decap_key {
411 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
412 uint32_t refmt_type:8; /**< Header reformat type. */
413 uint32_t buf_size:8; /**< Encap buf size. */
414 uint32_t table_level:8; /**< Root table or not. */
415 uint32_t cksum; /**< Encap buf check sum. */
417 uint64_t v64; /**< full 64bits value of key */
420 /* Encap/decap resource structure. */
421 struct mlx5_flow_dv_encap_decap_resource {
422 struct mlx5_hlist_entry entry;
423 /* Pointer to next element. */
424 rte_atomic32_t refcnt; /**< Reference counter. */
426 /**< Encap/decap action object. */
427 uint8_t buf[MLX5_ENCAP_MAX_LEN];
429 uint8_t reformat_type;
431 uint64_t flags; /**< Flags for RDMA API. */
432 uint32_t idx; /**< Index for the index memory pool. */
435 /* Tag resource structure. */
436 struct mlx5_flow_dv_tag_resource {
437 struct mlx5_hlist_entry entry;
438 /**< hash list entry for tag resource, tag value as the key. */
440 /**< Tag action object. */
441 rte_atomic32_t refcnt; /**< Reference counter. */
442 uint32_t idx; /**< Index for the index memory pool. */
446 * Number of modification commands.
447 * The maximal actions amount in FW is some constant, and it is 16 in the
448 * latest releases. In some old releases, it will be limited to 8.
449 * Since there is no interface to query the capacity, the maximal value should
450 * be used to allow PMD to create the flow. The validation will be done in the
451 * lower driver layer or FW. A failure will be returned if exceeds the maximal
452 * supported actions number on the root table.
453 * On non-root tables, there is no limitation, but 32 is enough right now.
455 #define MLX5_MAX_MODIFY_NUM 32
456 #define MLX5_ROOT_TBL_MODIFY_NUM 16
458 /* Modify resource structure */
459 struct mlx5_flow_dv_modify_hdr_resource {
460 struct mlx5_hlist_entry entry;
461 /* Pointer to next element. */
462 rte_atomic32_t refcnt; /**< Reference counter. */
464 /**< Modify header action object. */
465 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
466 uint32_t actions_num; /**< Number of modification actions. */
467 uint64_t flags; /**< Flags for RDMA API. */
468 struct mlx5_modification_cmd actions[];
469 /**< Modification actions. */
472 /* Modify resource key of the hash organization. */
473 union mlx5_flow_modify_hdr_key {
475 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
476 uint32_t actions_num:5; /**< Number of modification actions. */
477 uint32_t group:19; /**< Flow group id. */
478 uint32_t cksum; /**< Actions check sum. */
480 uint64_t v64; /**< full 64bits value of key */
483 /* Jump action resource structure. */
484 struct mlx5_flow_dv_jump_tbl_resource {
485 rte_atomic32_t refcnt; /**< Reference counter. */
486 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
487 void *action; /**< Pointer to the rdma core action. */
490 /* Port ID resource structure. */
491 struct mlx5_flow_dv_port_id_action_resource {
492 ILIST_ENTRY(uint32_t)next;
493 /* Pointer to next element. */
494 rte_atomic32_t refcnt; /**< Reference counter. */
496 /**< Action object. */
497 uint32_t port_id; /**< Port ID value. */
500 /* Push VLAN action resource structure */
501 struct mlx5_flow_dv_push_vlan_action_resource {
502 ILIST_ENTRY(uint32_t)next;
503 /* Pointer to next element. */
504 rte_atomic32_t refcnt; /**< Reference counter. */
505 void *action; /**< Action object. */
506 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
507 rte_be32_t vlan_tag; /**< VLAN tag value. */
510 /* Metadata register copy table entry. */
511 struct mlx5_flow_mreg_copy_resource {
513 * Hash list entry for copy table.
514 * - Key is 32/64-bit MARK action ID.
515 * - MUST be the first entry.
517 struct mlx5_hlist_entry hlist_ent;
518 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
519 /* List entry for device flows. */
520 uint32_t refcnt; /* Reference counter. */
521 uint32_t appcnt; /* Apply/Remove counter. */
523 uint32_t rix_flow; /* Built flow for copy. */
526 /* Table data structure of the hash organization. */
527 struct mlx5_flow_tbl_data_entry {
528 struct mlx5_hlist_entry entry;
529 /**< hash list entry, 64-bits key inside. */
530 struct mlx5_flow_tbl_resource tbl;
531 /**< flow table resource. */
532 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
533 /**< matchers' header associated with the flow table. */
534 struct mlx5_flow_dv_jump_tbl_resource jump;
535 /**< jump resource, at most one for each table created. */
536 uint32_t idx; /**< index for the indexed mempool. */
537 /**< tunnel offload */
538 const struct mlx5_flow_tunnel *tunnel;
543 /* Sub rdma-core actions list. */
544 struct mlx5_flow_sub_actions_list {
545 uint32_t actions_num; /**< Number of sample actions. */
546 uint64_t action_flags;
547 void *dr_queue_action;
550 void *dr_port_id_action;
551 void *dr_encap_action;
554 /* Sample sub-actions resource list. */
555 struct mlx5_flow_sub_actions_idx {
556 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
557 uint32_t rix_tag; /**< Index to the tag action. */
559 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
560 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
563 /* Sample action resource structure. */
564 struct mlx5_flow_dv_sample_resource {
565 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
566 uint32_t refcnt; /**< Reference counter. */
567 void *verbs_action; /**< Verbs sample action object. */
568 uint8_t ft_type; /** Flow Table Type */
569 uint32_t ft_id; /** Flow Table Level */
570 uint32_t ratio; /** Sample Ratio */
571 uint64_t set_action; /** Restore reg_c0 value */
572 void *normal_path_tbl; /** Flow Table pointer */
573 void *default_miss; /** default_miss dr_action. */
574 struct mlx5_flow_sub_actions_idx sample_idx;
575 /**< Action index resources. */
576 struct mlx5_flow_sub_actions_list sample_act;
577 /**< Action resources. */
580 #define MLX5_MAX_DEST_NUM 2
582 /* Destination array action resource structure. */
583 struct mlx5_flow_dv_dest_array_resource {
584 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
585 uint32_t refcnt; /**< Reference counter. */
586 uint8_t ft_type; /** Flow Table Type */
587 uint8_t num_of_dest; /**< Number of destination actions. */
588 void *action; /**< Pointer to the rdma core action. */
589 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
590 /**< Action index resources. */
591 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
592 /**< Action resources. */
595 /* Verbs specification header. */
596 struct ibv_spec_header {
597 enum ibv_flow_spec_type type;
601 /* RSS description. */
602 struct mlx5_flow_rss_desc {
604 uint32_t queue_num; /**< Number of entries in @p queue. */
605 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
606 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
607 uint16_t queue[]; /**< Destination queues to redirect traffic to. */
610 /* PMD flow priority for tunnel */
611 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
612 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
615 /** Device flow handle structure for DV mode only. */
616 struct mlx5_flow_handle_dv {
618 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
619 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
620 /**< Pointer to modify header resource in cache. */
621 uint32_t rix_encap_decap;
622 /**< Index to encap/decap resource in cache. */
623 uint32_t rix_push_vlan;
624 /**< Index to push VLAN action resource in cache. */
626 /**< Index to the tag action. */
628 /**< Index to sample action resource in cache. */
629 uint32_t rix_dest_array;
630 /**< Index to destination array resource in cache. */
633 /** Device flow handle structure: used both for creating & destroying. */
634 struct mlx5_flow_handle {
635 SILIST_ENTRY(uint32_t)next;
636 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
637 /**< Index to next device flow handle. */
639 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
640 void *drv_flow; /**< pointer to driver flow object. */
641 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
642 uint32_t mark:1; /**< Metadate rxq mark flag. */
643 uint32_t fate_action:3; /**< Fate action type. */
645 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
646 uint32_t rix_jump; /**< Index to the jump action resource. */
647 uint32_t rix_port_id_action;
648 /**< Index to port ID action resource. */
650 /**< Generic value indicates the fate action. */
651 uint32_t rix_default_fate;
652 /**< Indicates default miss fate action. */
654 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
655 struct mlx5_flow_handle_dv dvh;
660 * Size for Verbs device flow handle structure only. Do not use the DV only
661 * structure in Verbs. No DV flows attributes will be accessed.
662 * Macro offsetof() could also be used here.
664 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
665 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
666 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
668 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
672 * Max number of actions per DV flow.
673 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
674 * in rdma-core file providers/mlx5/verbs.c.
676 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
678 /** Device flow structure only for DV flow creation. */
679 struct mlx5_flow_dv_workspace {
680 uint32_t group; /**< The group index. */
681 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
682 int actions_n; /**< number of actions. */
683 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
684 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
685 /**< Pointer to encap/decap resource in cache. */
686 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
687 /**< Pointer to push VLAN action resource in cache. */
688 struct mlx5_flow_dv_tag_resource *tag_resource;
689 /**< pointer to the tag action. */
690 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
691 /**< Pointer to port ID action resource. */
692 struct mlx5_flow_dv_jump_tbl_resource *jump;
693 /**< Pointer to the jump action resource. */
694 struct mlx5_flow_dv_match_params value;
695 /**< Holds the value that the packet is compared to. */
696 struct mlx5_flow_dv_sample_resource *sample_res;
697 /**< Pointer to the sample action resource. */
698 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
699 /**< Pointer to the destination array resource. */
703 * Maximal Verbs flow specifications & actions size.
704 * Some elements are mutually exclusive, but enough space should be allocated.
705 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
706 * 2. One tunnel header (exception: GRE + MPLS),
707 * SPEC length: GRE == tunnel.
708 * Actions: 1. 1 Mark OR Flag.
709 * 2. 1 Drop (if any).
710 * 3. No limitation for counters, but it makes no sense to support too
711 * many counters in a single device flow.
713 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
714 #define MLX5_VERBS_MAX_SPEC_SIZE \
716 (2 * (sizeof(struct ibv_flow_spec_eth) + \
717 sizeof(struct ibv_flow_spec_ipv6) + \
718 sizeof(struct ibv_flow_spec_tcp_udp)) + \
719 sizeof(struct ibv_flow_spec_gre) + \
720 sizeof(struct ibv_flow_spec_mpls)) \
723 #define MLX5_VERBS_MAX_SPEC_SIZE \
725 (2 * (sizeof(struct ibv_flow_spec_eth) + \
726 sizeof(struct ibv_flow_spec_ipv6) + \
727 sizeof(struct ibv_flow_spec_tcp_udp)) + \
728 sizeof(struct ibv_flow_spec_tunnel)) \
732 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
733 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
734 #define MLX5_VERBS_MAX_ACT_SIZE \
736 sizeof(struct ibv_flow_spec_action_tag) + \
737 sizeof(struct ibv_flow_spec_action_drop) + \
738 sizeof(struct ibv_flow_spec_counter_action) * 4 \
741 #define MLX5_VERBS_MAX_ACT_SIZE \
743 sizeof(struct ibv_flow_spec_action_tag) + \
744 sizeof(struct ibv_flow_spec_action_drop) \
748 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
749 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
751 /** Device flow structure only for Verbs flow creation. */
752 struct mlx5_flow_verbs_workspace {
753 unsigned int size; /**< Size of the attribute. */
754 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
755 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
756 /**< Specifications & actions buffer of verbs flow. */
759 /** Maximal number of device sub-flows supported. */
760 #define MLX5_NUM_MAX_DEV_FLOWS 32
762 /** Device flow structure. */
764 struct rte_flow *flow; /**< Pointer to the main flow. */
765 uint32_t flow_idx; /**< The memory pool index to the main flow. */
766 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
768 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
769 bool external; /**< true if the flow is created external to PMD. */
770 uint8_t ingress; /**< 1 if the flow is ingress. */
772 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
773 struct mlx5_flow_dv_workspace dv;
775 struct mlx5_flow_verbs_workspace verbs;
777 struct mlx5_flow_handle *handle;
778 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
779 const struct mlx5_flow_tunnel *tunnel;
782 /* Flow meter state. */
783 #define MLX5_FLOW_METER_DISABLE 0
784 #define MLX5_FLOW_METER_ENABLE 1
786 #define MLX5_MAN_WIDTH 8
787 /* Modify this value if enum rte_mtr_color changes. */
788 #define RTE_MTR_DROPPED RTE_COLORS
790 /* Meter policer statistics */
791 struct mlx5_flow_policer_stats {
792 uint32_t cnt[RTE_COLORS + 1];
793 /**< Color counter, extra for drop. */
795 /**< Statistics mask for the colors. */
798 /* Meter table structure. */
799 struct mlx5_meter_domain_info {
800 struct mlx5_flow_tbl_resource *tbl;
802 struct mlx5_flow_tbl_resource *sfx_tbl;
803 /**< Meter suffix table. */
805 /**< Meter color not match default criteria. */
807 /**< Meter color match criteria. */
809 /**< Meter match action. */
810 void *policer_rules[RTE_MTR_DROPPED + 1];
811 /**< Meter policer for the match. */
814 /* Meter table set for TX RX FDB. */
815 struct mlx5_meter_domains_infos {
817 /**< Table user count. */
818 struct mlx5_meter_domain_info egress;
819 /**< TX meter table. */
820 struct mlx5_meter_domain_info ingress;
821 /**< RX meter table. */
822 struct mlx5_meter_domain_info transfer;
823 /**< FDB meter table. */
825 /**< Drop action as not matched. */
826 void *count_actns[RTE_MTR_DROPPED + 1];
827 /**< Counters for match and unmatched statistics. */
828 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
829 /**< Flow meter parameter. */
831 /**< Flow meter parameter size. */
833 /**< Flow meter action. */
836 /* Meter parameter structure. */
837 struct mlx5_flow_meter {
838 TAILQ_ENTRY(mlx5_flow_meter) next;
839 /**< Pointer to the next flow meter structure. */
840 uint32_t idx; /* Index to meter object. */
843 struct mlx5_flow_meter_profile *profile;
844 /**< Meter profile parameters. */
846 /** Policer actions (per meter output color). */
847 enum rte_mtr_policer_action action[RTE_COLORS];
849 /** Set of stats counters to be enabled.
850 * @see enum rte_mtr_stats_type
854 /**< Rule applies to ingress traffic. */
857 /**< Rule applies to egress traffic. */
860 * Instead of simply matching the properties of traffic as it would
861 * appear on a given DPDK port ID, enabling this attribute transfers
862 * a flow rule to the lowest possible level of any device endpoints
863 * found in the pattern.
865 * When supported, this effectively enables an application to
866 * re-route traffic not necessarily intended for it (e.g. coming
867 * from or addressed to different physical ports, VFs or
868 * applications) at the device level.
870 * It complements the behavior of some pattern items such as
871 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
873 * When transferring flow rules, ingress and egress attributes keep
874 * their original meaning, as if processing traffic emitted or
875 * received by the application.
878 struct mlx5_meter_domains_infos *mfts;
879 /**< Flow table created for this meter. */
880 struct mlx5_flow_policer_stats policer_stats;
881 /**< Meter policer statistics. */
884 uint32_t active_state:1;
887 /**< Meter shared or not. */
890 /* RFC2697 parameter structure. */
891 struct mlx5_flow_meter_srtcm_rfc2697_prm {
892 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
893 uint32_t cbs_exponent:5;
894 uint32_t cbs_mantissa:8;
895 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
896 uint32_t cir_exponent:5;
897 uint32_t cir_mantissa:8;
898 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
899 uint32_t ebs_exponent:5;
900 uint32_t ebs_mantissa:8;
903 /* Flow meter profile structure. */
904 struct mlx5_flow_meter_profile {
905 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
906 /**< Pointer to the next flow meter structure. */
907 uint32_t meter_profile_id; /**< Profile id. */
908 struct rte_mtr_meter_profile profile; /**< Profile detail. */
910 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
911 /**< srtcm_rfc2697 struct. */
913 uint32_t ref_cnt; /**< Use count. */
916 /* Fdir flow structure */
917 struct mlx5_fdir_flow {
918 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */
919 struct mlx5_fdir *fdir; /* Pointer to fdir. */
920 uint32_t rix_flow; /* Index to flow. */
923 #define HAIRPIN_FLOW_ID_BITS 28
925 #define MLX5_MAX_TUNNELS 256
926 #define MLX5_TNL_MISS_RULE_PRIORITY 3
927 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
930 * When tunnel offload is active, all JUMP group ids are converted
931 * using the same method. That conversion is applied both to tunnel and
932 * regular rule types.
933 * Group ids used in tunnel rules are relative to it's tunnel (!).
934 * Application can create number of steer rules, using the same
935 * tunnel, with different group id in each rule.
936 * Each tunnel stores its groups internally in PMD tunnel object.
937 * Groups used in regular rules do not belong to any tunnel and are stored
941 struct mlx5_flow_tunnel {
942 LIST_ENTRY(mlx5_flow_tunnel) chain;
943 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
944 uint32_t tunnel_id; /** unique tunnel ID */
946 struct rte_flow_action action;
947 struct rte_flow_item item;
948 struct mlx5_hlist *groups; /** tunnel groups */
951 /** PMD tunnel related context */
952 struct mlx5_flow_tunnel_hub {
953 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
954 struct mlx5_flow_id_pool *tunnel_ids;
955 struct mlx5_flow_id_pool *table_ids;
956 struct mlx5_hlist *groups; /** non tunnel groups */
959 /* convert jump group to flow table ID in tunnel rules */
960 struct tunnel_tbl_entry {
961 struct mlx5_hlist_entry hash;
965 static inline uint32_t
966 tunnel_id_to_flow_tbl(uint32_t id)
968 return id | (1u << 16);
971 static inline uint32_t
972 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
974 return flow_tbl & ~(1u << 16);
977 union tunnel_tbl_key {
985 static inline struct mlx5_flow_tunnel_hub *
986 mlx5_tunnel_hub(struct rte_eth_dev *dev)
988 struct mlx5_priv *priv = dev->data->dev_private;
989 return priv->sh->tunnel_hub;
993 is_tunnel_offload_active(struct rte_eth_dev *dev)
995 struct mlx5_priv *priv = dev->data->dev_private;
996 return !!priv->config.dv_miss_info;
1000 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
1001 __rte_unused const struct rte_flow_attr *attr,
1002 __rte_unused const struct rte_flow_item items[],
1003 __rte_unused const struct rte_flow_action actions[])
1005 return (items[0].type == (typeof(items[0].type))
1006 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1010 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1011 __rte_unused const struct rte_flow_attr *attr,
1012 __rte_unused const struct rte_flow_item items[],
1013 __rte_unused const struct rte_flow_action actions[])
1015 return (actions[0].type == (typeof(actions[0].type))
1016 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1019 static inline const struct mlx5_flow_tunnel *
1020 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1022 return actions[0].conf;
1025 static inline const struct mlx5_flow_tunnel *
1026 flow_items_to_tunnel(const struct rte_flow_item items[])
1028 return items[0].spec;
1031 /* Flow structure. */
1033 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1034 struct mlx5_shared_action_rss *shared_rss; /** < Shred RSS action. */
1035 uint32_t dev_handles;
1036 /**< Device flow handles that are part of the flow. */
1037 uint32_t drv_type:2; /**< Driver type. */
1038 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */
1040 uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS;
1041 /**< The flow id used for hairpin. */
1042 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
1043 uint32_t rix_mreg_copy;
1044 /**< Index to metadata register copy table resource. */
1045 uint32_t counter; /**< Holds flow counter. */
1046 uint32_t tunnel_id; /**< Tunnel id */
1047 uint16_t meter; /**< Holds flow meter id. */
1051 * Define list of valid combinations of RX Hash fields
1052 * (see enum ibv_rx_hash_fields).
1054 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1055 #define MLX5_RSS_HASH_IPV4_TCP \
1056 (MLX5_RSS_HASH_IPV4 | \
1057 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1058 #define MLX5_RSS_HASH_IPV4_UDP \
1059 (MLX5_RSS_HASH_IPV4 | \
1060 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1061 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1062 #define MLX5_RSS_HASH_IPV6_TCP \
1063 (MLX5_RSS_HASH_IPV6 | \
1064 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1065 #define MLX5_RSS_HASH_IPV6_UDP \
1066 (MLX5_RSS_HASH_IPV6 | \
1067 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1068 #define MLX5_RSS_HASH_NONE 0ULL
1070 /* array of valid combinations of RX Hash fields for RSS */
1071 static const uint64_t mlx5_rss_hash_fields[] = {
1073 MLX5_RSS_HASH_IPV4_TCP,
1074 MLX5_RSS_HASH_IPV4_UDP,
1076 MLX5_RSS_HASH_IPV6_TCP,
1077 MLX5_RSS_HASH_IPV6_UDP,
1081 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
1083 /* Shared RSS action structure */
1084 struct mlx5_shared_action_rss {
1085 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1086 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1087 uint16_t *queue; /**< Queue indices to use. */
1088 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1089 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1090 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
1091 /**< Hash RX queue indexes for tunneled RSS */
1094 struct rte_flow_shared_action {
1095 LIST_ENTRY(rte_flow_shared_action) next;
1096 /**< Pointer to the next element. */
1097 uint32_t refcnt; /**< Atomically accessed refcnt. */
1099 /**< Shared action type (see MLX5_FLOW_ACTION_SHARED_*). */
1101 struct mlx5_shared_action_rss rss;
1102 /**< Shared RSS action. */
1106 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1107 const struct rte_flow_attr *attr,
1108 const struct rte_flow_item items[],
1109 const struct rte_flow_action actions[],
1112 struct rte_flow_error *error);
1113 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1114 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1115 const struct rte_flow_item items[],
1116 const struct rte_flow_action actions[], struct rte_flow_error *error);
1117 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1118 struct mlx5_flow *dev_flow,
1119 const struct rte_flow_attr *attr,
1120 const struct rte_flow_item items[],
1121 const struct rte_flow_action actions[],
1122 struct rte_flow_error *error);
1123 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1124 struct rte_flow_error *error);
1125 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1126 struct rte_flow *flow);
1127 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1128 struct rte_flow *flow);
1129 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1130 struct rte_flow *flow,
1131 const struct rte_flow_action *actions,
1133 struct rte_flow_error *error);
1134 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1135 (struct rte_eth_dev *dev,
1136 const struct mlx5_flow_meter *fm);
1137 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1138 struct mlx5_meter_domains_infos *tbls);
1139 typedef int (*mlx5_flow_create_policer_rules_t)
1140 (struct rte_eth_dev *dev,
1141 struct mlx5_flow_meter *fm,
1142 const struct rte_flow_attr *attr);
1143 typedef int (*mlx5_flow_destroy_policer_rules_t)
1144 (struct rte_eth_dev *dev,
1145 const struct mlx5_flow_meter *fm,
1146 const struct rte_flow_attr *attr);
1147 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1148 (struct rte_eth_dev *dev);
1149 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1151 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1153 bool clear, uint64_t *pkts,
1155 typedef int (*mlx5_flow_get_aged_flows_t)
1156 (struct rte_eth_dev *dev,
1158 uint32_t nb_contexts,
1159 struct rte_flow_error *error);
1160 typedef int (*mlx5_flow_action_validate_t)
1161 (struct rte_eth_dev *dev,
1162 const struct rte_flow_shared_action_conf *conf,
1163 const struct rte_flow_action *action,
1164 struct rte_flow_error *error);
1165 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1166 (struct rte_eth_dev *dev,
1167 const struct rte_flow_shared_action_conf *conf,
1168 const struct rte_flow_action *action,
1169 struct rte_flow_error *error);
1170 typedef int (*mlx5_flow_action_destroy_t)
1171 (struct rte_eth_dev *dev,
1172 struct rte_flow_shared_action *action,
1173 struct rte_flow_error *error);
1174 typedef int (*mlx5_flow_action_update_t)
1175 (struct rte_eth_dev *dev,
1176 struct rte_flow_shared_action *action,
1177 const void *action_conf,
1178 struct rte_flow_error *error);
1179 struct mlx5_flow_driver_ops {
1180 mlx5_flow_validate_t validate;
1181 mlx5_flow_prepare_t prepare;
1182 mlx5_flow_translate_t translate;
1183 mlx5_flow_apply_t apply;
1184 mlx5_flow_remove_t remove;
1185 mlx5_flow_destroy_t destroy;
1186 mlx5_flow_query_t query;
1187 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1188 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1189 mlx5_flow_create_policer_rules_t create_policer_rules;
1190 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1191 mlx5_flow_counter_alloc_t counter_alloc;
1192 mlx5_flow_counter_free_t counter_free;
1193 mlx5_flow_counter_query_t counter_query;
1194 mlx5_flow_get_aged_flows_t get_aged_flows;
1195 mlx5_flow_action_validate_t action_validate;
1196 mlx5_flow_action_create_t action_create;
1197 mlx5_flow_action_destroy_t action_destroy;
1198 mlx5_flow_action_update_t action_update;
1203 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id);
1204 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
1205 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
1206 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
1209 struct flow_grp_info {
1210 uint64_t external:1;
1211 uint64_t transfer:1;
1212 uint64_t fdb_def_rule:1;
1213 /* force standard group translation */
1214 uint64_t std_tbl_fix:1;
1218 tunnel_use_standard_attr_group_translate
1219 (struct rte_eth_dev *dev,
1220 const struct mlx5_flow_tunnel *tunnel,
1221 const struct rte_flow_attr *attr,
1222 const struct rte_flow_item items[],
1223 const struct rte_flow_action actions[])
1227 if (!is_tunnel_offload_active(dev))
1228 /* no tunnel offload API */
1232 * OvS will use jump to group 0 in tunnel steer rule.
1233 * If tunnel steer rule starts from group 0 (attr.group == 0)
1234 * that 0 group must be translated with standard method.
1235 * attr.group == 0 in tunnel match rule translated with tunnel
1238 verdict = !attr->group &&
1239 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1242 * non-tunnel group translation uses standard method for
1243 * root group only: attr.group == 0
1245 verdict = !attr->group;
1251 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1252 const struct mlx5_flow_tunnel *tunnel,
1253 uint32_t group, uint32_t *table,
1254 struct flow_grp_info flags,
1255 struct rte_flow_error *error);
1256 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1257 int tunnel, uint64_t layer_types,
1258 uint64_t hash_fields);
1259 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1260 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1261 uint32_t subpriority);
1262 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1263 enum mlx5_feature_name feature,
1265 struct rte_flow_error *error);
1266 const struct rte_flow_action *mlx5_flow_find_action
1267 (const struct rte_flow_action *actions,
1268 enum rte_flow_action_type action);
1269 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1270 const struct rte_flow_action *action,
1271 struct rte_flow_error *error);
1272 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1273 const struct rte_flow_attr *attr,
1274 struct rte_flow_error *error);
1275 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1276 const struct rte_flow_attr *attr,
1277 struct rte_flow_error *error);
1278 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1279 const struct rte_flow_attr *attr,
1280 struct rte_flow_error *error);
1281 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1282 uint64_t action_flags,
1283 const struct rte_flow_attr *attr,
1284 struct rte_flow_error *error);
1285 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1286 uint64_t action_flags,
1287 struct rte_eth_dev *dev,
1288 const struct rte_flow_attr *attr,
1289 struct rte_flow_error *error);
1290 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1291 uint64_t action_flags,
1292 struct rte_eth_dev *dev,
1293 const struct rte_flow_attr *attr,
1294 uint64_t item_flags,
1295 struct rte_flow_error *error);
1296 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1297 const struct rte_flow_attr *attr,
1298 struct rte_flow_error *error);
1299 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1300 const struct rte_flow_attr *attributes,
1301 struct rte_flow_error *error);
1302 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1303 const uint8_t *mask,
1304 const uint8_t *nic_mask,
1306 bool range_accepted,
1307 struct rte_flow_error *error);
1308 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1309 uint64_t item_flags,
1310 struct rte_flow_error *error);
1311 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1312 uint64_t item_flags,
1313 uint8_t target_protocol,
1314 struct rte_flow_error *error);
1315 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1316 uint64_t item_flags,
1317 const struct rte_flow_item *gre_item,
1318 struct rte_flow_error *error);
1319 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1320 uint64_t item_flags,
1322 uint16_t ether_type,
1323 const struct rte_flow_item_ipv4 *acc_mask,
1324 bool range_accepted,
1325 struct rte_flow_error *error);
1326 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1327 uint64_t item_flags,
1329 uint16_t ether_type,
1330 const struct rte_flow_item_ipv6 *acc_mask,
1331 struct rte_flow_error *error);
1332 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1333 const struct rte_flow_item *item,
1334 uint64_t item_flags,
1335 uint64_t prev_layer,
1336 struct rte_flow_error *error);
1337 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1338 uint64_t item_flags,
1339 uint8_t target_protocol,
1340 const struct rte_flow_item_tcp *flow_mask,
1341 struct rte_flow_error *error);
1342 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1343 uint64_t item_flags,
1344 uint8_t target_protocol,
1345 struct rte_flow_error *error);
1346 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1347 uint64_t item_flags,
1348 struct rte_eth_dev *dev,
1349 struct rte_flow_error *error);
1350 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1351 uint64_t item_flags,
1352 struct rte_flow_error *error);
1353 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1354 uint64_t item_flags,
1355 struct rte_eth_dev *dev,
1356 struct rte_flow_error *error);
1357 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1358 uint64_t item_flags,
1359 uint8_t target_protocol,
1360 struct rte_flow_error *error);
1361 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1362 uint64_t item_flags,
1363 uint8_t target_protocol,
1364 struct rte_flow_error *error);
1365 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1366 uint64_t item_flags,
1367 uint8_t target_protocol,
1368 struct rte_flow_error *error);
1369 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1370 uint64_t item_flags,
1371 struct rte_eth_dev *dev,
1372 struct rte_flow_error *error);
1373 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1374 uint64_t item_flags,
1376 uint16_t ether_type,
1377 const struct rte_flow_item_ecpri *acc_mask,
1378 struct rte_flow_error *error);
1379 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1380 (struct rte_eth_dev *dev,
1381 const struct mlx5_flow_meter *fm);
1382 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1383 struct mlx5_meter_domains_infos *tbl);
1384 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1385 struct mlx5_flow_meter *fm,
1386 const struct rte_flow_attr *attr);
1387 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1388 struct mlx5_flow_meter *fm,
1389 const struct rte_flow_attr *attr);
1390 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1391 struct rte_mtr_error *error);
1392 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1393 struct rte_flow_shared_action *mlx5_flow_get_shared_rss(struct rte_flow *flow);
1394 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1395 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1396 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1397 #endif /* RTE_PMD_MLX5_FLOW_H_ */