1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* Private rte flow items. */
22 enum mlx5_rte_flow_item_type {
23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
24 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
30 /* Private (internal) rte flow actions. */
31 enum mlx5_rte_flow_action_type {
32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
34 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
38 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
39 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
40 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
43 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
46 MLX5_INDIRECT_ACTION_TYPE_RSS,
47 MLX5_INDIRECT_ACTION_TYPE_AGE,
50 /* Matches on selected register. */
51 struct mlx5_rte_flow_item_tag {
56 /* Modify selected register. */
57 struct mlx5_rte_flow_action_set_tag {
64 struct mlx5_flow_action_copy_mreg {
69 /* Matches on source queue. */
70 struct mlx5_rte_flow_item_tx_queue {
74 /* Feature name to allocate metadata register. */
75 enum mlx5_feature_name {
89 /* Default queue number. */
90 #define MLX5_RSSQ_DEFAULT_NUM 16
92 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
93 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
94 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
95 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
96 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
97 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
99 /* Pattern inner Layer bits. */
100 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
101 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
102 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
103 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
104 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
105 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
107 /* Pattern tunnel Layer bits. */
108 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
109 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
110 #define MLX5_FLOW_LAYER_GRE (1u << 14)
111 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
112 /* List of tunnel Layer bits continued below. */
114 /* General pattern items bits. */
115 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
116 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
117 #define MLX5_FLOW_ITEM_TAG (1u << 18)
118 #define MLX5_FLOW_ITEM_MARK (1u << 19)
120 /* Pattern MISC bits. */
121 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
122 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
123 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
125 /* Pattern tunnel Layer bits (continued). */
126 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
127 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
128 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
129 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
132 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
134 /* Pattern tunnel Layer bits (continued). */
135 #define MLX5_FLOW_LAYER_GTP (1u << 28)
137 /* Pattern eCPRI Layer bit. */
138 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
140 /* IPv6 Fragment Extension Header bit. */
141 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
142 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
144 /* Pattern tunnel Layer bits (continued). */
145 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
146 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
149 #define MLX5_FLOW_LAYER_OUTER_L3 \
150 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
151 #define MLX5_FLOW_LAYER_OUTER_L4 \
152 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
153 #define MLX5_FLOW_LAYER_OUTER \
154 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
155 MLX5_FLOW_LAYER_OUTER_L4)
158 #define MLX5_FLOW_LAYER_TUNNEL \
159 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
160 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
161 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
162 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
165 #define MLX5_FLOW_LAYER_INNER_L3 \
166 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
167 #define MLX5_FLOW_LAYER_INNER_L4 \
168 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
169 #define MLX5_FLOW_LAYER_INNER \
170 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
171 MLX5_FLOW_LAYER_INNER_L4)
174 #define MLX5_FLOW_LAYER_L2 \
175 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
176 #define MLX5_FLOW_LAYER_L3_IPV4 \
177 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
178 #define MLX5_FLOW_LAYER_L3_IPV6 \
179 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
180 #define MLX5_FLOW_LAYER_L3 \
181 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
182 #define MLX5_FLOW_LAYER_L4 \
183 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
186 #define MLX5_FLOW_ACTION_DROP (1u << 0)
187 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
188 #define MLX5_FLOW_ACTION_RSS (1u << 2)
189 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
190 #define MLX5_FLOW_ACTION_MARK (1u << 4)
191 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
192 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
193 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
194 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
195 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
196 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
197 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
198 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
199 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
200 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
201 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
202 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
203 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
204 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
205 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
206 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
207 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
208 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
209 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
210 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
211 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
212 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
213 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
214 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
215 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
216 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
217 #define MLX5_FLOW_ACTION_METER (1ull << 31)
218 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
219 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
220 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
221 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
222 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
223 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
224 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
225 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
226 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
228 #define MLX5_FLOW_FATE_ACTIONS \
229 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
230 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
231 MLX5_FLOW_ACTION_DEFAULT_MISS | \
232 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
234 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
235 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
236 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
238 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
239 MLX5_FLOW_ACTION_SET_IPV4_DST | \
240 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
241 MLX5_FLOW_ACTION_SET_IPV6_DST | \
242 MLX5_FLOW_ACTION_SET_TP_SRC | \
243 MLX5_FLOW_ACTION_SET_TP_DST | \
244 MLX5_FLOW_ACTION_SET_TTL | \
245 MLX5_FLOW_ACTION_DEC_TTL | \
246 MLX5_FLOW_ACTION_SET_MAC_SRC | \
247 MLX5_FLOW_ACTION_SET_MAC_DST | \
248 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
249 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
250 MLX5_FLOW_ACTION_INC_TCP_ACK | \
251 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
252 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
253 MLX5_FLOW_ACTION_SET_TAG | \
254 MLX5_FLOW_ACTION_MARK_EXT | \
255 MLX5_FLOW_ACTION_SET_META | \
256 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
257 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
258 MLX5_FLOW_ACTION_MODIFY_FIELD)
260 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
261 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
263 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
266 #define IPPROTO_MPLS 137
269 /* UDP port number for MPLS */
270 #define MLX5_UDP_PORT_MPLS 6635
272 /* UDP port numbers for VxLAN. */
273 #define MLX5_UDP_PORT_VXLAN 4789
274 #define MLX5_UDP_PORT_VXLAN_GPE 4790
276 /* UDP port numbers for GENEVE. */
277 #define MLX5_UDP_PORT_GENEVE 6081
279 /* Lowest priority indicator. */
280 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
283 * Max priority for ingress\egress flow groups
284 * greater than 0 and for any transfer flow group.
285 * From user configation: 0 - 21843.
287 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
290 * Number of sub priorities.
291 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
292 * matching on the NIC (firmware dependent) L4 most have the higher priority
293 * followed by L3 and ending with L2.
295 #define MLX5_PRIORITY_MAP_L2 2
296 #define MLX5_PRIORITY_MAP_L3 1
297 #define MLX5_PRIORITY_MAP_L4 0
298 #define MLX5_PRIORITY_MAP_MAX 3
300 /* Valid layer type for IPV4 RSS. */
301 #define MLX5_IPV4_LAYER_TYPES \
302 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
303 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
304 ETH_RSS_NONFRAG_IPV4_OTHER)
306 /* IBV hash source bits for IPV4. */
307 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
309 /* Valid layer type for IPV6 RSS. */
310 #define MLX5_IPV6_LAYER_TYPES \
311 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
312 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
313 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
315 /* IBV hash source bits for IPV6. */
316 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
318 /* IBV hash bits for L3 SRC. */
319 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
321 /* IBV hash bits for L3 DST. */
322 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
324 /* IBV hash bits for TCP. */
325 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
326 IBV_RX_HASH_DST_PORT_TCP)
328 /* IBV hash bits for UDP. */
329 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
330 IBV_RX_HASH_DST_PORT_UDP)
332 /* IBV hash bits for L4 SRC. */
333 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
334 IBV_RX_HASH_SRC_PORT_UDP)
336 /* IBV hash bits for L4 DST. */
337 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
338 IBV_RX_HASH_DST_PORT_UDP)
340 /* Geneve header first 16Bit */
341 #define MLX5_GENEVE_VER_MASK 0x3
342 #define MLX5_GENEVE_VER_SHIFT 14
343 #define MLX5_GENEVE_VER_VAL(a) \
344 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
345 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
346 #define MLX5_GENEVE_OPTLEN_SHIFT 8
347 #define MLX5_GENEVE_OPTLEN_VAL(a) \
348 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
349 #define MLX5_GENEVE_OAMF_MASK 0x1
350 #define MLX5_GENEVE_OAMF_SHIFT 7
351 #define MLX5_GENEVE_OAMF_VAL(a) \
352 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
353 #define MLX5_GENEVE_CRITO_MASK 0x1
354 #define MLX5_GENEVE_CRITO_SHIFT 6
355 #define MLX5_GENEVE_CRITO_VAL(a) \
356 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
357 #define MLX5_GENEVE_RSVD_MASK 0x3F
358 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
360 * The length of the Geneve options fields, expressed in four byte multiples,
361 * not including the eight byte fixed tunnel.
363 #define MLX5_GENEVE_OPT_LEN_0 14
364 #define MLX5_GENEVE_OPT_LEN_1 63
366 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
367 sizeof(struct rte_ipv4_hdr))
368 /* GTP extension header flag. */
369 #define MLX5_GTP_EXT_HEADER_FLAG 4
371 /* GTP extension header max PDU type value. */
372 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
374 /* GTP extension header PDU type shift. */
375 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
377 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
378 #define MLX5_IPV4_FRAG_OFFSET_MASK \
379 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
381 /* Specific item's fields can accept a range of values (using spec and last). */
382 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
383 #define MLX5_ITEM_RANGE_ACCEPTED true
385 /* Software header modify action numbers of a flow. */
386 #define MLX5_ACT_NUM_MDF_IPV4 1
387 #define MLX5_ACT_NUM_MDF_IPV6 4
388 #define MLX5_ACT_NUM_MDF_MAC 2
389 #define MLX5_ACT_NUM_MDF_VID 1
390 #define MLX5_ACT_NUM_MDF_PORT 2
391 #define MLX5_ACT_NUM_MDF_TTL 1
392 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
393 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
394 #define MLX5_ACT_NUM_MDF_TCPACK 1
395 #define MLX5_ACT_NUM_SET_REG 1
396 #define MLX5_ACT_NUM_SET_TAG 1
397 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
398 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
399 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
400 #define MLX5_ACT_NUM_SET_DSCP 1
402 /* Maximum number of fields to modify in MODIFY_FIELD */
403 #define MLX5_ACT_MAX_MOD_FIELDS 5
405 enum mlx5_flow_drv_type {
408 MLX5_FLOW_TYPE_VERBS,
412 /* Fate action type. */
413 enum mlx5_flow_fate_type {
414 MLX5_FLOW_FATE_NONE, /* Egress flow. */
415 MLX5_FLOW_FATE_QUEUE,
417 MLX5_FLOW_FATE_PORT_ID,
419 MLX5_FLOW_FATE_DEFAULT_MISS,
420 MLX5_FLOW_FATE_SHARED_RSS,
424 /* Matcher PRM representation */
425 struct mlx5_flow_dv_match_params {
427 /**< Size of match value. Do NOT split size and key! */
428 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
429 /**< Matcher value. This value is used as the mask or as a key. */
432 /* Matcher structure. */
433 struct mlx5_flow_dv_matcher {
434 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
435 struct mlx5_flow_tbl_resource *tbl;
436 /**< Pointer to the table(group) the matcher associated with. */
437 void *matcher_object; /**< Pointer to DV matcher */
438 uint16_t crc; /**< CRC of key. */
439 uint16_t priority; /**< Priority of matcher. */
440 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
443 #define MLX5_ENCAP_MAX_LEN 132
445 /* Encap/decap resource structure. */
446 struct mlx5_flow_dv_encap_decap_resource {
447 struct mlx5_hlist_entry entry;
448 /* Pointer to next element. */
449 uint32_t refcnt; /**< Reference counter. */
451 /**< Encap/decap action object. */
452 uint8_t buf[MLX5_ENCAP_MAX_LEN];
454 uint8_t reformat_type;
456 uint64_t flags; /**< Flags for RDMA API. */
457 uint32_t idx; /**< Index for the index memory pool. */
460 /* Tag resource structure. */
461 struct mlx5_flow_dv_tag_resource {
462 struct mlx5_hlist_entry entry;
463 /**< hash list entry for tag resource, tag value as the key. */
465 /**< Tag action object. */
466 uint32_t refcnt; /**< Reference counter. */
467 uint32_t idx; /**< Index for the index memory pool. */
468 uint32_t tag_id; /**< Tag ID. */
472 * Number of modification commands.
473 * The maximal actions amount in FW is some constant, and it is 16 in the
474 * latest releases. In some old releases, it will be limited to 8.
475 * Since there is no interface to query the capacity, the maximal value should
476 * be used to allow PMD to create the flow. The validation will be done in the
477 * lower driver layer or FW. A failure will be returned if exceeds the maximal
478 * supported actions number on the root table.
479 * On non-root tables, there is no limitation, but 32 is enough right now.
481 #define MLX5_MAX_MODIFY_NUM 32
482 #define MLX5_ROOT_TBL_MODIFY_NUM 16
484 /* Modify resource structure */
485 struct mlx5_flow_dv_modify_hdr_resource {
486 struct mlx5_hlist_entry entry;
487 void *action; /**< Modify header action object. */
488 /* Key area for hash list matching: */
489 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
490 uint32_t actions_num; /**< Number of modification actions. */
491 uint64_t flags; /**< Flags for RDMA API. */
492 struct mlx5_modification_cmd actions[];
493 /**< Modification actions. */
496 /* Modify resource key of the hash organization. */
497 union mlx5_flow_modify_hdr_key {
499 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
500 uint32_t actions_num:5; /**< Number of modification actions. */
501 uint32_t group:19; /**< Flow group id. */
502 uint32_t cksum; /**< Actions check sum. */
504 uint64_t v64; /**< full 64bits value of key */
507 /* Jump action resource structure. */
508 struct mlx5_flow_dv_jump_tbl_resource {
509 void *action; /**< Pointer to the rdma core action. */
512 /* Port ID resource structure. */
513 struct mlx5_flow_dv_port_id_action_resource {
514 struct mlx5_cache_entry entry;
515 void *action; /**< Action object. */
516 uint32_t port_id; /**< Port ID value. */
517 uint32_t idx; /**< Indexed pool memory index. */
520 /* Push VLAN action resource structure */
521 struct mlx5_flow_dv_push_vlan_action_resource {
522 struct mlx5_cache_entry entry; /* Cache entry. */
523 void *action; /**< Action object. */
524 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
525 rte_be32_t vlan_tag; /**< VLAN tag value. */
526 uint32_t idx; /**< Indexed pool memory index. */
529 /* Metadata register copy table entry. */
530 struct mlx5_flow_mreg_copy_resource {
532 * Hash list entry for copy table.
533 * - Key is 32/64-bit MARK action ID.
534 * - MUST be the first entry.
536 struct mlx5_hlist_entry hlist_ent;
537 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
538 /* List entry for device flows. */
540 uint32_t rix_flow; /* Built flow for copy. */
544 /* Table tunnel parameter. */
545 struct mlx5_flow_tbl_tunnel_prm {
546 const struct mlx5_flow_tunnel *tunnel;
551 /* Table data structure of the hash organization. */
552 struct mlx5_flow_tbl_data_entry {
553 struct mlx5_hlist_entry entry;
554 /**< hash list entry, 64-bits key inside. */
555 struct mlx5_flow_tbl_resource tbl;
556 /**< flow table resource. */
557 struct mlx5_cache_list matchers;
558 /**< matchers' header associated with the flow table. */
559 struct mlx5_flow_dv_jump_tbl_resource jump;
560 /**< jump resource, at most one for each table created. */
561 uint32_t idx; /**< index for the indexed mempool. */
562 /**< tunnel offload */
563 const struct mlx5_flow_tunnel *tunnel;
566 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
567 uint32_t is_egress:1; /**< Egress table. */
568 uint32_t is_transfer:1; /**< Transfer table. */
569 uint32_t dummy:1; /**< DR table. */
570 uint32_t id:22; /**< Table ID. */
571 uint32_t reserve:5; /**< Reserved to future using. */
572 uint32_t level; /**< Table level. */
575 /* Sub rdma-core actions list. */
576 struct mlx5_flow_sub_actions_list {
577 uint32_t actions_num; /**< Number of sample actions. */
578 uint64_t action_flags;
579 void *dr_queue_action;
582 void *dr_port_id_action;
583 void *dr_encap_action;
584 void *dr_jump_action;
587 /* Sample sub-actions resource list. */
588 struct mlx5_flow_sub_actions_idx {
589 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
590 uint32_t rix_tag; /**< Index to the tag action. */
591 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
592 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
593 uint32_t rix_jump; /**< Index to the jump action resource. */
596 /* Sample action resource structure. */
597 struct mlx5_flow_dv_sample_resource {
598 struct mlx5_cache_entry entry; /**< Cache entry. */
600 void *verbs_action; /**< Verbs sample action object. */
601 void **sub_actions; /**< Sample sub-action array. */
603 struct rte_eth_dev *dev; /**< Device registers the action. */
604 uint32_t idx; /** Sample object index. */
605 uint8_t ft_type; /** Flow Table Type */
606 uint32_t ft_id; /** Flow Table Level */
607 uint32_t ratio; /** Sample Ratio */
608 uint64_t set_action; /** Restore reg_c0 value */
609 void *normal_path_tbl; /** Flow Table pointer */
610 struct mlx5_flow_sub_actions_idx sample_idx;
611 /**< Action index resources. */
612 struct mlx5_flow_sub_actions_list sample_act;
613 /**< Action resources. */
616 #define MLX5_MAX_DEST_NUM 2
618 /* Destination array action resource structure. */
619 struct mlx5_flow_dv_dest_array_resource {
620 struct mlx5_cache_entry entry; /**< Cache entry. */
621 uint32_t idx; /** Destination array action object index. */
622 uint8_t ft_type; /** Flow Table Type */
623 uint8_t num_of_dest; /**< Number of destination actions. */
624 struct rte_eth_dev *dev; /**< Device registers the action. */
625 void *action; /**< Pointer to the rdma core action. */
626 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
627 /**< Action index resources. */
628 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
629 /**< Action resources. */
632 /* PMD flow priority for tunnel */
633 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
634 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
637 /** Device flow handle structure for DV mode only. */
638 struct mlx5_flow_handle_dv {
640 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
641 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
642 /**< Pointer to modify header resource in cache. */
643 uint32_t rix_encap_decap;
644 /**< Index to encap/decap resource in cache. */
645 uint32_t rix_push_vlan;
646 /**< Index to push VLAN action resource in cache. */
648 /**< Index to the tag action. */
650 /**< Index to sample action resource in cache. */
651 uint32_t rix_dest_array;
652 /**< Index to destination array resource in cache. */
655 /** Device flow handle structure: used both for creating & destroying. */
656 struct mlx5_flow_handle {
657 SILIST_ENTRY(uint32_t)next;
658 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
659 /**< Index to next device flow handle. */
661 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
662 void *drv_flow; /**< pointer to driver flow object. */
663 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
664 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
665 uint32_t mark:1; /**< Metadate rxq mark flag. */
666 uint32_t fate_action:3; /**< Fate action type. */
668 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
669 uint32_t rix_jump; /**< Index to the jump action resource. */
670 uint32_t rix_port_id_action;
671 /**< Index to port ID action resource. */
673 /**< Generic value indicates the fate action. */
674 uint32_t rix_default_fate;
675 /**< Indicates default miss fate action. */
677 /**< Indicates shared RSS fate action. */
679 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
680 struct mlx5_flow_handle_dv dvh;
685 * Size for Verbs device flow handle structure only. Do not use the DV only
686 * structure in Verbs. No DV flows attributes will be accessed.
687 * Macro offsetof() could also be used here.
689 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
690 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
691 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
693 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
696 /** Device flow structure only for DV flow creation. */
697 struct mlx5_flow_dv_workspace {
698 uint32_t group; /**< The group index. */
699 uint32_t table_id; /**< Flow table identifier. */
700 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
701 int actions_n; /**< number of actions. */
702 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
703 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
704 /**< Pointer to encap/decap resource in cache. */
705 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
706 /**< Pointer to push VLAN action resource in cache. */
707 struct mlx5_flow_dv_tag_resource *tag_resource;
708 /**< pointer to the tag action. */
709 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
710 /**< Pointer to port ID action resource. */
711 struct mlx5_flow_dv_jump_tbl_resource *jump;
712 /**< Pointer to the jump action resource. */
713 struct mlx5_flow_dv_match_params value;
714 /**< Holds the value that the packet is compared to. */
715 struct mlx5_flow_dv_sample_resource *sample_res;
716 /**< Pointer to the sample action resource. */
717 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
718 /**< Pointer to the destination array resource. */
721 #ifdef HAVE_INFINIBAND_VERBS_H
723 * Maximal Verbs flow specifications & actions size.
724 * Some elements are mutually exclusive, but enough space should be allocated.
725 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
726 * 2. One tunnel header (exception: GRE + MPLS),
727 * SPEC length: GRE == tunnel.
728 * Actions: 1. 1 Mark OR Flag.
729 * 2. 1 Drop (if any).
730 * 3. No limitation for counters, but it makes no sense to support too
731 * many counters in a single device flow.
733 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
734 #define MLX5_VERBS_MAX_SPEC_SIZE \
736 (2 * (sizeof(struct ibv_flow_spec_eth) + \
737 sizeof(struct ibv_flow_spec_ipv6) + \
738 sizeof(struct ibv_flow_spec_tcp_udp)) + \
739 sizeof(struct ibv_flow_spec_gre) + \
740 sizeof(struct ibv_flow_spec_mpls)) \
743 #define MLX5_VERBS_MAX_SPEC_SIZE \
745 (2 * (sizeof(struct ibv_flow_spec_eth) + \
746 sizeof(struct ibv_flow_spec_ipv6) + \
747 sizeof(struct ibv_flow_spec_tcp_udp)) + \
748 sizeof(struct ibv_flow_spec_tunnel)) \
752 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
753 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
754 #define MLX5_VERBS_MAX_ACT_SIZE \
756 sizeof(struct ibv_flow_spec_action_tag) + \
757 sizeof(struct ibv_flow_spec_action_drop) + \
758 sizeof(struct ibv_flow_spec_counter_action) * 4 \
761 #define MLX5_VERBS_MAX_ACT_SIZE \
763 sizeof(struct ibv_flow_spec_action_tag) + \
764 sizeof(struct ibv_flow_spec_action_drop) \
768 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
769 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
771 /** Device flow structure only for Verbs flow creation. */
772 struct mlx5_flow_verbs_workspace {
773 unsigned int size; /**< Size of the attribute. */
774 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
775 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
776 /**< Specifications & actions buffer of verbs flow. */
778 #endif /* HAVE_INFINIBAND_VERBS_H */
780 #define MLX5_SCALE_FLOW_GROUP_BIT 0
781 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
783 /** Maximal number of device sub-flows supported. */
784 #define MLX5_NUM_MAX_DEV_FLOWS 32
786 /** Device flow structure. */
789 struct rte_flow *flow; /**< Pointer to the main flow. */
790 uint32_t flow_idx; /**< The memory pool index to the main flow. */
791 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
793 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
794 bool external; /**< true if the flow is created external to PMD. */
795 uint8_t ingress:1; /**< 1 if the flow is ingress. */
796 uint8_t skip_scale:2;
798 * Each Bit be set to 1 if Skip the scale the flow group with factor.
799 * If bit0 be set to 1, then skip the scale the original flow group;
800 * If bit1 be set to 1, then skip the scale the jump flow group if
801 * having jump action.
802 * 00: Enable scale in a flow, default value.
803 * 01: Skip scale the flow group with factor, enable scale the group
805 * 10: Enable scale the group with factor, skip scale the group of
807 * 11: Skip scale the table with factor both for flow group and jump
811 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
812 struct mlx5_flow_dv_workspace dv;
814 #ifdef HAVE_INFINIBAND_VERBS_H
815 struct mlx5_flow_verbs_workspace verbs;
818 struct mlx5_flow_handle *handle;
819 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
820 const struct mlx5_flow_tunnel *tunnel;
823 /* Flow meter state. */
824 #define MLX5_FLOW_METER_DISABLE 0
825 #define MLX5_FLOW_METER_ENABLE 1
827 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
828 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
830 #define MLX5_MAN_WIDTH 8
831 /* Legacy Meter parameter structure. */
832 struct mlx5_legacy_flow_meter {
833 struct mlx5_flow_meter_info fm;
834 /* Must be the first in struct. */
835 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
836 /**< Pointer to the next flow meter structure. */
838 /* Index to meter object. */
841 #define MLX5_MAX_TUNNELS 256
842 #define MLX5_TNL_MISS_RULE_PRIORITY 3
843 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
846 * When tunnel offload is active, all JUMP group ids are converted
847 * using the same method. That conversion is applied both to tunnel and
848 * regular rule types.
849 * Group ids used in tunnel rules are relative to it's tunnel (!).
850 * Application can create number of steer rules, using the same
851 * tunnel, with different group id in each rule.
852 * Each tunnel stores its groups internally in PMD tunnel object.
853 * Groups used in regular rules do not belong to any tunnel and are stored
857 struct mlx5_flow_tunnel {
858 LIST_ENTRY(mlx5_flow_tunnel) chain;
859 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
860 uint32_t tunnel_id; /** unique tunnel ID */
862 struct rte_flow_action action;
863 struct rte_flow_item item;
864 struct mlx5_hlist *groups; /** tunnel groups */
867 /** PMD tunnel related context */
868 struct mlx5_flow_tunnel_hub {
870 * Access to the list MUST be MT protected
872 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
873 /* protect access to the tunnels list */
875 struct mlx5_hlist *groups; /** non tunnel groups */
878 /* convert jump group to flow table ID in tunnel rules */
879 struct tunnel_tbl_entry {
880 struct mlx5_hlist_entry hash;
886 static inline uint32_t
887 tunnel_id_to_flow_tbl(uint32_t id)
889 return id | (1u << 16);
892 static inline uint32_t
893 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
895 return flow_tbl & ~(1u << 16);
898 union tunnel_tbl_key {
906 static inline struct mlx5_flow_tunnel_hub *
907 mlx5_tunnel_hub(struct rte_eth_dev *dev)
909 struct mlx5_priv *priv = dev->data->dev_private;
910 return priv->sh->tunnel_hub;
914 is_tunnel_offload_active(struct rte_eth_dev *dev)
916 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
917 struct mlx5_priv *priv = dev->data->dev_private;
918 return !!priv->config.dv_miss_info;
926 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
927 __rte_unused const struct rte_flow_attr *attr,
928 __rte_unused const struct rte_flow_item items[],
929 __rte_unused const struct rte_flow_action actions[])
931 return (items[0].type == (typeof(items[0].type))
932 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
936 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
937 __rte_unused const struct rte_flow_attr *attr,
938 __rte_unused const struct rte_flow_item items[],
939 __rte_unused const struct rte_flow_action actions[])
941 return (actions[0].type == (typeof(actions[0].type))
942 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
945 static inline const struct mlx5_flow_tunnel *
946 flow_actions_to_tunnel(const struct rte_flow_action actions[])
948 return actions[0].conf;
951 static inline const struct mlx5_flow_tunnel *
952 flow_items_to_tunnel(const struct rte_flow_item items[])
954 return items[0].spec;
957 /* Flow structure. */
959 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
960 uint32_t dev_handles;
961 /**< Device flow handles that are part of the flow. */
962 uint32_t drv_type:2; /**< Driver type. */
964 uint32_t meter:24; /**< Holds flow meter id. */
965 uint32_t rix_mreg_copy;
966 /**< Index to metadata register copy table resource. */
967 uint32_t counter; /**< Holds flow counter. */
968 uint32_t tunnel_id; /**< Tunnel id */
969 uint32_t age; /**< Holds ASO age bit index. */
970 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
974 * Define list of valid combinations of RX Hash fields
975 * (see enum ibv_rx_hash_fields).
977 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
978 #define MLX5_RSS_HASH_IPV4_TCP \
979 (MLX5_RSS_HASH_IPV4 | \
980 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
981 #define MLX5_RSS_HASH_IPV4_UDP \
982 (MLX5_RSS_HASH_IPV4 | \
983 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
984 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
985 #define MLX5_RSS_HASH_IPV6_TCP \
986 (MLX5_RSS_HASH_IPV6 | \
987 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
988 #define MLX5_RSS_HASH_IPV6_UDP \
989 (MLX5_RSS_HASH_IPV6 | \
990 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
991 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
992 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
993 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
994 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
995 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
996 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
997 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
998 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
999 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1000 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1001 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1002 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1003 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1004 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1005 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1006 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1007 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1008 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1009 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1010 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1011 #define MLX5_RSS_HASH_NONE 0ULL
1013 /* array of valid combinations of RX Hash fields for RSS */
1014 static const uint64_t mlx5_rss_hash_fields[] = {
1016 MLX5_RSS_HASH_IPV4_TCP,
1017 MLX5_RSS_HASH_IPV4_UDP,
1019 MLX5_RSS_HASH_IPV6_TCP,
1020 MLX5_RSS_HASH_IPV6_UDP,
1024 /* Shared RSS action structure */
1025 struct mlx5_shared_action_rss {
1026 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1027 uint32_t refcnt; /**< Atomically accessed refcnt. */
1028 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1029 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1030 struct mlx5_ind_table_obj *ind_tbl;
1031 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1032 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1033 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1034 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1037 struct rte_flow_action_handle {
1041 /* Thread specific flow workspace intermediate data. */
1042 struct mlx5_flow_workspace {
1043 /* If creating another flow in same thread, push new as stack. */
1044 struct mlx5_flow_workspace *prev;
1045 struct mlx5_flow_workspace *next;
1046 uint32_t inuse; /* can't create new flow with current. */
1047 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1048 struct mlx5_flow_rss_desc rss_desc;
1049 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1050 uint32_t flow_idx; /* Intermediate device flow index. */
1051 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1052 uint32_t skip_matcher_reg:1;
1053 /* Indicates if need to skip matcher register in translate. */
1056 struct mlx5_flow_split_info {
1058 /**< True if flow is created by request external to PMD. */
1059 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1060 uint32_t flow_idx; /**< This memory pool index to the flow. */
1061 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1062 uint64_t prefix_layers; /**< Prefix subflow layers. */
1063 uint32_t table_id; /**< Flow table identifier. */
1066 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1067 const struct rte_flow_attr *attr,
1068 const struct rte_flow_item items[],
1069 const struct rte_flow_action actions[],
1072 struct rte_flow_error *error);
1073 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1074 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1075 const struct rte_flow_item items[],
1076 const struct rte_flow_action actions[], struct rte_flow_error *error);
1077 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1078 struct mlx5_flow *dev_flow,
1079 const struct rte_flow_attr *attr,
1080 const struct rte_flow_item items[],
1081 const struct rte_flow_action actions[],
1082 struct rte_flow_error *error);
1083 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1084 struct rte_flow_error *error);
1085 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1086 struct rte_flow *flow);
1087 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1088 struct rte_flow *flow);
1089 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1090 struct rte_flow *flow,
1091 const struct rte_flow_action *actions,
1093 struct rte_flow_error *error);
1094 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1095 struct mlx5_flow_meter_info *fm,
1097 uint8_t domain_bitmap);
1098 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1099 struct mlx5_flow_meter_info *fm);
1100 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1101 typedef struct mlx5_flow_meter_sub_policy *
1102 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1103 (struct rte_eth_dev *dev,
1104 struct mlx5_flow_meter_policy *mtr_policy,
1105 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1106 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1107 (struct rte_eth_dev *dev);
1108 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1110 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1111 (struct rte_eth_dev *dev);
1112 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1114 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1116 bool clear, uint64_t *pkts,
1118 typedef int (*mlx5_flow_get_aged_flows_t)
1119 (struct rte_eth_dev *dev,
1121 uint32_t nb_contexts,
1122 struct rte_flow_error *error);
1123 typedef int (*mlx5_flow_action_validate_t)
1124 (struct rte_eth_dev *dev,
1125 const struct rte_flow_indir_action_conf *conf,
1126 const struct rte_flow_action *action,
1127 struct rte_flow_error *error);
1128 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1129 (struct rte_eth_dev *dev,
1130 const struct rte_flow_indir_action_conf *conf,
1131 const struct rte_flow_action *action,
1132 struct rte_flow_error *error);
1133 typedef int (*mlx5_flow_action_destroy_t)
1134 (struct rte_eth_dev *dev,
1135 struct rte_flow_action_handle *action,
1136 struct rte_flow_error *error);
1137 typedef int (*mlx5_flow_action_update_t)
1138 (struct rte_eth_dev *dev,
1139 struct rte_flow_action_handle *action,
1141 struct rte_flow_error *error);
1142 typedef int (*mlx5_flow_action_query_t)
1143 (struct rte_eth_dev *dev,
1144 const struct rte_flow_action_handle *action,
1146 struct rte_flow_error *error);
1147 typedef int (*mlx5_flow_sync_domain_t)
1148 (struct rte_eth_dev *dev,
1151 typedef int (*mlx5_flow_validate_mtr_acts_t)
1152 (struct rte_eth_dev *dev,
1153 const struct rte_flow_action *actions[RTE_COLORS],
1154 struct rte_flow_attr *attr,
1156 uint8_t *domain_bitmap,
1157 bool *is_def_policy,
1158 struct rte_mtr_error *error);
1159 typedef int (*mlx5_flow_create_mtr_acts_t)
1160 (struct rte_eth_dev *dev,
1161 struct mlx5_flow_meter_policy *mtr_policy,
1162 const struct rte_flow_action *actions[RTE_COLORS],
1163 struct rte_mtr_error *error);
1164 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1165 (struct rte_eth_dev *dev,
1166 struct mlx5_flow_meter_policy *mtr_policy);
1167 typedef int (*mlx5_flow_create_policy_rules_t)
1168 (struct rte_eth_dev *dev,
1169 struct mlx5_flow_meter_policy *mtr_policy);
1170 typedef void (*mlx5_flow_destroy_policy_rules_t)
1171 (struct rte_eth_dev *dev,
1172 struct mlx5_flow_meter_policy *mtr_policy);
1173 typedef int (*mlx5_flow_create_def_policy_t)
1174 (struct rte_eth_dev *dev);
1175 typedef void (*mlx5_flow_destroy_def_policy_t)
1176 (struct rte_eth_dev *dev);
1178 struct mlx5_flow_driver_ops {
1179 mlx5_flow_validate_t validate;
1180 mlx5_flow_prepare_t prepare;
1181 mlx5_flow_translate_t translate;
1182 mlx5_flow_apply_t apply;
1183 mlx5_flow_remove_t remove;
1184 mlx5_flow_destroy_t destroy;
1185 mlx5_flow_query_t query;
1186 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1187 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1188 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1189 mlx5_flow_mtr_alloc_t create_meter;
1190 mlx5_flow_mtr_free_t free_meter;
1191 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1192 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1193 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1194 mlx5_flow_create_policy_rules_t create_policy_rules;
1195 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1196 mlx5_flow_create_def_policy_t create_def_policy;
1197 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1198 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1199 mlx5_flow_counter_alloc_t counter_alloc;
1200 mlx5_flow_counter_free_t counter_free;
1201 mlx5_flow_counter_query_t counter_query;
1202 mlx5_flow_get_aged_flows_t get_aged_flows;
1203 mlx5_flow_action_validate_t action_validate;
1204 mlx5_flow_action_create_t action_create;
1205 mlx5_flow_action_destroy_t action_destroy;
1206 mlx5_flow_action_update_t action_update;
1207 mlx5_flow_action_query_t action_query;
1208 mlx5_flow_sync_domain_t sync_domain;
1213 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1215 struct flow_grp_info {
1216 uint64_t external:1;
1217 uint64_t transfer:1;
1218 uint64_t fdb_def_rule:1;
1219 /* force standard group translation */
1220 uint64_t std_tbl_fix:1;
1221 uint64_t skip_scale:2;
1225 tunnel_use_standard_attr_group_translate
1226 (struct rte_eth_dev *dev,
1227 const struct mlx5_flow_tunnel *tunnel,
1228 const struct rte_flow_attr *attr,
1229 const struct rte_flow_item items[],
1230 const struct rte_flow_action actions[])
1234 if (!is_tunnel_offload_active(dev))
1235 /* no tunnel offload API */
1239 * OvS will use jump to group 0 in tunnel steer rule.
1240 * If tunnel steer rule starts from group 0 (attr.group == 0)
1241 * that 0 group must be translated with standard method.
1242 * attr.group == 0 in tunnel match rule translated with tunnel
1245 verdict = !attr->group &&
1246 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1249 * non-tunnel group translation uses standard method for
1250 * root group only: attr.group == 0
1252 verdict = !attr->group;
1259 * Get DV flow aso meter by index.
1262 * Pointer to the Ethernet device structure.
1264 * mlx5 flow aso meter index in the container.
1266 * mlx5 flow aso meter pool in the container,
1269 * Pointer to the aso meter, NULL otherwise.
1271 static inline struct mlx5_aso_mtr *
1272 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1274 struct mlx5_aso_mtr_pool *pool;
1275 struct mlx5_aso_mtr_pools_mng *pools_mng =
1276 &priv->sh->mtrmng->pools_mng;
1278 /* Decrease to original index. */
1280 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1281 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1282 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1285 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1286 const struct mlx5_flow_tunnel *tunnel,
1287 uint32_t group, uint32_t *table,
1288 const struct flow_grp_info *flags,
1289 struct rte_flow_error *error);
1290 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1291 int tunnel, uint64_t layer_types,
1292 uint64_t hash_fields);
1293 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1294 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1295 uint32_t subpriority);
1296 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1297 const struct rte_flow_attr *attr);
1298 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1299 const struct rte_flow_attr *attr,
1300 uint32_t subpriority);
1301 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1302 enum mlx5_feature_name feature,
1304 struct rte_flow_error *error);
1305 const struct rte_flow_action *mlx5_flow_find_action
1306 (const struct rte_flow_action *actions,
1307 enum rte_flow_action_type action);
1308 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1309 const struct rte_flow_action *action,
1310 struct rte_flow_error *error);
1311 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1312 const struct rte_flow_attr *attr,
1313 struct rte_flow_error *error);
1314 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1315 const struct rte_flow_attr *attr,
1316 struct rte_flow_error *error);
1317 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1318 const struct rte_flow_attr *attr,
1319 struct rte_flow_error *error);
1320 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1321 uint64_t action_flags,
1322 const struct rte_flow_attr *attr,
1323 struct rte_flow_error *error);
1324 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1325 uint64_t action_flags,
1326 struct rte_eth_dev *dev,
1327 const struct rte_flow_attr *attr,
1328 struct rte_flow_error *error);
1329 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1330 uint64_t action_flags,
1331 struct rte_eth_dev *dev,
1332 const struct rte_flow_attr *attr,
1333 uint64_t item_flags,
1334 struct rte_flow_error *error);
1335 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1336 const struct rte_flow_attr *attr,
1337 struct rte_flow_error *error);
1338 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1339 const struct rte_flow_attr *attributes,
1340 struct rte_flow_error *error);
1341 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1342 const uint8_t *mask,
1343 const uint8_t *nic_mask,
1345 bool range_accepted,
1346 struct rte_flow_error *error);
1347 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1348 uint64_t item_flags, bool ext_vlan_sup,
1349 struct rte_flow_error *error);
1350 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1351 uint64_t item_flags,
1352 uint8_t target_protocol,
1353 struct rte_flow_error *error);
1354 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1355 uint64_t item_flags,
1356 const struct rte_flow_item *gre_item,
1357 struct rte_flow_error *error);
1358 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1359 uint64_t item_flags,
1361 uint16_t ether_type,
1362 const struct rte_flow_item_ipv4 *acc_mask,
1363 bool range_accepted,
1364 struct rte_flow_error *error);
1365 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1366 uint64_t item_flags,
1368 uint16_t ether_type,
1369 const struct rte_flow_item_ipv6 *acc_mask,
1370 struct rte_flow_error *error);
1371 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1372 const struct rte_flow_item *item,
1373 uint64_t item_flags,
1374 uint64_t prev_layer,
1375 struct rte_flow_error *error);
1376 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1377 uint64_t item_flags,
1378 uint8_t target_protocol,
1379 const struct rte_flow_item_tcp *flow_mask,
1380 struct rte_flow_error *error);
1381 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1382 uint64_t item_flags,
1383 uint8_t target_protocol,
1384 struct rte_flow_error *error);
1385 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1386 uint64_t item_flags,
1387 struct rte_eth_dev *dev,
1388 struct rte_flow_error *error);
1389 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1390 uint64_t item_flags,
1391 struct rte_flow_error *error);
1392 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1393 uint64_t item_flags,
1394 struct rte_eth_dev *dev,
1395 struct rte_flow_error *error);
1396 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1397 uint64_t item_flags,
1398 uint8_t target_protocol,
1399 struct rte_flow_error *error);
1400 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1401 uint64_t item_flags,
1402 uint8_t target_protocol,
1403 struct rte_flow_error *error);
1404 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1405 uint64_t item_flags,
1406 uint8_t target_protocol,
1407 struct rte_flow_error *error);
1408 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1409 uint64_t item_flags,
1410 struct rte_eth_dev *dev,
1411 struct rte_flow_error *error);
1412 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1414 const struct rte_flow_item *geneve_item,
1415 struct rte_eth_dev *dev,
1416 struct rte_flow_error *error);
1417 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1418 uint64_t item_flags,
1420 uint16_t ether_type,
1421 const struct rte_flow_item_ecpri *acc_mask,
1422 struct rte_flow_error *error);
1423 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1424 struct mlx5_flow_meter_info *fm,
1426 uint8_t domain_bitmap);
1427 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1428 struct mlx5_flow_meter_info *fm);
1429 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1430 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1431 (struct rte_eth_dev *dev,
1432 struct mlx5_flow_meter_policy *mtr_policy,
1433 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1434 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1435 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1436 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1437 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1439 /* Hash list callbacks for flow tables: */
1440 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1441 uint64_t key, void *entry_ctx);
1442 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1443 struct mlx5_hlist_entry *entry, uint64_t key,
1445 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1446 struct mlx5_hlist_entry *entry);
1447 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1448 uint32_t table_level, uint8_t egress, uint8_t transfer,
1449 bool external, const struct mlx5_flow_tunnel *tunnel,
1450 uint32_t group_id, uint8_t dummy,
1451 uint32_t table_id, struct rte_flow_error *error);
1453 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1454 uint64_t key, void *cb_ctx);
1455 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1456 struct mlx5_hlist_entry *entry, uint64_t key,
1458 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1459 struct mlx5_hlist_entry *entry);
1461 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1462 struct mlx5_hlist_entry *entry,
1463 uint64_t key, void *cb_ctx);
1464 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1465 uint64_t key, void *ctx);
1466 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1467 struct mlx5_hlist_entry *entry);
1469 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1470 uint64_t key, void *ctx);
1471 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1472 struct mlx5_hlist_entry *entry, uint64_t key,
1474 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1475 struct mlx5_hlist_entry *entry);
1477 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1478 struct mlx5_hlist_entry *entry,
1479 uint64_t key, void *cb_ctx);
1480 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1481 uint64_t key, void *cb_ctx);
1482 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1483 struct mlx5_hlist_entry *entry);
1485 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1486 struct mlx5_cache_entry *entry, void *ctx);
1487 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1488 struct mlx5_cache_entry *entry, void *ctx);
1489 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1490 struct mlx5_cache_entry *entry);
1492 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1493 struct mlx5_cache_entry *entry, void *cb_ctx);
1494 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1495 struct mlx5_cache_entry *entry, void *cb_ctx);
1496 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1497 struct mlx5_cache_entry *entry);
1499 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1500 struct mlx5_cache_entry *entry, void *cb_ctx);
1501 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1502 (struct mlx5_cache_list *list,
1503 struct mlx5_cache_entry *entry, void *cb_ctx);
1504 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1505 struct mlx5_cache_entry *entry);
1507 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1508 struct mlx5_cache_entry *entry, void *cb_ctx);
1509 struct mlx5_cache_entry *flow_dv_sample_create_cb
1510 (struct mlx5_cache_list *list,
1511 struct mlx5_cache_entry *entry, void *cb_ctx);
1512 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1513 struct mlx5_cache_entry *entry);
1515 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1516 struct mlx5_cache_entry *entry, void *cb_ctx);
1517 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1518 (struct mlx5_cache_list *list,
1519 struct mlx5_cache_entry *entry, void *cb_ctx);
1520 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1521 struct mlx5_cache_entry *entry);
1522 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1524 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1525 const struct rte_flow_item *item,
1526 struct rte_flow_error *error);
1527 void flow_release_workspace(void *data);
1528 int mlx5_flow_os_init_workspace_once(void);
1529 void *mlx5_flow_os_get_specific_workspace(void);
1530 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1531 void mlx5_flow_os_release_workspace(void);
1532 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1533 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1534 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1535 const struct rte_flow_action *actions[RTE_COLORS],
1536 struct rte_flow_attr *attr,
1538 uint8_t *domain_bitmap,
1539 bool *is_def_policy,
1540 struct rte_mtr_error *error);
1541 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1542 struct mlx5_flow_meter_policy *mtr_policy);
1543 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1544 struct mlx5_flow_meter_policy *mtr_policy,
1545 const struct rte_flow_action *actions[RTE_COLORS],
1546 struct rte_mtr_error *error);
1547 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1548 struct mlx5_flow_meter_policy *mtr_policy);
1549 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1550 struct mlx5_flow_meter_policy *mtr_policy);
1551 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1552 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1553 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1554 struct mlx5_flow_handle *dev_handle);
1555 #endif /* RTE_PMD_MLX5_FLOW_H_ */