1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_alarm.h>
17 #include <mlx5_glue.h>
22 /* Private rte flow items. */
23 enum mlx5_rte_flow_item_type {
24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
25 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
38 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
39 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 #define MLX5_SHARED_ACTION_TYPE_OFFSET 30
45 MLX5_SHARED_ACTION_TYPE_RSS,
46 MLX5_SHARED_ACTION_TYPE_AGE,
49 /* Matches on selected register. */
50 struct mlx5_rte_flow_item_tag {
55 /* Modify selected register. */
56 struct mlx5_rte_flow_action_set_tag {
61 struct mlx5_flow_action_copy_mreg {
66 /* Matches on source queue. */
67 struct mlx5_rte_flow_item_tx_queue {
71 /* Feature name to allocate metadata register. */
72 enum mlx5_feature_name {
85 /* Default queue number. */
86 #define MLX5_RSSQ_DEFAULT_NUM 16
88 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
89 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
90 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
91 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
92 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
93 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
95 /* Pattern inner Layer bits. */
96 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
97 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
98 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
99 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
100 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
101 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
103 /* Pattern tunnel Layer bits. */
104 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
105 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
106 #define MLX5_FLOW_LAYER_GRE (1u << 14)
107 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
108 /* List of tunnel Layer bits continued below. */
110 /* General pattern items bits. */
111 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
112 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
113 #define MLX5_FLOW_ITEM_TAG (1u << 18)
114 #define MLX5_FLOW_ITEM_MARK (1u << 19)
116 /* Pattern MISC bits. */
117 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
118 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
119 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
121 /* Pattern tunnel Layer bits (continued). */
122 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
123 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
124 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
125 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
128 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
130 /* Pattern tunnel Layer bits (continued). */
131 #define MLX5_FLOW_LAYER_GTP (1u << 28)
133 /* Pattern eCPRI Layer bit. */
134 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
136 /* IPv6 Fragment Extension Header bit. */
137 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
138 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
141 #define MLX5_FLOW_LAYER_OUTER_L3 \
142 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
143 #define MLX5_FLOW_LAYER_OUTER_L4 \
144 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
145 #define MLX5_FLOW_LAYER_OUTER \
146 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
147 MLX5_FLOW_LAYER_OUTER_L4)
150 #define MLX5_FLOW_LAYER_TUNNEL \
151 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
152 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
153 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
154 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
157 #define MLX5_FLOW_LAYER_INNER_L3 \
158 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
159 #define MLX5_FLOW_LAYER_INNER_L4 \
160 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
161 #define MLX5_FLOW_LAYER_INNER \
162 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
163 MLX5_FLOW_LAYER_INNER_L4)
166 #define MLX5_FLOW_LAYER_L2 \
167 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
168 #define MLX5_FLOW_LAYER_L3_IPV4 \
169 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
170 #define MLX5_FLOW_LAYER_L3_IPV6 \
171 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
172 #define MLX5_FLOW_LAYER_L3 \
173 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
174 #define MLX5_FLOW_LAYER_L4 \
175 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
178 #define MLX5_FLOW_ACTION_DROP (1u << 0)
179 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
180 #define MLX5_FLOW_ACTION_RSS (1u << 2)
181 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
182 #define MLX5_FLOW_ACTION_MARK (1u << 4)
183 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
184 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
185 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
186 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
187 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
188 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
189 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
190 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
191 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
192 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
193 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
194 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
195 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
196 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
197 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
198 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
199 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
200 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
201 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
202 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
203 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
204 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
205 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
206 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
207 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
208 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
209 #define MLX5_FLOW_ACTION_METER (1ull << 31)
210 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
211 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
212 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
213 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
214 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
215 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
216 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
218 #define MLX5_FLOW_FATE_ACTIONS \
219 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
220 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
221 MLX5_FLOW_ACTION_DEFAULT_MISS)
223 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
224 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
225 MLX5_FLOW_ACTION_JUMP)
228 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
229 MLX5_FLOW_ACTION_SET_IPV4_DST | \
230 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
231 MLX5_FLOW_ACTION_SET_IPV6_DST | \
232 MLX5_FLOW_ACTION_SET_TP_SRC | \
233 MLX5_FLOW_ACTION_SET_TP_DST | \
234 MLX5_FLOW_ACTION_SET_TTL | \
235 MLX5_FLOW_ACTION_DEC_TTL | \
236 MLX5_FLOW_ACTION_SET_MAC_SRC | \
237 MLX5_FLOW_ACTION_SET_MAC_DST | \
238 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
239 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
240 MLX5_FLOW_ACTION_INC_TCP_ACK | \
241 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
242 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
243 MLX5_FLOW_ACTION_SET_TAG | \
244 MLX5_FLOW_ACTION_MARK_EXT | \
245 MLX5_FLOW_ACTION_SET_META | \
246 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
247 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
249 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
250 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
252 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
255 #define IPPROTO_MPLS 137
258 /* UDP port number for MPLS */
259 #define MLX5_UDP_PORT_MPLS 6635
261 /* UDP port numbers for VxLAN. */
262 #define MLX5_UDP_PORT_VXLAN 4789
263 #define MLX5_UDP_PORT_VXLAN_GPE 4790
265 /* UDP port numbers for GENEVE. */
266 #define MLX5_UDP_PORT_GENEVE 6081
268 /* Priority reserved for default flows. */
269 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
272 * Number of sub priorities.
273 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
274 * matching on the NIC (firmware dependent) L4 most have the higher priority
275 * followed by L3 and ending with L2.
277 #define MLX5_PRIORITY_MAP_L2 2
278 #define MLX5_PRIORITY_MAP_L3 1
279 #define MLX5_PRIORITY_MAP_L4 0
280 #define MLX5_PRIORITY_MAP_MAX 3
282 /* Valid layer type for IPV4 RSS. */
283 #define MLX5_IPV4_LAYER_TYPES \
284 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
285 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
286 ETH_RSS_NONFRAG_IPV4_OTHER)
288 /* IBV hash source bits for IPV4. */
289 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
291 /* Valid layer type for IPV6 RSS. */
292 #define MLX5_IPV6_LAYER_TYPES \
293 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
294 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
295 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
297 /* IBV hash source bits for IPV6. */
298 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
300 /* IBV hash bits for L3 SRC. */
301 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
303 /* IBV hash bits for L3 DST. */
304 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
306 /* IBV hash bits for TCP. */
307 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
308 IBV_RX_HASH_DST_PORT_TCP)
310 /* IBV hash bits for UDP. */
311 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
312 IBV_RX_HASH_DST_PORT_UDP)
314 /* IBV hash bits for L4 SRC. */
315 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
316 IBV_RX_HASH_SRC_PORT_UDP)
318 /* IBV hash bits for L4 DST. */
319 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
320 IBV_RX_HASH_DST_PORT_UDP)
322 /* Geneve header first 16Bit */
323 #define MLX5_GENEVE_VER_MASK 0x3
324 #define MLX5_GENEVE_VER_SHIFT 14
325 #define MLX5_GENEVE_VER_VAL(a) \
326 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
327 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
328 #define MLX5_GENEVE_OPTLEN_SHIFT 7
329 #define MLX5_GENEVE_OPTLEN_VAL(a) \
330 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
331 #define MLX5_GENEVE_OAMF_MASK 0x1
332 #define MLX5_GENEVE_OAMF_SHIFT 7
333 #define MLX5_GENEVE_OAMF_VAL(a) \
334 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
335 #define MLX5_GENEVE_CRITO_MASK 0x1
336 #define MLX5_GENEVE_CRITO_SHIFT 6
337 #define MLX5_GENEVE_CRITO_VAL(a) \
338 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
339 #define MLX5_GENEVE_RSVD_MASK 0x3F
340 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
342 * The length of the Geneve options fields, expressed in four byte multiples,
343 * not including the eight byte fixed tunnel.
345 #define MLX5_GENEVE_OPT_LEN_0 14
346 #define MLX5_GENEVE_OPT_LEN_1 63
348 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
349 sizeof(struct rte_flow_item_ipv4))
351 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
352 #define MLX5_IPV4_FRAG_OFFSET_MASK \
353 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
355 /* Specific item's fields can accept a range of values (using spec and last). */
356 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
357 #define MLX5_ITEM_RANGE_ACCEPTED true
359 /* Software header modify action numbers of a flow. */
360 #define MLX5_ACT_NUM_MDF_IPV4 1
361 #define MLX5_ACT_NUM_MDF_IPV6 4
362 #define MLX5_ACT_NUM_MDF_MAC 2
363 #define MLX5_ACT_NUM_MDF_VID 1
364 #define MLX5_ACT_NUM_MDF_PORT 2
365 #define MLX5_ACT_NUM_MDF_TTL 1
366 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
367 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
368 #define MLX5_ACT_NUM_MDF_TCPACK 1
369 #define MLX5_ACT_NUM_SET_REG 1
370 #define MLX5_ACT_NUM_SET_TAG 1
371 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
372 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
373 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
374 #define MLX5_ACT_NUM_SET_DSCP 1
376 enum mlx5_flow_drv_type {
379 MLX5_FLOW_TYPE_VERBS,
383 /* Fate action type. */
384 enum mlx5_flow_fate_type {
385 MLX5_FLOW_FATE_NONE, /* Egress flow. */
386 MLX5_FLOW_FATE_QUEUE,
388 MLX5_FLOW_FATE_PORT_ID,
390 MLX5_FLOW_FATE_DEFAULT_MISS,
394 /* Matcher PRM representation */
395 struct mlx5_flow_dv_match_params {
397 /**< Size of match value. Do NOT split size and key! */
398 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
399 /**< Matcher value. This value is used as the mask or as a key. */
402 /* Matcher structure. */
403 struct mlx5_flow_dv_matcher {
404 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
405 struct mlx5_flow_tbl_resource *tbl;
406 /**< Pointer to the table(group) the matcher associated with. */
407 void *matcher_object; /**< Pointer to DV matcher */
408 uint16_t crc; /**< CRC of key. */
409 uint16_t priority; /**< Priority of matcher. */
410 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
413 #define MLX5_ENCAP_MAX_LEN 132
415 /* Encap/decap resource key of the hash organization. */
416 union mlx5_flow_encap_decap_key {
418 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
419 uint32_t refmt_type:8; /**< Header reformat type. */
420 uint32_t buf_size:8; /**< Encap buf size. */
421 uint32_t table_level:8; /**< Root table or not. */
422 uint32_t cksum; /**< Encap buf check sum. */
424 uint64_t v64; /**< full 64bits value of key */
427 /* Encap/decap resource structure. */
428 struct mlx5_flow_dv_encap_decap_resource {
429 struct mlx5_hlist_entry entry;
430 /* Pointer to next element. */
431 uint32_t refcnt; /**< Reference counter. */
433 /**< Encap/decap action object. */
434 uint8_t buf[MLX5_ENCAP_MAX_LEN];
436 uint8_t reformat_type;
438 uint64_t flags; /**< Flags for RDMA API. */
439 uint32_t idx; /**< Index for the index memory pool. */
442 /* Tag resource structure. */
443 struct mlx5_flow_dv_tag_resource {
444 struct mlx5_hlist_entry entry;
445 /**< hash list entry for tag resource, tag value as the key. */
447 /**< Tag action object. */
448 uint32_t refcnt; /**< Reference counter. */
449 uint32_t idx; /**< Index for the index memory pool. */
453 * Number of modification commands.
454 * The maximal actions amount in FW is some constant, and it is 16 in the
455 * latest releases. In some old releases, it will be limited to 8.
456 * Since there is no interface to query the capacity, the maximal value should
457 * be used to allow PMD to create the flow. The validation will be done in the
458 * lower driver layer or FW. A failure will be returned if exceeds the maximal
459 * supported actions number on the root table.
460 * On non-root tables, there is no limitation, but 32 is enough right now.
462 #define MLX5_MAX_MODIFY_NUM 32
463 #define MLX5_ROOT_TBL_MODIFY_NUM 16
465 /* Modify resource structure */
466 struct mlx5_flow_dv_modify_hdr_resource {
467 struct mlx5_hlist_entry entry;
468 void *action; /**< Modify header action object. */
469 /* Key area for hash list matching: */
470 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
471 uint32_t actions_num; /**< Number of modification actions. */
472 uint64_t flags; /**< Flags for RDMA API. */
473 struct mlx5_modification_cmd actions[];
474 /**< Modification actions. */
477 /* Modify resource key of the hash organization. */
478 union mlx5_flow_modify_hdr_key {
480 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
481 uint32_t actions_num:5; /**< Number of modification actions. */
482 uint32_t group:19; /**< Flow group id. */
483 uint32_t cksum; /**< Actions check sum. */
485 uint64_t v64; /**< full 64bits value of key */
488 /* Jump action resource structure. */
489 struct mlx5_flow_dv_jump_tbl_resource {
490 void *action; /**< Pointer to the rdma core action. */
493 /* Port ID resource structure. */
494 struct mlx5_flow_dv_port_id_action_resource {
495 struct mlx5_cache_entry entry;
496 void *action; /**< Action object. */
497 uint32_t port_id; /**< Port ID value. */
498 uint32_t idx; /**< Indexed pool memory index. */
501 /* Push VLAN action resource structure */
502 struct mlx5_flow_dv_push_vlan_action_resource {
503 struct mlx5_cache_entry entry; /* Cache entry. */
504 void *action; /**< Action object. */
505 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
506 rte_be32_t vlan_tag; /**< VLAN tag value. */
507 uint32_t idx; /**< Indexed pool memory index. */
510 /* Metadata register copy table entry. */
511 struct mlx5_flow_mreg_copy_resource {
513 * Hash list entry for copy table.
514 * - Key is 32/64-bit MARK action ID.
515 * - MUST be the first entry.
517 struct mlx5_hlist_entry hlist_ent;
518 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
519 /* List entry for device flows. */
521 uint32_t rix_flow; /* Built flow for copy. */
524 /* Table tunnel parameter. */
525 struct mlx5_flow_tbl_tunnel_prm {
526 const struct mlx5_flow_tunnel *tunnel;
531 /* Table data structure of the hash organization. */
532 struct mlx5_flow_tbl_data_entry {
533 struct mlx5_hlist_entry entry;
534 /**< hash list entry, 64-bits key inside. */
535 struct mlx5_flow_tbl_resource tbl;
536 /**< flow table resource. */
537 struct mlx5_cache_list matchers;
538 /**< matchers' header associated with the flow table. */
539 struct mlx5_flow_dv_jump_tbl_resource jump;
540 /**< jump resource, at most one for each table created. */
541 uint32_t idx; /**< index for the indexed mempool. */
542 /**< tunnel offload */
543 const struct mlx5_flow_tunnel *tunnel;
546 bool tunnel_offload; /* Tunnel offlod table or not. */
547 bool is_egress; /**< Egress table. */
550 /* Sub rdma-core actions list. */
551 struct mlx5_flow_sub_actions_list {
552 uint32_t actions_num; /**< Number of sample actions. */
553 uint64_t action_flags;
554 void *dr_queue_action;
557 void *dr_port_id_action;
558 void *dr_encap_action;
561 /* Sample sub-actions resource list. */
562 struct mlx5_flow_sub_actions_idx {
563 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
564 uint32_t rix_tag; /**< Index to the tag action. */
566 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
567 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
570 /* Sample action resource structure. */
571 struct mlx5_flow_dv_sample_resource {
572 struct mlx5_cache_entry entry; /**< Cache entry. */
574 void *verbs_action; /**< Verbs sample action object. */
575 void **sub_actions; /**< Sample sub-action array. */
577 uint32_t idx; /** Sample object index. */
578 uint8_t ft_type; /** Flow Table Type */
579 uint32_t ft_id; /** Flow Table Level */
580 uint32_t ratio; /** Sample Ratio */
581 uint64_t set_action; /** Restore reg_c0 value */
582 void *normal_path_tbl; /** Flow Table pointer */
583 void *default_miss; /** default_miss dr_action. */
584 struct mlx5_flow_sub_actions_idx sample_idx;
585 /**< Action index resources. */
586 struct mlx5_flow_sub_actions_list sample_act;
587 /**< Action resources. */
590 #define MLX5_MAX_DEST_NUM 2
592 /* Destination array action resource structure. */
593 struct mlx5_flow_dv_dest_array_resource {
594 struct mlx5_cache_entry entry; /**< Cache entry. */
595 uint32_t idx; /** Destination array action object index. */
596 uint8_t ft_type; /** Flow Table Type */
597 uint8_t num_of_dest; /**< Number of destination actions. */
598 void *action; /**< Pointer to the rdma core action. */
599 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
600 /**< Action index resources. */
601 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
602 /**< Action resources. */
605 /* Verbs specification header. */
606 struct ibv_spec_header {
607 enum ibv_flow_spec_type type;
611 /* PMD flow priority for tunnel */
612 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
613 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
616 /** Device flow handle structure for DV mode only. */
617 struct mlx5_flow_handle_dv {
619 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
620 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
621 /**< Pointer to modify header resource in cache. */
622 uint32_t rix_encap_decap;
623 /**< Index to encap/decap resource in cache. */
624 uint32_t rix_push_vlan;
625 /**< Index to push VLAN action resource in cache. */
627 /**< Index to the tag action. */
629 /**< Index to sample action resource in cache. */
630 uint32_t rix_dest_array;
631 /**< Index to destination array resource in cache. */
634 /** Device flow handle structure: used both for creating & destroying. */
635 struct mlx5_flow_handle {
636 SILIST_ENTRY(uint32_t)next;
637 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
638 /**< Index to next device flow handle. */
640 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
641 void *drv_flow; /**< pointer to driver flow object. */
642 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
643 uint32_t mark:1; /**< Metadate rxq mark flag. */
644 uint32_t fate_action:3; /**< Fate action type. */
646 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
647 uint32_t rix_jump; /**< Index to the jump action resource. */
648 uint32_t rix_port_id_action;
649 /**< Index to port ID action resource. */
651 /**< Generic value indicates the fate action. */
652 uint32_t rix_default_fate;
653 /**< Indicates default miss fate action. */
655 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
656 struct mlx5_flow_handle_dv dvh;
661 * Size for Verbs device flow handle structure only. Do not use the DV only
662 * structure in Verbs. No DV flows attributes will be accessed.
663 * Macro offsetof() could also be used here.
665 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
666 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
667 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
669 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
673 * Max number of actions per DV flow.
674 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
675 * in rdma-core file providers/mlx5/verbs.c.
677 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
679 /** Device flow structure only for DV flow creation. */
680 struct mlx5_flow_dv_workspace {
681 uint32_t group; /**< The group index. */
682 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
683 int actions_n; /**< number of actions. */
684 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
685 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
686 /**< Pointer to encap/decap resource in cache. */
687 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
688 /**< Pointer to push VLAN action resource in cache. */
689 struct mlx5_flow_dv_tag_resource *tag_resource;
690 /**< pointer to the tag action. */
691 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
692 /**< Pointer to port ID action resource. */
693 struct mlx5_flow_dv_jump_tbl_resource *jump;
694 /**< Pointer to the jump action resource. */
695 struct mlx5_flow_dv_match_params value;
696 /**< Holds the value that the packet is compared to. */
697 struct mlx5_flow_dv_sample_resource *sample_res;
698 /**< Pointer to the sample action resource. */
699 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
700 /**< Pointer to the destination array resource. */
704 * Maximal Verbs flow specifications & actions size.
705 * Some elements are mutually exclusive, but enough space should be allocated.
706 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
707 * 2. One tunnel header (exception: GRE + MPLS),
708 * SPEC length: GRE == tunnel.
709 * Actions: 1. 1 Mark OR Flag.
710 * 2. 1 Drop (if any).
711 * 3. No limitation for counters, but it makes no sense to support too
712 * many counters in a single device flow.
714 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
715 #define MLX5_VERBS_MAX_SPEC_SIZE \
717 (2 * (sizeof(struct ibv_flow_spec_eth) + \
718 sizeof(struct ibv_flow_spec_ipv6) + \
719 sizeof(struct ibv_flow_spec_tcp_udp)) + \
720 sizeof(struct ibv_flow_spec_gre) + \
721 sizeof(struct ibv_flow_spec_mpls)) \
724 #define MLX5_VERBS_MAX_SPEC_SIZE \
726 (2 * (sizeof(struct ibv_flow_spec_eth) + \
727 sizeof(struct ibv_flow_spec_ipv6) + \
728 sizeof(struct ibv_flow_spec_tcp_udp)) + \
729 sizeof(struct ibv_flow_spec_tunnel)) \
733 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
734 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
735 #define MLX5_VERBS_MAX_ACT_SIZE \
737 sizeof(struct ibv_flow_spec_action_tag) + \
738 sizeof(struct ibv_flow_spec_action_drop) + \
739 sizeof(struct ibv_flow_spec_counter_action) * 4 \
742 #define MLX5_VERBS_MAX_ACT_SIZE \
744 sizeof(struct ibv_flow_spec_action_tag) + \
745 sizeof(struct ibv_flow_spec_action_drop) \
749 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
750 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
752 /** Device flow structure only for Verbs flow creation. */
753 struct mlx5_flow_verbs_workspace {
754 unsigned int size; /**< Size of the attribute. */
755 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
756 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
757 /**< Specifications & actions buffer of verbs flow. */
760 /** Maximal number of device sub-flows supported. */
761 #define MLX5_NUM_MAX_DEV_FLOWS 32
763 /** Device flow structure. */
765 struct rte_flow *flow; /**< Pointer to the main flow. */
766 uint32_t flow_idx; /**< The memory pool index to the main flow. */
767 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
769 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
770 bool external; /**< true if the flow is created external to PMD. */
771 uint8_t ingress; /**< 1 if the flow is ingress. */
773 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
774 struct mlx5_flow_dv_workspace dv;
776 struct mlx5_flow_verbs_workspace verbs;
778 struct mlx5_flow_handle *handle;
779 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
780 const struct mlx5_flow_tunnel *tunnel;
783 /* Flow meter state. */
784 #define MLX5_FLOW_METER_DISABLE 0
785 #define MLX5_FLOW_METER_ENABLE 1
787 #define MLX5_MAN_WIDTH 8
788 /* Modify this value if enum rte_mtr_color changes. */
789 #define RTE_MTR_DROPPED RTE_COLORS
791 /* Meter policer statistics */
792 struct mlx5_flow_policer_stats {
793 uint32_t cnt[RTE_COLORS + 1];
794 /**< Color counter, extra for drop. */
796 /**< Statistics mask for the colors. */
799 /* Meter table structure. */
800 struct mlx5_meter_domain_info {
801 struct mlx5_flow_tbl_resource *tbl;
803 struct mlx5_flow_tbl_resource *sfx_tbl;
804 /**< Meter suffix table. */
806 /**< Meter color not match default criteria. */
808 /**< Meter color match criteria. */
810 /**< Meter match action. */
811 void *policer_rules[RTE_MTR_DROPPED + 1];
812 /**< Meter policer for the match. */
815 /* Meter table set for TX RX FDB. */
816 struct mlx5_meter_domains_infos {
818 /**< Table user count. */
819 struct mlx5_meter_domain_info egress;
820 /**< TX meter table. */
821 struct mlx5_meter_domain_info ingress;
822 /**< RX meter table. */
823 struct mlx5_meter_domain_info transfer;
824 /**< FDB meter table. */
826 /**< Drop action as not matched. */
827 void *count_actns[RTE_MTR_DROPPED + 1];
828 /**< Counters for match and unmatched statistics. */
829 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
830 /**< Flow meter parameter. */
832 /**< Flow meter parameter size. */
834 /**< Flow meter action. */
837 /* Meter parameter structure. */
838 struct mlx5_flow_meter {
839 TAILQ_ENTRY(mlx5_flow_meter) next;
840 /**< Pointer to the next flow meter structure. */
841 uint32_t idx; /* Index to meter object. */
844 struct mlx5_flow_meter_profile *profile;
845 /**< Meter profile parameters. */
847 rte_spinlock_t sl; /**< Meter action spinlock. */
849 /** Policer actions (per meter output color). */
850 enum rte_mtr_policer_action action[RTE_COLORS];
852 /** Set of stats counters to be enabled.
853 * @see enum rte_mtr_stats_type
857 /**< Rule applies to ingress traffic. */
860 /**< Rule applies to egress traffic. */
863 * Instead of simply matching the properties of traffic as it would
864 * appear on a given DPDK port ID, enabling this attribute transfers
865 * a flow rule to the lowest possible level of any device endpoints
866 * found in the pattern.
868 * When supported, this effectively enables an application to
869 * re-route traffic not necessarily intended for it (e.g. coming
870 * from or addressed to different physical ports, VFs or
871 * applications) at the device level.
873 * It complements the behavior of some pattern items such as
874 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
876 * When transferring flow rules, ingress and egress attributes keep
877 * their original meaning, as if processing traffic emitted or
878 * received by the application.
881 struct mlx5_meter_domains_infos *mfts;
882 /**< Flow table created for this meter. */
883 struct mlx5_flow_policer_stats policer_stats;
884 /**< Meter policer statistics. */
887 uint32_t active_state:1;
890 /**< Meter shared or not. */
893 /* RFC2697 parameter structure. */
894 struct mlx5_flow_meter_srtcm_rfc2697_prm {
895 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
896 uint32_t cbs_exponent:5;
897 uint32_t cbs_mantissa:8;
898 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
899 uint32_t cir_exponent:5;
900 uint32_t cir_mantissa:8;
901 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
902 uint32_t ebs_exponent:5;
903 uint32_t ebs_mantissa:8;
906 /* Flow meter profile structure. */
907 struct mlx5_flow_meter_profile {
908 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
909 /**< Pointer to the next flow meter structure. */
910 uint32_t meter_profile_id; /**< Profile id. */
911 struct rte_mtr_meter_profile profile; /**< Profile detail. */
913 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
914 /**< srtcm_rfc2697 struct. */
916 uint32_t ref_cnt; /**< Use count. */
919 #define MLX5_MAX_TUNNELS 256
920 #define MLX5_TNL_MISS_RULE_PRIORITY 3
921 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
924 * When tunnel offload is active, all JUMP group ids are converted
925 * using the same method. That conversion is applied both to tunnel and
926 * regular rule types.
927 * Group ids used in tunnel rules are relative to it's tunnel (!).
928 * Application can create number of steer rules, using the same
929 * tunnel, with different group id in each rule.
930 * Each tunnel stores its groups internally in PMD tunnel object.
931 * Groups used in regular rules do not belong to any tunnel and are stored
935 struct mlx5_flow_tunnel {
936 LIST_ENTRY(mlx5_flow_tunnel) chain;
937 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
938 uint32_t tunnel_id; /** unique tunnel ID */
940 struct rte_flow_action action;
941 struct rte_flow_item item;
942 struct mlx5_hlist *groups; /** tunnel groups */
945 /** PMD tunnel related context */
946 struct mlx5_flow_tunnel_hub {
947 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
948 rte_spinlock_t sl; /* Tunnel list spinlock. */
949 struct mlx5_hlist *groups; /** non tunnel groups */
952 /* convert jump group to flow table ID in tunnel rules */
953 struct tunnel_tbl_entry {
954 struct mlx5_hlist_entry hash;
958 static inline uint32_t
959 tunnel_id_to_flow_tbl(uint32_t id)
961 return id | (1u << 16);
964 static inline uint32_t
965 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
967 return flow_tbl & ~(1u << 16);
970 union tunnel_tbl_key {
978 static inline struct mlx5_flow_tunnel_hub *
979 mlx5_tunnel_hub(struct rte_eth_dev *dev)
981 struct mlx5_priv *priv = dev->data->dev_private;
982 return priv->sh->tunnel_hub;
986 is_tunnel_offload_active(struct rte_eth_dev *dev)
988 struct mlx5_priv *priv = dev->data->dev_private;
989 return !!priv->config.dv_miss_info;
993 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
994 __rte_unused const struct rte_flow_attr *attr,
995 __rte_unused const struct rte_flow_item items[],
996 __rte_unused const struct rte_flow_action actions[])
998 return (items[0].type == (typeof(items[0].type))
999 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1003 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1004 __rte_unused const struct rte_flow_attr *attr,
1005 __rte_unused const struct rte_flow_item items[],
1006 __rte_unused const struct rte_flow_action actions[])
1008 return (actions[0].type == (typeof(actions[0].type))
1009 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1012 static inline const struct mlx5_flow_tunnel *
1013 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1015 return actions[0].conf;
1018 static inline const struct mlx5_flow_tunnel *
1019 flow_items_to_tunnel(const struct rte_flow_item items[])
1021 return items[0].spec;
1024 /* Flow structure. */
1026 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1027 uint32_t shared_rss; /** < Shared RSS action ID. */
1028 uint32_t dev_handles;
1029 /**< Device flow handles that are part of the flow. */
1030 uint32_t drv_type:2; /**< Driver type. */
1032 uint32_t meter:16; /**< Holds flow meter id. */
1033 uint32_t rix_mreg_copy;
1034 /**< Index to metadata register copy table resource. */
1035 uint32_t counter; /**< Holds flow counter. */
1036 uint32_t tunnel_id; /**< Tunnel id */
1037 uint32_t age; /**< Holds ASO age bit index. */
1041 * Define list of valid combinations of RX Hash fields
1042 * (see enum ibv_rx_hash_fields).
1044 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1045 #define MLX5_RSS_HASH_IPV4_TCP \
1046 (MLX5_RSS_HASH_IPV4 | \
1047 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1048 #define MLX5_RSS_HASH_IPV4_UDP \
1049 (MLX5_RSS_HASH_IPV4 | \
1050 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1051 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1052 #define MLX5_RSS_HASH_IPV6_TCP \
1053 (MLX5_RSS_HASH_IPV6 | \
1054 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1055 #define MLX5_RSS_HASH_IPV6_UDP \
1056 (MLX5_RSS_HASH_IPV6 | \
1057 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1058 #define MLX5_RSS_HASH_NONE 0ULL
1060 /* array of valid combinations of RX Hash fields for RSS */
1061 static const uint64_t mlx5_rss_hash_fields[] = {
1063 MLX5_RSS_HASH_IPV4_TCP,
1064 MLX5_RSS_HASH_IPV4_UDP,
1066 MLX5_RSS_HASH_IPV6_TCP,
1067 MLX5_RSS_HASH_IPV6_UDP,
1071 /* Shared RSS action structure */
1072 struct mlx5_shared_action_rss {
1073 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1074 uint32_t refcnt; /**< Atomically accessed refcnt. */
1075 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1076 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1077 uint16_t *queue; /**< Queue indices to use. */
1078 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1079 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1080 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
1081 /**< Hash RX queue indexes for tunneled RSS */
1084 struct rte_flow_shared_action {
1088 /* Thread specific flow workspace intermediate data. */
1089 struct mlx5_flow_workspace {
1090 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1091 struct mlx5_flow_rss_desc rss_desc[2];
1092 uint32_t rssq_num[2]; /* Allocated queue num in rss_desc. */
1093 int flow_idx; /* Intermediate device flow index. */
1094 int flow_nested_idx; /* Intermediate device flow index, nested. */
1097 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1098 const struct rte_flow_attr *attr,
1099 const struct rte_flow_item items[],
1100 const struct rte_flow_action actions[],
1103 struct rte_flow_error *error);
1104 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1105 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1106 const struct rte_flow_item items[],
1107 const struct rte_flow_action actions[], struct rte_flow_error *error);
1108 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1109 struct mlx5_flow *dev_flow,
1110 const struct rte_flow_attr *attr,
1111 const struct rte_flow_item items[],
1112 const struct rte_flow_action actions[],
1113 struct rte_flow_error *error);
1114 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1115 struct rte_flow_error *error);
1116 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1117 struct rte_flow *flow);
1118 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1119 struct rte_flow *flow);
1120 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1121 struct rte_flow *flow,
1122 const struct rte_flow_action *actions,
1124 struct rte_flow_error *error);
1125 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1126 (struct rte_eth_dev *dev,
1127 const struct mlx5_flow_meter *fm);
1128 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1129 struct mlx5_meter_domains_infos *tbls);
1130 typedef int (*mlx5_flow_create_policer_rules_t)
1131 (struct rte_eth_dev *dev,
1132 struct mlx5_flow_meter *fm,
1133 const struct rte_flow_attr *attr);
1134 typedef int (*mlx5_flow_destroy_policer_rules_t)
1135 (struct rte_eth_dev *dev,
1136 const struct mlx5_flow_meter *fm,
1137 const struct rte_flow_attr *attr);
1138 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1139 (struct rte_eth_dev *dev);
1140 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1142 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1144 bool clear, uint64_t *pkts,
1146 typedef int (*mlx5_flow_get_aged_flows_t)
1147 (struct rte_eth_dev *dev,
1149 uint32_t nb_contexts,
1150 struct rte_flow_error *error);
1151 typedef int (*mlx5_flow_action_validate_t)
1152 (struct rte_eth_dev *dev,
1153 const struct rte_flow_shared_action_conf *conf,
1154 const struct rte_flow_action *action,
1155 struct rte_flow_error *error);
1156 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1157 (struct rte_eth_dev *dev,
1158 const struct rte_flow_shared_action_conf *conf,
1159 const struct rte_flow_action *action,
1160 struct rte_flow_error *error);
1161 typedef int (*mlx5_flow_action_destroy_t)
1162 (struct rte_eth_dev *dev,
1163 struct rte_flow_shared_action *action,
1164 struct rte_flow_error *error);
1165 typedef int (*mlx5_flow_action_update_t)
1166 (struct rte_eth_dev *dev,
1167 struct rte_flow_shared_action *action,
1168 const void *action_conf,
1169 struct rte_flow_error *error);
1170 typedef int (*mlx5_flow_action_query_t)
1171 (struct rte_eth_dev *dev,
1172 const struct rte_flow_shared_action *action,
1174 struct rte_flow_error *error);
1175 typedef int (*mlx5_flow_sync_domain_t)
1176 (struct rte_eth_dev *dev,
1180 struct mlx5_flow_driver_ops {
1181 mlx5_flow_validate_t validate;
1182 mlx5_flow_prepare_t prepare;
1183 mlx5_flow_translate_t translate;
1184 mlx5_flow_apply_t apply;
1185 mlx5_flow_remove_t remove;
1186 mlx5_flow_destroy_t destroy;
1187 mlx5_flow_query_t query;
1188 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1189 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1190 mlx5_flow_create_policer_rules_t create_policer_rules;
1191 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1192 mlx5_flow_counter_alloc_t counter_alloc;
1193 mlx5_flow_counter_free_t counter_free;
1194 mlx5_flow_counter_query_t counter_query;
1195 mlx5_flow_get_aged_flows_t get_aged_flows;
1196 mlx5_flow_action_validate_t action_validate;
1197 mlx5_flow_action_create_t action_create;
1198 mlx5_flow_action_destroy_t action_destroy;
1199 mlx5_flow_action_update_t action_update;
1200 mlx5_flow_action_query_t action_query;
1201 mlx5_flow_sync_domain_t sync_domain;
1206 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1208 struct flow_grp_info {
1209 uint64_t external:1;
1210 uint64_t transfer:1;
1211 uint64_t fdb_def_rule:1;
1212 /* force standard group translation */
1213 uint64_t std_tbl_fix:1;
1217 tunnel_use_standard_attr_group_translate
1218 (struct rte_eth_dev *dev,
1219 const struct mlx5_flow_tunnel *tunnel,
1220 const struct rte_flow_attr *attr,
1221 const struct rte_flow_item items[],
1222 const struct rte_flow_action actions[])
1226 if (!is_tunnel_offload_active(dev))
1227 /* no tunnel offload API */
1231 * OvS will use jump to group 0 in tunnel steer rule.
1232 * If tunnel steer rule starts from group 0 (attr.group == 0)
1233 * that 0 group must be translated with standard method.
1234 * attr.group == 0 in tunnel match rule translated with tunnel
1237 verdict = !attr->group &&
1238 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1241 * non-tunnel group translation uses standard method for
1242 * root group only: attr.group == 0
1244 verdict = !attr->group;
1250 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1251 const struct mlx5_flow_tunnel *tunnel,
1252 uint32_t group, uint32_t *table,
1253 struct flow_grp_info flags,
1254 struct rte_flow_error *error);
1255 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1256 int tunnel, uint64_t layer_types,
1257 uint64_t hash_fields);
1258 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1259 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1260 uint32_t subpriority);
1261 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1262 enum mlx5_feature_name feature,
1264 struct rte_flow_error *error);
1265 const struct rte_flow_action *mlx5_flow_find_action
1266 (const struct rte_flow_action *actions,
1267 enum rte_flow_action_type action);
1268 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1269 const struct rte_flow_action *action,
1270 struct rte_flow_error *error);
1271 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1272 const struct rte_flow_attr *attr,
1273 struct rte_flow_error *error);
1274 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1275 const struct rte_flow_attr *attr,
1276 struct rte_flow_error *error);
1277 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1278 const struct rte_flow_attr *attr,
1279 struct rte_flow_error *error);
1280 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1281 uint64_t action_flags,
1282 const struct rte_flow_attr *attr,
1283 struct rte_flow_error *error);
1284 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1285 uint64_t action_flags,
1286 struct rte_eth_dev *dev,
1287 const struct rte_flow_attr *attr,
1288 struct rte_flow_error *error);
1289 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1290 uint64_t action_flags,
1291 struct rte_eth_dev *dev,
1292 const struct rte_flow_attr *attr,
1293 uint64_t item_flags,
1294 struct rte_flow_error *error);
1295 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1296 const struct rte_flow_attr *attr,
1297 struct rte_flow_error *error);
1298 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1299 const struct rte_flow_attr *attributes,
1300 struct rte_flow_error *error);
1301 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1302 const uint8_t *mask,
1303 const uint8_t *nic_mask,
1305 bool range_accepted,
1306 struct rte_flow_error *error);
1307 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1308 uint64_t item_flags, bool ext_vlan_sup,
1309 struct rte_flow_error *error);
1310 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1311 uint64_t item_flags,
1312 uint8_t target_protocol,
1313 struct rte_flow_error *error);
1314 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1315 uint64_t item_flags,
1316 const struct rte_flow_item *gre_item,
1317 struct rte_flow_error *error);
1318 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1319 uint64_t item_flags,
1321 uint16_t ether_type,
1322 const struct rte_flow_item_ipv4 *acc_mask,
1323 bool range_accepted,
1324 struct rte_flow_error *error);
1325 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1326 uint64_t item_flags,
1328 uint16_t ether_type,
1329 const struct rte_flow_item_ipv6 *acc_mask,
1330 struct rte_flow_error *error);
1331 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1332 const struct rte_flow_item *item,
1333 uint64_t item_flags,
1334 uint64_t prev_layer,
1335 struct rte_flow_error *error);
1336 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1337 uint64_t item_flags,
1338 uint8_t target_protocol,
1339 const struct rte_flow_item_tcp *flow_mask,
1340 struct rte_flow_error *error);
1341 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1342 uint64_t item_flags,
1343 uint8_t target_protocol,
1344 struct rte_flow_error *error);
1345 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1346 uint64_t item_flags,
1347 struct rte_eth_dev *dev,
1348 struct rte_flow_error *error);
1349 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1350 uint64_t item_flags,
1351 struct rte_flow_error *error);
1352 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1353 uint64_t item_flags,
1354 struct rte_eth_dev *dev,
1355 struct rte_flow_error *error);
1356 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1357 uint64_t item_flags,
1358 uint8_t target_protocol,
1359 struct rte_flow_error *error);
1360 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1361 uint64_t item_flags,
1362 uint8_t target_protocol,
1363 struct rte_flow_error *error);
1364 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1365 uint64_t item_flags,
1366 uint8_t target_protocol,
1367 struct rte_flow_error *error);
1368 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1369 uint64_t item_flags,
1370 struct rte_eth_dev *dev,
1371 struct rte_flow_error *error);
1372 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1373 uint64_t item_flags,
1375 uint16_t ether_type,
1376 const struct rte_flow_item_ecpri *acc_mask,
1377 struct rte_flow_error *error);
1378 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1379 (struct rte_eth_dev *dev,
1380 const struct mlx5_flow_meter *fm);
1381 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1382 struct mlx5_meter_domains_infos *tbl);
1383 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1384 struct mlx5_flow_meter *fm,
1385 const struct rte_flow_attr *attr);
1386 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1387 struct mlx5_flow_meter *fm,
1388 const struct rte_flow_attr *attr);
1389 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1390 struct rte_mtr_error *error);
1391 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1392 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1393 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1394 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1396 /* Hash list callbacks for flow tables: */
1397 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1398 uint64_t key, void *entry_ctx);
1399 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1400 struct mlx5_hlist_entry *entry);
1401 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1402 uint32_t table_id, uint8_t egress, uint8_t transfer,
1403 bool external, const struct mlx5_flow_tunnel *tunnel,
1404 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error);
1406 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1407 uint64_t key, void *cb_ctx);
1408 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1409 struct mlx5_hlist_entry *entry);
1411 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1412 struct mlx5_hlist_entry *entry,
1413 uint64_t key, void *cb_ctx);
1414 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1415 uint64_t key, void *ctx);
1416 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1417 struct mlx5_hlist_entry *entry);
1419 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1420 uint64_t key, void *ctx);
1421 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1422 struct mlx5_hlist_entry *entry);
1424 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1425 struct mlx5_hlist_entry *entry,
1426 uint64_t key, void *cb_ctx);
1427 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1428 uint64_t key, void *cb_ctx);
1429 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1430 struct mlx5_hlist_entry *entry);
1432 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1433 struct mlx5_cache_entry *entry, void *ctx);
1434 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1435 struct mlx5_cache_entry *entry, void *ctx);
1436 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1437 struct mlx5_cache_entry *entry);
1439 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1440 struct mlx5_cache_entry *entry, void *cb_ctx);
1441 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1442 struct mlx5_cache_entry *entry, void *cb_ctx);
1443 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1444 struct mlx5_cache_entry *entry);
1446 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1447 struct mlx5_cache_entry *entry, void *cb_ctx);
1448 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1449 (struct mlx5_cache_list *list,
1450 struct mlx5_cache_entry *entry, void *cb_ctx);
1451 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1452 struct mlx5_cache_entry *entry);
1454 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1455 struct mlx5_cache_entry *entry, void *cb_ctx);
1456 struct mlx5_cache_entry *flow_dv_sample_create_cb
1457 (struct mlx5_cache_list *list,
1458 struct mlx5_cache_entry *entry, void *cb_ctx);
1459 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1460 struct mlx5_cache_entry *entry);
1462 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1463 struct mlx5_cache_entry *entry, void *cb_ctx);
1464 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1465 (struct mlx5_cache_list *list,
1466 struct mlx5_cache_entry *entry, void *cb_ctx);
1467 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1468 struct mlx5_cache_entry *entry);
1469 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1471 #endif /* RTE_PMD_MLX5_FLOW_H_ */