1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
27 /* Pattern outer Layer bits. */
28 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
29 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
30 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
31 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
32 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
33 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
35 /* Pattern inner Layer bits. */
36 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
37 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
38 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
39 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
40 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
41 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
43 /* Pattern tunnel Layer bits. */
44 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
45 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
46 #define MLX5_FLOW_LAYER_GRE (1u << 14)
47 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
49 /* General pattern items bits. */
50 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
51 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
53 /* Pattern MISC bits. */
54 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
55 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
56 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)
59 #define MLX5_FLOW_LAYER_OUTER_L3 \
60 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
61 #define MLX5_FLOW_LAYER_OUTER_L4 \
62 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
63 #define MLX5_FLOW_LAYER_OUTER \
64 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
65 MLX5_FLOW_LAYER_OUTER_L4)
68 #define MLX5_FLOW_LAYER_TUNNEL \
69 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
70 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS)
73 #define MLX5_FLOW_LAYER_INNER_L3 \
74 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
75 #define MLX5_FLOW_LAYER_INNER_L4 \
76 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
77 #define MLX5_FLOW_LAYER_INNER \
78 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
79 MLX5_FLOW_LAYER_INNER_L4)
82 #define MLX5_FLOW_LAYER_L2 \
83 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
84 #define MLX5_FLOW_LAYER_L3_IPV4 \
85 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
86 #define MLX5_FLOW_LAYER_L3_IPV6 \
87 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
88 #define MLX5_FLOW_LAYER_L3 \
89 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
90 #define MLX5_FLOW_LAYER_L4 \
91 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
94 #define MLX5_FLOW_ACTION_DROP (1u << 0)
95 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
96 #define MLX5_FLOW_ACTION_RSS (1u << 2)
97 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
98 #define MLX5_FLOW_ACTION_MARK (1u << 4)
99 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
100 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
101 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
102 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
103 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
104 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
105 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
106 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
107 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
108 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
109 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
110 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
111 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
112 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
113 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
114 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
115 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
116 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
117 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
118 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
119 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
120 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
121 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
122 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
123 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
124 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
125 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
127 #define MLX5_FLOW_FATE_ACTIONS \
128 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
129 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
131 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
132 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
133 MLX5_FLOW_ACTION_JUMP)
135 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
136 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
137 MLX5_FLOW_ACTION_RAW_ENCAP)
139 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
140 MLX5_FLOW_ACTION_NVGRE_DECAP | \
141 MLX5_FLOW_ACTION_RAW_DECAP)
143 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
144 MLX5_FLOW_ACTION_SET_IPV4_DST | \
145 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
146 MLX5_FLOW_ACTION_SET_IPV6_DST | \
147 MLX5_FLOW_ACTION_SET_TP_SRC | \
148 MLX5_FLOW_ACTION_SET_TP_DST | \
149 MLX5_FLOW_ACTION_SET_TTL | \
150 MLX5_FLOW_ACTION_DEC_TTL | \
151 MLX5_FLOW_ACTION_SET_MAC_SRC | \
152 MLX5_FLOW_ACTION_SET_MAC_DST | \
153 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
154 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
155 MLX5_FLOW_ACTION_INC_TCP_ACK | \
156 MLX5_FLOW_ACTION_DEC_TCP_ACK)
159 #define IPPROTO_MPLS 137
162 /* UDP port number for MPLS */
163 #define MLX5_UDP_PORT_MPLS 6635
165 /* UDP port numbers for VxLAN. */
166 #define MLX5_UDP_PORT_VXLAN 4789
167 #define MLX5_UDP_PORT_VXLAN_GPE 4790
169 /* Priority reserved for default flows. */
170 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
173 * Number of sub priorities.
174 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
175 * matching on the NIC (firmware dependent) L4 most have the higher priority
176 * followed by L3 and ending with L2.
178 #define MLX5_PRIORITY_MAP_L2 2
179 #define MLX5_PRIORITY_MAP_L3 1
180 #define MLX5_PRIORITY_MAP_L4 0
181 #define MLX5_PRIORITY_MAP_MAX 3
183 /* Valid layer type for IPV4 RSS. */
184 #define MLX5_IPV4_LAYER_TYPES \
185 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
186 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
187 ETH_RSS_NONFRAG_IPV4_OTHER)
189 /* IBV hash source bits for IPV4. */
190 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
192 /* Valid layer type for IPV6 RSS. */
193 #define MLX5_IPV6_LAYER_TYPES \
194 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
195 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
196 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
198 /* IBV hash source bits for IPV6. */
199 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
201 enum mlx5_flow_drv_type {
204 MLX5_FLOW_TYPE_VERBS,
208 /* Matcher PRM representation */
209 struct mlx5_flow_dv_match_params {
211 /**< Size of match value. Do NOT split size and key! */
212 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
213 /**< Matcher value. This value is used as the mask or as a key. */
216 /* Matcher structure. */
217 struct mlx5_flow_dv_matcher {
218 LIST_ENTRY(mlx5_flow_dv_matcher) next;
219 /* Pointer to the next element. */
220 rte_atomic32_t refcnt; /**< Reference counter. */
221 void *matcher_object; /**< Pointer to DV matcher */
222 uint16_t crc; /**< CRC of key. */
223 uint16_t priority; /**< Priority of matcher. */
224 uint8_t egress; /**< Egress matcher. */
225 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
226 uint32_t group; /**< The matcher group. */
227 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
230 #define MLX5_ENCAP_MAX_LEN 132
232 /* Encap/decap resource structure. */
233 struct mlx5_flow_dv_encap_decap_resource {
234 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
235 /* Pointer to next element. */
236 rte_atomic32_t refcnt; /**< Reference counter. */
238 /**< Verbs encap/decap action object. */
239 uint8_t buf[MLX5_ENCAP_MAX_LEN];
241 uint8_t reformat_type;
243 uint64_t flags; /**< Flags for RDMA API. */
246 /* Tag resource structure. */
247 struct mlx5_flow_dv_tag_resource {
248 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
249 /* Pointer to next element. */
250 rte_atomic32_t refcnt; /**< Reference counter. */
252 /**< Verbs tag action object. */
253 uint32_t tag; /**< the tag value. */
256 /* Number of modification commands. */
257 #define MLX5_MODIFY_NUM 8
259 /* Modify resource structure */
260 struct mlx5_flow_dv_modify_hdr_resource {
261 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
262 /* Pointer to next element. */
263 rte_atomic32_t refcnt; /**< Reference counter. */
264 struct ibv_flow_action *verbs_action;
265 /**< Verbs modify header action object. */
266 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
267 uint32_t actions_num; /**< Number of modification actions. */
268 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
269 /**< Modification actions. */
270 uint64_t flags; /**< Flags for RDMA API. */
273 /* Jump action resource structure. */
274 struct mlx5_flow_dv_jump_tbl_resource {
275 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
276 /* Pointer to next element. */
277 rte_atomic32_t refcnt; /**< Reference counter. */
278 void *action; /**< Pointer to the rdma core action. */
279 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
280 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
283 /* Port ID resource structure. */
284 struct mlx5_flow_dv_port_id_action_resource {
285 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
286 /* Pointer to next element. */
287 rte_atomic32_t refcnt; /**< Reference counter. */
289 /**< Verbs tag action object. */
290 uint32_t port_id; /**< Port ID value. */
294 * Max number of actions per DV flow.
295 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
296 * In rdma-core file providers/mlx5/verbs.c
298 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
300 /* DV flows structure. */
301 struct mlx5_flow_dv {
302 uint64_t hash_fields; /**< Fields that participate in the hash. */
303 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
305 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
306 struct mlx5_flow_dv_match_params value;
307 /**< Holds the value that the packet is compared to. */
308 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
309 /**< Pointer to encap/decap resource in cache. */
310 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
311 /**< Pointer to modify header resource in cache. */
312 struct ibv_flow *flow; /**< Installed flow. */
313 struct mlx5_flow_dv_jump_tbl_resource *jump;
314 /**< Pointer to the jump action resource. */
315 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
316 /**< Pointer to port ID action resource. */
317 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
318 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
321 int actions_n; /**< number of actions. */
324 /* Verbs specification header. */
325 struct ibv_spec_header {
326 enum ibv_flow_spec_type type;
330 /** Handles information leading to a drop fate. */
331 struct mlx5_flow_verbs {
332 LIST_ENTRY(mlx5_flow_verbs) next;
333 unsigned int size; /**< Size of the attribute. */
335 struct ibv_flow_attr *attr;
336 /**< Pointer to the Specification buffer. */
337 uint8_t *specs; /**< Pointer to the specifications. */
339 struct ibv_flow *flow; /**< Verbs flow pointer. */
340 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
341 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
344 /** Device flow structure. */
346 LIST_ENTRY(mlx5_flow) next;
347 struct rte_flow *flow; /**< Pointer to the main flow. */
349 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
351 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
352 struct mlx5_flow_dv dv;
354 struct mlx5_flow_verbs verbs;
358 /* Counters information. */
359 struct mlx5_flow_counter {
360 LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */
361 uint32_t shared:1; /**< Share counter ID with other flow rules. */
362 uint32_t ref_cnt:31; /**< Reference counter. */
363 uint32_t id; /**< Counter ID. */
364 union { /**< Holds the counters for the rule. */
365 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
366 struct ibv_counter_set *cs;
367 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
368 struct ibv_counters *cs;
370 struct mlx5_devx_counter_set *dcs;
372 uint64_t hits; /**< Number of packets matched by the rule. */
373 uint64_t bytes; /**< Number of bytes matched by the rule. */
374 void *action; /**< Pointer to the dv action. */
377 /* Flow structure. */
379 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
380 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
381 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
382 struct mlx5_flow_dv_tag_resource *tag_resource;
383 /**< pointer to the tag action. */
384 struct rte_flow_action_rss rss;/**< RSS context. */
385 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
386 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
387 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
388 /**< Device flows that are part of the flow. */
390 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
391 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
392 uint8_t ingress; /**< 1 if the flow is ingress. */
393 uint32_t group; /**< The group index. */
394 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
397 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
398 const struct rte_flow_attr *attr,
399 const struct rte_flow_item items[],
400 const struct rte_flow_action actions[],
401 struct rte_flow_error *error);
402 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
403 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
404 const struct rte_flow_action actions[], struct rte_flow_error *error);
405 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
406 struct mlx5_flow *dev_flow,
407 const struct rte_flow_attr *attr,
408 const struct rte_flow_item items[],
409 const struct rte_flow_action actions[],
410 struct rte_flow_error *error);
411 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
412 struct rte_flow_error *error);
413 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
414 struct rte_flow *flow);
415 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
416 struct rte_flow *flow);
417 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
418 struct rte_flow *flow,
419 const struct rte_flow_action *actions,
421 struct rte_flow_error *error);
422 struct mlx5_flow_driver_ops {
423 mlx5_flow_validate_t validate;
424 mlx5_flow_prepare_t prepare;
425 mlx5_flow_translate_t translate;
426 mlx5_flow_apply_t apply;
427 mlx5_flow_remove_t remove;
428 mlx5_flow_destroy_t destroy;
429 mlx5_flow_query_t query;
434 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
435 uint64_t layer_types,
436 uint64_t hash_fields);
437 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
438 uint32_t subpriority);
439 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
440 const struct rte_flow_attr *attr,
441 struct rte_flow_error *error);
442 int mlx5_flow_validate_action_drop(uint64_t action_flags,
443 const struct rte_flow_attr *attr,
444 struct rte_flow_error *error);
445 int mlx5_flow_validate_action_flag(uint64_t action_flags,
446 const struct rte_flow_attr *attr,
447 struct rte_flow_error *error);
448 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
449 uint64_t action_flags,
450 const struct rte_flow_attr *attr,
451 struct rte_flow_error *error);
452 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
453 uint64_t action_flags,
454 struct rte_eth_dev *dev,
455 const struct rte_flow_attr *attr,
456 struct rte_flow_error *error);
457 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
458 uint64_t action_flags,
459 struct rte_eth_dev *dev,
460 const struct rte_flow_attr *attr,
462 struct rte_flow_error *error);
463 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
464 const struct rte_flow_attr *attributes,
465 struct rte_flow_error *error);
466 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
468 const uint8_t *nic_mask,
470 struct rte_flow_error *error);
471 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
473 struct rte_flow_error *error);
474 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
476 uint8_t target_protocol,
477 struct rte_flow_error *error);
478 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
480 const struct rte_flow_item *gre_item,
481 struct rte_flow_error *error);
482 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
484 const struct rte_flow_item_ipv4 *acc_mask,
485 struct rte_flow_error *error);
486 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
488 const struct rte_flow_item_ipv6 *acc_mask,
489 struct rte_flow_error *error);
490 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
491 const struct rte_flow_item *item,
494 struct rte_flow_error *error);
495 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
497 uint8_t target_protocol,
498 const struct rte_flow_item_tcp *flow_mask,
499 struct rte_flow_error *error);
500 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
502 uint8_t target_protocol,
503 struct rte_flow_error *error);
504 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
506 struct rte_flow_error *error);
507 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
509 struct rte_flow_error *error);
510 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
512 struct rte_eth_dev *dev,
513 struct rte_flow_error *error);
514 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
516 uint8_t target_protocol,
517 struct rte_flow_error *error);
518 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
520 uint8_t target_protocol,
521 struct rte_flow_error *error);
523 #endif /* RTE_PMD_MLX5_FLOW_H_ */