1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
32 /* Private rte flow items. */
33 enum mlx5_rte_flow_item_type {
34 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
35 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
36 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
39 /* Private (internal) rte flow actions. */
40 enum mlx5_rte_flow_action_type {
41 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
42 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
43 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
44 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
47 /* Matches on selected register. */
48 struct mlx5_rte_flow_item_tag {
53 /* Modify selected register. */
54 struct mlx5_rte_flow_action_set_tag {
59 struct mlx5_flow_action_copy_mreg {
64 /* Matches on source queue. */
65 struct mlx5_rte_flow_item_tx_queue {
69 /* Feature name to allocate metadata register. */
70 enum mlx5_feature_name {
83 /* Pattern outer Layer bits. */
84 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
85 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
86 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
87 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
88 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
89 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
91 /* Pattern inner Layer bits. */
92 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
93 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
94 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
95 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
96 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
97 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
99 /* Pattern tunnel Layer bits. */
100 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
101 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
102 #define MLX5_FLOW_LAYER_GRE (1u << 14)
103 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
104 /* List of tunnel Layer bits continued below. */
106 /* General pattern items bits. */
107 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
108 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
109 #define MLX5_FLOW_ITEM_TAG (1u << 18)
110 #define MLX5_FLOW_ITEM_MARK (1u << 19)
112 /* Pattern MISC bits. */
113 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
114 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
115 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
117 /* Pattern tunnel Layer bits (continued). */
118 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
119 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
120 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
121 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
124 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
126 /* Pattern tunnel Layer bits (continued). */
127 #define MLX5_FLOW_LAYER_GTP (1u << 28)
130 #define MLX5_FLOW_LAYER_OUTER_L3 \
131 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
132 #define MLX5_FLOW_LAYER_OUTER_L4 \
133 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
134 #define MLX5_FLOW_LAYER_OUTER \
135 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
136 MLX5_FLOW_LAYER_OUTER_L4)
139 #define MLX5_FLOW_LAYER_TUNNEL \
140 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
141 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
142 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
143 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
146 #define MLX5_FLOW_LAYER_INNER_L3 \
147 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
148 #define MLX5_FLOW_LAYER_INNER_L4 \
149 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
150 #define MLX5_FLOW_LAYER_INNER \
151 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
152 MLX5_FLOW_LAYER_INNER_L4)
155 #define MLX5_FLOW_LAYER_L2 \
156 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
157 #define MLX5_FLOW_LAYER_L3_IPV4 \
158 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
159 #define MLX5_FLOW_LAYER_L3_IPV6 \
160 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
161 #define MLX5_FLOW_LAYER_L3 \
162 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
163 #define MLX5_FLOW_LAYER_L4 \
164 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
167 #define MLX5_FLOW_ACTION_DROP (1u << 0)
168 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
169 #define MLX5_FLOW_ACTION_RSS (1u << 2)
170 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
171 #define MLX5_FLOW_ACTION_MARK (1u << 4)
172 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
173 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
174 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
175 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
176 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
177 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
178 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
179 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
180 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
181 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
182 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
183 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
184 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
185 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
186 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
187 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
188 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
189 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
190 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
191 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
192 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
193 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
194 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
195 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
196 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
197 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
198 #define MLX5_FLOW_ACTION_METER (1ull << 31)
199 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
200 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
202 #define MLX5_FLOW_FATE_ACTIONS \
203 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
204 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
206 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
207 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
208 MLX5_FLOW_ACTION_JUMP)
211 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
212 MLX5_FLOW_ACTION_SET_IPV4_DST | \
213 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
214 MLX5_FLOW_ACTION_SET_IPV6_DST | \
215 MLX5_FLOW_ACTION_SET_TP_SRC | \
216 MLX5_FLOW_ACTION_SET_TP_DST | \
217 MLX5_FLOW_ACTION_SET_TTL | \
218 MLX5_FLOW_ACTION_DEC_TTL | \
219 MLX5_FLOW_ACTION_SET_MAC_SRC | \
220 MLX5_FLOW_ACTION_SET_MAC_DST | \
221 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
222 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
223 MLX5_FLOW_ACTION_INC_TCP_ACK | \
224 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
225 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
226 MLX5_FLOW_ACTION_SET_TAG | \
227 MLX5_FLOW_ACTION_MARK_EXT | \
228 MLX5_FLOW_ACTION_SET_META | \
229 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
230 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
232 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
233 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
235 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
238 #define IPPROTO_MPLS 137
241 /* UDP port number for MPLS */
242 #define MLX5_UDP_PORT_MPLS 6635
244 /* UDP port numbers for VxLAN. */
245 #define MLX5_UDP_PORT_VXLAN 4789
246 #define MLX5_UDP_PORT_VXLAN_GPE 4790
248 /* UDP port numbers for GENEVE. */
249 #define MLX5_UDP_PORT_GENEVE 6081
251 /* Priority reserved for default flows. */
252 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
255 * Number of sub priorities.
256 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
257 * matching on the NIC (firmware dependent) L4 most have the higher priority
258 * followed by L3 and ending with L2.
260 #define MLX5_PRIORITY_MAP_L2 2
261 #define MLX5_PRIORITY_MAP_L3 1
262 #define MLX5_PRIORITY_MAP_L4 0
263 #define MLX5_PRIORITY_MAP_MAX 3
265 /* Valid layer type for IPV4 RSS. */
266 #define MLX5_IPV4_LAYER_TYPES \
267 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
268 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
269 ETH_RSS_NONFRAG_IPV4_OTHER)
271 /* IBV hash source bits for IPV4. */
272 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
274 /* Valid layer type for IPV6 RSS. */
275 #define MLX5_IPV6_LAYER_TYPES \
276 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
277 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
278 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
280 /* IBV hash source bits for IPV6. */
281 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
283 /* IBV hash bits for L3 SRC. */
284 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
286 /* IBV hash bits for L3 DST. */
287 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
289 /* IBV hash bits for TCP. */
290 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
291 IBV_RX_HASH_DST_PORT_TCP)
293 /* IBV hash bits for UDP. */
294 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
295 IBV_RX_HASH_DST_PORT_UDP)
297 /* IBV hash bits for L4 SRC. */
298 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
299 IBV_RX_HASH_SRC_PORT_UDP)
301 /* IBV hash bits for L4 DST. */
302 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
303 IBV_RX_HASH_DST_PORT_UDP)
305 /* Geneve header first 16Bit */
306 #define MLX5_GENEVE_VER_MASK 0x3
307 #define MLX5_GENEVE_VER_SHIFT 14
308 #define MLX5_GENEVE_VER_VAL(a) \
309 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
310 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
311 #define MLX5_GENEVE_OPTLEN_SHIFT 7
312 #define MLX5_GENEVE_OPTLEN_VAL(a) \
313 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
314 #define MLX5_GENEVE_OAMF_MASK 0x1
315 #define MLX5_GENEVE_OAMF_SHIFT 7
316 #define MLX5_GENEVE_OAMF_VAL(a) \
317 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
318 #define MLX5_GENEVE_CRITO_MASK 0x1
319 #define MLX5_GENEVE_CRITO_SHIFT 6
320 #define MLX5_GENEVE_CRITO_VAL(a) \
321 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
322 #define MLX5_GENEVE_RSVD_MASK 0x3F
323 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
325 * The length of the Geneve options fields, expressed in four byte multiples,
326 * not including the eight byte fixed tunnel.
328 #define MLX5_GENEVE_OPT_LEN_0 14
329 #define MLX5_GENEVE_OPT_LEN_1 63
331 enum mlx5_flow_drv_type {
334 MLX5_FLOW_TYPE_VERBS,
338 /* Matcher PRM representation */
339 struct mlx5_flow_dv_match_params {
341 /**< Size of match value. Do NOT split size and key! */
342 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
343 /**< Matcher value. This value is used as the mask or as a key. */
346 /* Matcher structure. */
347 struct mlx5_flow_dv_matcher {
348 LIST_ENTRY(mlx5_flow_dv_matcher) next;
349 /**< Pointer to the next element. */
350 struct mlx5_flow_tbl_resource *tbl;
351 /**< Pointer to the table(group) the matcher associated with. */
352 rte_atomic32_t refcnt; /**< Reference counter. */
353 void *matcher_object; /**< Pointer to DV matcher */
354 uint16_t crc; /**< CRC of key. */
355 uint16_t priority; /**< Priority of matcher. */
356 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
359 #define MLX5_ENCAP_MAX_LEN 132
361 /* Encap/decap resource structure. */
362 struct mlx5_flow_dv_encap_decap_resource {
363 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
364 /* Pointer to next element. */
365 rte_atomic32_t refcnt; /**< Reference counter. */
367 /**< Verbs encap/decap action object. */
368 uint8_t buf[MLX5_ENCAP_MAX_LEN];
370 uint8_t reformat_type;
372 uint64_t flags; /**< Flags for RDMA API. */
375 /* Tag resource structure. */
376 struct mlx5_flow_dv_tag_resource {
377 struct mlx5_hlist_entry entry;
378 /**< hash list entry for tag resource, tag value as the key. */
380 /**< Verbs tag action object. */
381 rte_atomic32_t refcnt; /**< Reference counter. */
385 * Number of modification commands.
386 * If extensive metadata registers are supported, the maximal actions amount is
387 * 16 and 8 otherwise on root table. The validation could also be done in the
388 * lower driver layer.
389 * On non-root table, there is no limitation, but 32 is enough right now.
391 #define MLX5_MAX_MODIFY_NUM 32
392 #define MLX5_ROOT_TBL_MODIFY_NUM 16
393 #define MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG 8
395 /* Modify resource structure */
396 struct mlx5_flow_dv_modify_hdr_resource {
397 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
398 /* Pointer to next element. */
399 rte_atomic32_t refcnt; /**< Reference counter. */
400 struct ibv_flow_action *verbs_action;
401 /**< Verbs modify header action object. */
402 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
403 uint32_t actions_num; /**< Number of modification actions. */
404 uint64_t flags; /**< Flags for RDMA API. */
405 struct mlx5_modification_cmd actions[];
406 /**< Modification actions. */
409 /* Jump action resource structure. */
410 struct mlx5_flow_dv_jump_tbl_resource {
411 rte_atomic32_t refcnt; /**< Reference counter. */
412 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
413 void *action; /**< Pointer to the rdma core action. */
416 /* Port ID resource structure. */
417 struct mlx5_flow_dv_port_id_action_resource {
418 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
419 /* Pointer to next element. */
420 rte_atomic32_t refcnt; /**< Reference counter. */
422 /**< Verbs tag action object. */
423 uint32_t port_id; /**< Port ID value. */
426 /* Push VLAN action resource structure */
427 struct mlx5_flow_dv_push_vlan_action_resource {
428 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
429 /* Pointer to next element. */
430 rte_atomic32_t refcnt; /**< Reference counter. */
431 void *action; /**< Direct verbs action object. */
432 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
433 rte_be32_t vlan_tag; /**< VLAN tag value. */
436 /* Metadata register copy table entry. */
437 struct mlx5_flow_mreg_copy_resource {
439 * Hash list entry for copy table.
440 * - Key is 32/64-bit MARK action ID.
441 * - MUST be the first entry.
443 struct mlx5_hlist_entry hlist_ent;
444 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
445 /* List entry for device flows. */
446 uint32_t refcnt; /* Reference counter. */
447 uint32_t appcnt; /* Apply/Remove counter. */
448 struct rte_flow *flow; /* Built flow for copy. */
451 /* Table data structure of the hash organization. */
452 struct mlx5_flow_tbl_data_entry {
453 struct mlx5_hlist_entry entry;
454 /**< hash list entry, 64-bits key inside. */
455 struct mlx5_flow_tbl_resource tbl;
456 /**< flow table resource. */
457 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
458 /**< matchers' header associated with the flow table. */
459 struct mlx5_flow_dv_jump_tbl_resource jump;
460 /**< jump resource, at most one for each table created. */
464 * Max number of actions per DV flow.
465 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
466 * In rdma-core file providers/mlx5/verbs.c
468 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
470 /* DV flows structure. */
471 struct mlx5_flow_dv {
472 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
474 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
475 struct mlx5_flow_dv_match_params value;
476 /**< Holds the value that the packet is compared to. */
477 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
478 /**< Pointer to encap/decap resource in cache. */
479 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
480 /**< Pointer to modify header resource in cache. */
481 struct ibv_flow *flow; /**< Installed flow. */
482 struct mlx5_flow_dv_jump_tbl_resource *jump;
483 /**< Pointer to the jump action resource. */
484 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
485 /**< Pointer to port ID action resource. */
486 struct mlx5_vf_vlan vf_vlan;
487 /**< Structure for VF VLAN workaround. */
488 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
489 /**< Pointer to push VLAN action resource in cache. */
490 struct mlx5_flow_dv_tag_resource *tag_resource;
491 /**< pointer to the tag action. */
492 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
493 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
496 int actions_n; /**< number of actions. */
499 /* Verbs specification header. */
500 struct ibv_spec_header {
501 enum ibv_flow_spec_type type;
505 /** Handles information leading to a drop fate. */
506 struct mlx5_flow_verbs {
507 LIST_ENTRY(mlx5_flow_verbs) next;
508 unsigned int size; /**< Size of the attribute. */
510 struct ibv_flow_attr *attr;
511 /**< Pointer to the Specification buffer. */
512 uint8_t *specs; /**< Pointer to the specifications. */
514 struct ibv_flow *flow; /**< Verbs flow pointer. */
515 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
516 struct mlx5_vf_vlan vf_vlan;
517 /**< Structure for VF VLAN workaround. */
520 struct mlx5_flow_rss {
522 uint32_t queue_num; /**< Number of entries in @p queue. */
523 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
524 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
525 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
528 /** Device flow structure. */
530 LIST_ENTRY(mlx5_flow) next;
531 struct rte_flow *flow; /**< Pointer to the main flow. */
533 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
535 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
536 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
537 uint8_t ingress; /**< 1 if the flow is ingress. */
538 uint32_t group; /**< The group index. */
539 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
541 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
542 struct mlx5_flow_dv dv;
544 struct mlx5_flow_verbs verbs;
547 uint32_t qrss_id; /**< Uniqie Q/RSS suffix subflow tag. */
548 uint32_t mtr_flow_id; /**< Unique meter match flow id. */
550 bool external; /**< true if the flow is created external to PMD. */
553 /* Flow meter state. */
554 #define MLX5_FLOW_METER_DISABLE 0
555 #define MLX5_FLOW_METER_ENABLE 1
557 #define MLX5_MAN_WIDTH 8
558 /* Modify this value if enum rte_mtr_color changes. */
559 #define RTE_MTR_DROPPED RTE_COLORS
561 /* Meter policer statistics */
562 struct mlx5_flow_policer_stats {
563 struct mlx5_flow_counter *cnt[RTE_COLORS + 1];
564 /**< Color counter, extra for drop. */
566 /**< Statistics mask for the colors. */
569 /* Meter table structure. */
570 struct mlx5_meter_domain_info {
571 struct mlx5_flow_tbl_resource *tbl;
574 /**< Meter color not match default criteria. */
576 /**< Meter color match criteria. */
578 /**< Meter match action. */
579 void *policer_rules[RTE_MTR_DROPPED + 1];
580 /**< Meter policer for the match. */
583 /* Meter table set for TX RX FDB. */
584 struct mlx5_meter_domains_infos {
586 /**< Table user count. */
587 struct mlx5_meter_domain_info egress;
588 /**< TX meter table. */
589 struct mlx5_meter_domain_info ingress;
590 /**< RX meter table. */
591 struct mlx5_meter_domain_info transfer;
592 /**< FDB meter table. */
594 /**< Drop action as not matched. */
595 void *count_actns[RTE_MTR_DROPPED + 1];
596 /**< Counters for match and unmatched statistics. */
597 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
598 /**< Flow meter parameter. */
600 /**< Flow meter parameter size. */
602 /**< Flow meter action. */
605 /* Meter parameter structure. */
606 struct mlx5_flow_meter {
607 TAILQ_ENTRY(mlx5_flow_meter) next;
608 /**< Pointer to the next flow meter structure. */
611 struct rte_mtr_params params;
612 /**< Meter rule parameters. */
613 struct mlx5_flow_meter_profile *profile;
614 /**< Meter profile parameters. */
615 struct rte_flow_attr attr;
616 /**< Flow attributes. */
617 struct mlx5_meter_domains_infos *mfts;
618 /**< Flow table created for this meter. */
619 struct mlx5_flow_policer_stats policer_stats;
620 /**< Meter policer statistics. */
623 uint32_t active_state:1;
626 /**< Meter shared or not. */
629 /* RFC2697 parameter structure. */
630 struct mlx5_flow_meter_srtcm_rfc2697_prm {
631 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
632 uint32_t cbs_exponent:5;
633 uint32_t cbs_mantissa:8;
634 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
635 uint32_t cir_exponent:5;
636 uint32_t cir_mantissa:8;
637 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
638 uint32_t ebs_exponent:5;
639 uint32_t ebs_mantissa:8;
642 /* Flow meter profile structure. */
643 struct mlx5_flow_meter_profile {
644 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
645 /**< Pointer to the next flow meter structure. */
646 uint32_t meter_profile_id; /**< Profile id. */
647 struct rte_mtr_meter_profile profile; /**< Profile detail. */
649 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
650 /**< srtcm_rfc2697 struct. */
652 uint32_t ref_cnt; /**< Use count. */
655 /* Flow structure. */
657 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
658 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
659 struct mlx5_flow_rss rss; /**< RSS context. */
660 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
661 struct mlx5_flow_mreg_copy_resource *mreg_copy;
662 /**< pointer to metadata register copy table resource. */
663 struct mlx5_flow_meter *meter; /**< Holds flow meter. */
664 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
665 /**< Device flows that are part of the flow. */
666 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
667 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
668 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
671 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
672 const struct rte_flow_attr *attr,
673 const struct rte_flow_item items[],
674 const struct rte_flow_action actions[],
676 struct rte_flow_error *error);
677 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
678 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
679 const struct rte_flow_action actions[], struct rte_flow_error *error);
680 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
681 struct mlx5_flow *dev_flow,
682 const struct rte_flow_attr *attr,
683 const struct rte_flow_item items[],
684 const struct rte_flow_action actions[],
685 struct rte_flow_error *error);
686 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
687 struct rte_flow_error *error);
688 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
689 struct rte_flow *flow);
690 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
691 struct rte_flow *flow);
692 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
693 struct rte_flow *flow,
694 const struct rte_flow_action *actions,
696 struct rte_flow_error *error);
697 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
698 (struct rte_eth_dev *dev,
699 const struct mlx5_flow_meter *fm);
700 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
701 struct mlx5_meter_domains_infos *tbls);
702 typedef int (*mlx5_flow_create_policer_rules_t)
703 (struct rte_eth_dev *dev,
704 struct mlx5_flow_meter *fm,
705 const struct rte_flow_attr *attr);
706 typedef int (*mlx5_flow_destroy_policer_rules_t)
707 (struct rte_eth_dev *dev,
708 const struct mlx5_flow_meter *fm,
709 const struct rte_flow_attr *attr);
710 typedef struct mlx5_flow_counter * (*mlx5_flow_counter_alloc_t)
711 (struct rte_eth_dev *dev);
712 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
713 struct mlx5_flow_counter *cnt);
714 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
715 struct mlx5_flow_counter *cnt,
716 bool clear, uint64_t *pkts,
718 struct mlx5_flow_driver_ops {
719 mlx5_flow_validate_t validate;
720 mlx5_flow_prepare_t prepare;
721 mlx5_flow_translate_t translate;
722 mlx5_flow_apply_t apply;
723 mlx5_flow_remove_t remove;
724 mlx5_flow_destroy_t destroy;
725 mlx5_flow_query_t query;
726 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
727 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
728 mlx5_flow_create_policer_rules_t create_policer_rules;
729 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
730 mlx5_flow_counter_alloc_t counter_alloc;
731 mlx5_flow_counter_free_t counter_free;
732 mlx5_flow_counter_query_t counter_query;
736 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
737 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
738 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
739 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
743 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id);
744 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
745 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
746 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
748 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
749 bool external, uint32_t group, bool fdb_def_rule,
750 uint32_t *table, struct rte_flow_error *error);
751 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
752 uint64_t layer_types,
753 uint64_t hash_fields);
754 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
755 uint32_t subpriority);
756 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
757 enum mlx5_feature_name feature,
759 struct rte_flow_error *error);
760 const struct rte_flow_action *mlx5_flow_find_action
761 (const struct rte_flow_action *actions,
762 enum rte_flow_action_type action);
763 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
764 const struct rte_flow_attr *attr,
765 struct rte_flow_error *error);
766 int mlx5_flow_validate_action_drop(uint64_t action_flags,
767 const struct rte_flow_attr *attr,
768 struct rte_flow_error *error);
769 int mlx5_flow_validate_action_flag(uint64_t action_flags,
770 const struct rte_flow_attr *attr,
771 struct rte_flow_error *error);
772 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
773 uint64_t action_flags,
774 const struct rte_flow_attr *attr,
775 struct rte_flow_error *error);
776 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
777 uint64_t action_flags,
778 struct rte_eth_dev *dev,
779 const struct rte_flow_attr *attr,
780 struct rte_flow_error *error);
781 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
782 uint64_t action_flags,
783 struct rte_eth_dev *dev,
784 const struct rte_flow_attr *attr,
786 struct rte_flow_error *error);
787 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
788 const struct rte_flow_attr *attributes,
789 struct rte_flow_error *error);
790 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
792 const uint8_t *nic_mask,
794 struct rte_flow_error *error);
795 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
797 struct rte_flow_error *error);
798 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
800 uint8_t target_protocol,
801 struct rte_flow_error *error);
802 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
804 const struct rte_flow_item *gre_item,
805 struct rte_flow_error *error);
806 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
810 const struct rte_flow_item_ipv4 *acc_mask,
811 struct rte_flow_error *error);
812 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
816 const struct rte_flow_item_ipv6 *acc_mask,
817 struct rte_flow_error *error);
818 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
819 const struct rte_flow_item *item,
822 struct rte_flow_error *error);
823 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
825 uint8_t target_protocol,
826 const struct rte_flow_item_tcp *flow_mask,
827 struct rte_flow_error *error);
828 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
830 uint8_t target_protocol,
831 struct rte_flow_error *error);
832 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
834 struct rte_eth_dev *dev,
835 struct rte_flow_error *error);
836 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
838 struct rte_flow_error *error);
839 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
841 struct rte_eth_dev *dev,
842 struct rte_flow_error *error);
843 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
845 uint8_t target_protocol,
846 struct rte_flow_error *error);
847 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
849 uint8_t target_protocol,
850 struct rte_flow_error *error);
851 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
853 uint8_t target_protocol,
854 struct rte_flow_error *error);
855 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
857 struct rte_eth_dev *dev,
858 struct rte_flow_error *error);
859 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
860 (struct rte_eth_dev *dev,
861 const struct mlx5_flow_meter *fm);
862 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
863 struct mlx5_meter_domains_infos *tbl);
864 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
865 struct mlx5_flow_meter *fm,
866 const struct rte_flow_attr *attr);
867 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
868 struct mlx5_flow_meter *fm,
869 const struct rte_flow_attr *attr);
870 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
871 struct rte_mtr_error *error);
872 #endif /* RTE_PMD_MLX5_FLOW_H_ */