1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* E-Switch Manager port, used for rte_flow_item_port_id. */
22 #define MLX5_PORT_ESW_MGR UINT32_MAX
24 /* Private rte flow items. */
25 enum mlx5_rte_flow_item_type {
26 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
28 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
29 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
30 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
33 /* Private (internal) rte flow actions. */
34 enum mlx5_rte_flow_action_type {
35 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
36 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
37 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
38 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
39 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
41 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
43 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
46 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
49 MLX5_INDIRECT_ACTION_TYPE_RSS,
50 MLX5_INDIRECT_ACTION_TYPE_AGE,
51 MLX5_INDIRECT_ACTION_TYPE_COUNT,
52 MLX5_INDIRECT_ACTION_TYPE_CT,
55 /* Now, the maximal ports will be supported is 256, action number is 4M. */
56 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100
58 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22
59 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)
61 /* 30-31: type, 22-29: owner port, 0-21: index. */
62 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \
63 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \
64 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \
65 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index))
67 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \
68 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \
69 MLX5_INDIRECT_ACT_CT_OWNER_MASK)
71 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \
72 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))
74 /* Matches on selected register. */
75 struct mlx5_rte_flow_item_tag {
80 /* Modify selected register. */
81 struct mlx5_rte_flow_action_set_tag {
88 struct mlx5_flow_action_copy_mreg {
93 /* Matches on source queue. */
94 struct mlx5_rte_flow_item_tx_queue {
98 /* Feature name to allocate metadata register. */
99 enum mlx5_feature_name {
115 /* Default queue number. */
116 #define MLX5_RSSQ_DEFAULT_NUM 16
118 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
119 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
120 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
121 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
122 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
123 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
125 /* Pattern inner Layer bits. */
126 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
127 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
128 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
129 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
130 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
131 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
133 /* Pattern tunnel Layer bits. */
134 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
135 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
136 #define MLX5_FLOW_LAYER_GRE (1u << 14)
137 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
138 /* List of tunnel Layer bits continued below. */
140 /* General pattern items bits. */
141 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
142 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
143 #define MLX5_FLOW_ITEM_TAG (1u << 18)
144 #define MLX5_FLOW_ITEM_MARK (1u << 19)
146 /* Pattern MISC bits. */
147 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
148 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
149 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
151 /* Pattern tunnel Layer bits (continued). */
152 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
153 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
154 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
155 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
158 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
160 /* Pattern tunnel Layer bits (continued). */
161 #define MLX5_FLOW_LAYER_GTP (1u << 28)
163 /* Pattern eCPRI Layer bit. */
164 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
166 /* IPv6 Fragment Extension Header bit. */
167 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
168 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
170 /* Pattern tunnel Layer bits (continued). */
171 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
172 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
174 /* INTEGRITY item bits */
175 #define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34)
176 #define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35)
177 #define MLX5_FLOW_ITEM_INTEGRITY \
178 (MLX5_FLOW_ITEM_OUTER_INTEGRITY | MLX5_FLOW_ITEM_INNER_INTEGRITY)
180 /* Conntrack item. */
181 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36)
184 #define MLX5_FLOW_ITEM_OUTER_FLEX (UINT64_C(1) << 37)
185 #define MLX5_FLOW_ITEM_INNER_FLEX (UINT64_C(1) << 38)
186 #define MLX5_FLOW_ITEM_FLEX_TUNNEL (UINT64_C(1) << 39)
189 #define MLX5_FLOW_LAYER_OUTER_L3 \
190 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
191 #define MLX5_FLOW_LAYER_OUTER_L4 \
192 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
193 #define MLX5_FLOW_LAYER_OUTER \
194 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
195 MLX5_FLOW_LAYER_OUTER_L4)
198 #define MLX5_FLOW_LAYER_TUNNEL \
199 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
200 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
201 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
202 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP | \
203 MLX5_FLOW_ITEM_FLEX_TUNNEL)
206 #define MLX5_FLOW_LAYER_INNER_L3 \
207 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
208 #define MLX5_FLOW_LAYER_INNER_L4 \
209 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
210 #define MLX5_FLOW_LAYER_INNER \
211 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
212 MLX5_FLOW_LAYER_INNER_L4)
215 #define MLX5_FLOW_LAYER_L2 \
216 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
217 #define MLX5_FLOW_LAYER_L3_IPV4 \
218 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
219 #define MLX5_FLOW_LAYER_L3_IPV6 \
220 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
221 #define MLX5_FLOW_LAYER_L3 \
222 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
223 #define MLX5_FLOW_LAYER_L4 \
224 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
227 #define MLX5_FLOW_ACTION_DROP (1u << 0)
228 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
229 #define MLX5_FLOW_ACTION_RSS (1u << 2)
230 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
231 #define MLX5_FLOW_ACTION_MARK (1u << 4)
232 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
233 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
234 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
235 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
236 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
237 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
238 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
239 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
240 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
241 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
242 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
243 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
244 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
245 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
246 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
247 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
248 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
249 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
250 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
251 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
252 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
253 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
254 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
255 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
256 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
257 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
258 #define MLX5_FLOW_ACTION_METER (1ull << 31)
259 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
260 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
261 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
262 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
263 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
264 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
265 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
266 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
267 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
268 #define MLX5_FLOW_ACTION_CT (1ull << 41)
270 #define MLX5_FLOW_FATE_ACTIONS \
271 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
272 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
273 MLX5_FLOW_ACTION_DEFAULT_MISS | \
274 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
276 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
277 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
278 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
280 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
281 MLX5_FLOW_ACTION_SET_IPV4_DST | \
282 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
283 MLX5_FLOW_ACTION_SET_IPV6_DST | \
284 MLX5_FLOW_ACTION_SET_TP_SRC | \
285 MLX5_FLOW_ACTION_SET_TP_DST | \
286 MLX5_FLOW_ACTION_SET_TTL | \
287 MLX5_FLOW_ACTION_DEC_TTL | \
288 MLX5_FLOW_ACTION_SET_MAC_SRC | \
289 MLX5_FLOW_ACTION_SET_MAC_DST | \
290 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
291 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
292 MLX5_FLOW_ACTION_INC_TCP_ACK | \
293 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
294 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
295 MLX5_FLOW_ACTION_SET_TAG | \
296 MLX5_FLOW_ACTION_MARK_EXT | \
297 MLX5_FLOW_ACTION_SET_META | \
298 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
299 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
300 MLX5_FLOW_ACTION_MODIFY_FIELD)
302 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
303 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
305 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
308 #define IPPROTO_MPLS 137
311 /* UDP port number for MPLS */
312 #define MLX5_UDP_PORT_MPLS 6635
314 /* UDP port numbers for VxLAN. */
315 #define MLX5_UDP_PORT_VXLAN 4789
316 #define MLX5_UDP_PORT_VXLAN_GPE 4790
318 /* UDP port numbers for GENEVE. */
319 #define MLX5_UDP_PORT_GENEVE 6081
321 /* Lowest priority indicator. */
322 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
325 * Max priority for ingress\egress flow groups
326 * greater than 0 and for any transfer flow group.
327 * From user configation: 0 - 21843.
329 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
332 * Number of sub priorities.
333 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
334 * matching on the NIC (firmware dependent) L4 most have the higher priority
335 * followed by L3 and ending with L2.
337 #define MLX5_PRIORITY_MAP_L2 2
338 #define MLX5_PRIORITY_MAP_L3 1
339 #define MLX5_PRIORITY_MAP_L4 0
340 #define MLX5_PRIORITY_MAP_MAX 3
342 /* Valid layer type for IPV4 RSS. */
343 #define MLX5_IPV4_LAYER_TYPES \
344 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \
345 RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
346 RTE_ETH_RSS_NONFRAG_IPV4_OTHER)
348 /* IBV hash source bits for IPV4. */
349 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
351 /* Valid layer type for IPV6 RSS. */
352 #define MLX5_IPV6_LAYER_TYPES \
353 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
354 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | \
355 RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER)
357 /* IBV hash source bits for IPV6. */
358 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
360 /* IBV hash bits for L3 SRC. */
361 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
363 /* IBV hash bits for L3 DST. */
364 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
366 /* IBV hash bits for TCP. */
367 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
368 IBV_RX_HASH_DST_PORT_TCP)
370 /* IBV hash bits for UDP. */
371 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
372 IBV_RX_HASH_DST_PORT_UDP)
374 /* IBV hash bits for L4 SRC. */
375 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
376 IBV_RX_HASH_SRC_PORT_UDP)
378 /* IBV hash bits for L4 DST. */
379 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
380 IBV_RX_HASH_DST_PORT_UDP)
382 /* Geneve header first 16Bit */
383 #define MLX5_GENEVE_VER_MASK 0x3
384 #define MLX5_GENEVE_VER_SHIFT 14
385 #define MLX5_GENEVE_VER_VAL(a) \
386 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
387 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
388 #define MLX5_GENEVE_OPTLEN_SHIFT 8
389 #define MLX5_GENEVE_OPTLEN_VAL(a) \
390 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
391 #define MLX5_GENEVE_OAMF_MASK 0x1
392 #define MLX5_GENEVE_OAMF_SHIFT 7
393 #define MLX5_GENEVE_OAMF_VAL(a) \
394 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
395 #define MLX5_GENEVE_CRITO_MASK 0x1
396 #define MLX5_GENEVE_CRITO_SHIFT 6
397 #define MLX5_GENEVE_CRITO_VAL(a) \
398 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
399 #define MLX5_GENEVE_RSVD_MASK 0x3F
400 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
402 * The length of the Geneve options fields, expressed in four byte multiples,
403 * not including the eight byte fixed tunnel.
405 #define MLX5_GENEVE_OPT_LEN_0 14
406 #define MLX5_GENEVE_OPT_LEN_1 63
408 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
409 sizeof(struct rte_ipv4_hdr))
410 /* GTP extension header flag. */
411 #define MLX5_GTP_EXT_HEADER_FLAG 4
413 /* GTP extension header PDU type shift. */
414 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
416 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
417 #define MLX5_IPV4_FRAG_OFFSET_MASK \
418 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
420 /* Specific item's fields can accept a range of values (using spec and last). */
421 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
422 #define MLX5_ITEM_RANGE_ACCEPTED true
424 /* Software header modify action numbers of a flow. */
425 #define MLX5_ACT_NUM_MDF_IPV4 1
426 #define MLX5_ACT_NUM_MDF_IPV6 4
427 #define MLX5_ACT_NUM_MDF_MAC 2
428 #define MLX5_ACT_NUM_MDF_VID 1
429 #define MLX5_ACT_NUM_MDF_PORT 2
430 #define MLX5_ACT_NUM_MDF_TTL 1
431 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
432 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
433 #define MLX5_ACT_NUM_MDF_TCPACK 1
434 #define MLX5_ACT_NUM_SET_REG 1
435 #define MLX5_ACT_NUM_SET_TAG 1
436 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
437 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
438 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
439 #define MLX5_ACT_NUM_SET_DSCP 1
441 /* Maximum number of fields to modify in MODIFY_FIELD */
442 #define MLX5_ACT_MAX_MOD_FIELDS 5
444 /* Syndrome bits definition for connection tracking. */
445 #define MLX5_CT_SYNDROME_VALID (0x0 << 6)
446 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6)
447 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6)
448 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1)
449 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0)
451 enum mlx5_flow_drv_type {
454 MLX5_FLOW_TYPE_VERBS,
458 /* Fate action type. */
459 enum mlx5_flow_fate_type {
460 MLX5_FLOW_FATE_NONE, /* Egress flow. */
461 MLX5_FLOW_FATE_QUEUE,
463 MLX5_FLOW_FATE_PORT_ID,
465 MLX5_FLOW_FATE_DEFAULT_MISS,
466 MLX5_FLOW_FATE_SHARED_RSS,
471 /* Matcher PRM representation */
472 struct mlx5_flow_dv_match_params {
474 /**< Size of match value. Do NOT split size and key! */
475 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
476 /**< Matcher value. This value is used as the mask or as a key. */
479 /* Matcher structure. */
480 struct mlx5_flow_dv_matcher {
481 struct mlx5_list_entry entry; /**< Pointer to the next element. */
482 struct mlx5_flow_tbl_resource *tbl;
483 /**< Pointer to the table(group) the matcher associated with. */
484 void *matcher_object; /**< Pointer to DV matcher */
485 uint16_t crc; /**< CRC of key. */
486 uint16_t priority; /**< Priority of matcher. */
487 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
490 #define MLX5_ENCAP_MAX_LEN 132
492 /* Encap/decap resource structure. */
493 struct mlx5_flow_dv_encap_decap_resource {
494 struct mlx5_list_entry entry;
495 /* Pointer to next element. */
496 uint32_t refcnt; /**< Reference counter. */
498 /**< Encap/decap action object. */
499 uint8_t buf[MLX5_ENCAP_MAX_LEN];
501 uint8_t reformat_type;
503 uint64_t flags; /**< Flags for RDMA API. */
504 uint32_t idx; /**< Index for the index memory pool. */
507 /* Tag resource structure. */
508 struct mlx5_flow_dv_tag_resource {
509 struct mlx5_list_entry entry;
510 /**< hash list entry for tag resource, tag value as the key. */
512 /**< Tag action object. */
513 uint32_t refcnt; /**< Reference counter. */
514 uint32_t idx; /**< Index for the index memory pool. */
515 uint32_t tag_id; /**< Tag ID. */
518 /* Modify resource structure */
519 struct mlx5_flow_dv_modify_hdr_resource {
520 struct mlx5_list_entry entry;
521 void *action; /**< Modify header action object. */
523 /* Key area for hash list matching: */
524 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
525 uint8_t actions_num; /**< Number of modification actions. */
526 bool root; /**< Whether action is in root table. */
527 struct mlx5_modification_cmd actions[];
528 /**< Modification actions. */
531 /* Modify resource key of the hash organization. */
532 union mlx5_flow_modify_hdr_key {
534 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
535 uint32_t actions_num:5; /**< Number of modification actions. */
536 uint32_t group:19; /**< Flow group id. */
537 uint32_t cksum; /**< Actions check sum. */
539 uint64_t v64; /**< full 64bits value of key */
542 /* Jump action resource structure. */
543 struct mlx5_flow_dv_jump_tbl_resource {
544 void *action; /**< Pointer to the rdma core action. */
547 /* Port ID resource structure. */
548 struct mlx5_flow_dv_port_id_action_resource {
549 struct mlx5_list_entry entry;
550 void *action; /**< Action object. */
551 uint32_t port_id; /**< Port ID value. */
552 uint32_t idx; /**< Indexed pool memory index. */
555 /* Push VLAN action resource structure */
556 struct mlx5_flow_dv_push_vlan_action_resource {
557 struct mlx5_list_entry entry; /* Cache entry. */
558 void *action; /**< Action object. */
559 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
560 rte_be32_t vlan_tag; /**< VLAN tag value. */
561 uint32_t idx; /**< Indexed pool memory index. */
564 /* Metadata register copy table entry. */
565 struct mlx5_flow_mreg_copy_resource {
567 * Hash list entry for copy table.
568 * - Key is 32/64-bit MARK action ID.
569 * - MUST be the first entry.
571 struct mlx5_list_entry hlist_ent;
572 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
573 /* List entry for device flows. */
575 uint32_t rix_flow; /* Built flow for copy. */
579 /* Table tunnel parameter. */
580 struct mlx5_flow_tbl_tunnel_prm {
581 const struct mlx5_flow_tunnel *tunnel;
586 /* Table data structure of the hash organization. */
587 struct mlx5_flow_tbl_data_entry {
588 struct mlx5_list_entry entry;
589 /**< hash list entry, 64-bits key inside. */
590 struct mlx5_flow_tbl_resource tbl;
591 /**< flow table resource. */
592 struct mlx5_list *matchers;
593 /**< matchers' header associated with the flow table. */
594 struct mlx5_flow_dv_jump_tbl_resource jump;
595 /**< jump resource, at most one for each table created. */
596 uint32_t idx; /**< index for the indexed mempool. */
597 /**< tunnel offload */
598 const struct mlx5_flow_tunnel *tunnel;
601 uint32_t tunnel_offload:1; /* Tunnel offload table or not. */
602 uint32_t is_egress:1; /**< Egress table. */
603 uint32_t is_transfer:1; /**< Transfer table. */
604 uint32_t dummy:1; /**< DR table. */
605 uint32_t id:22; /**< Table ID. */
606 uint32_t reserve:5; /**< Reserved to future using. */
607 uint32_t level; /**< Table level. */
610 /* Sub rdma-core actions list. */
611 struct mlx5_flow_sub_actions_list {
612 uint32_t actions_num; /**< Number of sample actions. */
613 uint64_t action_flags;
614 void *dr_queue_action;
617 void *dr_port_id_action;
618 void *dr_encap_action;
619 void *dr_jump_action;
622 /* Sample sub-actions resource list. */
623 struct mlx5_flow_sub_actions_idx {
624 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
625 uint32_t rix_tag; /**< Index to the tag action. */
626 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
627 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
628 uint32_t rix_jump; /**< Index to the jump action resource. */
631 /* Sample action resource structure. */
632 struct mlx5_flow_dv_sample_resource {
633 struct mlx5_list_entry entry; /**< Cache entry. */
635 void *verbs_action; /**< Verbs sample action object. */
636 void **sub_actions; /**< Sample sub-action array. */
638 struct rte_eth_dev *dev; /**< Device registers the action. */
639 uint32_t idx; /** Sample object index. */
640 uint8_t ft_type; /** Flow Table Type */
641 uint32_t ft_id; /** Flow Table Level */
642 uint32_t ratio; /** Sample Ratio */
643 uint64_t set_action; /** Restore reg_c0 value */
644 void *normal_path_tbl; /** Flow Table pointer */
645 struct mlx5_flow_sub_actions_idx sample_idx;
646 /**< Action index resources. */
647 struct mlx5_flow_sub_actions_list sample_act;
648 /**< Action resources. */
651 #define MLX5_MAX_DEST_NUM 2
653 /* Destination array action resource structure. */
654 struct mlx5_flow_dv_dest_array_resource {
655 struct mlx5_list_entry entry; /**< Cache entry. */
656 uint32_t idx; /** Destination array action object index. */
657 uint8_t ft_type; /** Flow Table Type */
658 uint8_t num_of_dest; /**< Number of destination actions. */
659 struct rte_eth_dev *dev; /**< Device registers the action. */
660 void *action; /**< Pointer to the rdma core action. */
661 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
662 /**< Action index resources. */
663 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
664 /**< Action resources. */
667 /* PMD flow priority for tunnel */
668 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
669 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
672 /** Device flow handle structure for DV mode only. */
673 struct mlx5_flow_handle_dv {
675 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
676 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
677 /**< Pointer to modify header resource in cache. */
678 uint32_t rix_encap_decap;
679 /**< Index to encap/decap resource in cache. */
680 uint32_t rix_push_vlan;
681 /**< Index to push VLAN action resource in cache. */
683 /**< Index to the tag action. */
685 /**< Index to sample action resource in cache. */
686 uint32_t rix_dest_array;
687 /**< Index to destination array resource in cache. */
690 /** Device flow handle structure: used both for creating & destroying. */
691 struct mlx5_flow_handle {
692 SILIST_ENTRY(uint32_t)next;
693 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
694 /**< Index to next device flow handle. */
696 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
697 void *drv_flow; /**< pointer to driver flow object. */
698 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
699 uint32_t is_meter_flow_id:1; /**< Indicate if flow_id is for meter. */
700 uint32_t fate_action:3; /**< Fate action type. */
701 uint32_t flex_item; /**< referenced Flex Item bitmask. */
703 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
704 uint32_t rix_jump; /**< Index to the jump action resource. */
705 uint32_t rix_port_id_action;
706 /**< Index to port ID action resource. */
708 /**< Generic value indicates the fate action. */
709 uint32_t rix_default_fate;
710 /**< Indicates default miss fate action. */
712 /**< Indicates shared RSS fate action. */
714 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
715 struct mlx5_flow_handle_dv dvh;
720 * Size for Verbs device flow handle structure only. Do not use the DV only
721 * structure in Verbs. No DV flows attributes will be accessed.
722 * Macro offsetof() could also be used here.
724 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
725 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
726 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
728 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
731 /** Device flow structure only for DV flow creation. */
732 struct mlx5_flow_dv_workspace {
733 uint32_t group; /**< The group index. */
734 uint32_t table_id; /**< Flow table identifier. */
735 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
736 int actions_n; /**< number of actions. */
737 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
738 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
739 /**< Pointer to encap/decap resource in cache. */
740 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
741 /**< Pointer to push VLAN action resource in cache. */
742 struct mlx5_flow_dv_tag_resource *tag_resource;
743 /**< pointer to the tag action. */
744 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
745 /**< Pointer to port ID action resource. */
746 struct mlx5_flow_dv_jump_tbl_resource *jump;
747 /**< Pointer to the jump action resource. */
748 struct mlx5_flow_dv_match_params value;
749 /**< Holds the value that the packet is compared to. */
750 struct mlx5_flow_dv_sample_resource *sample_res;
751 /**< Pointer to the sample action resource. */
752 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
753 /**< Pointer to the destination array resource. */
756 #ifdef HAVE_INFINIBAND_VERBS_H
758 * Maximal Verbs flow specifications & actions size.
759 * Some elements are mutually exclusive, but enough space should be allocated.
760 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
761 * 2. One tunnel header (exception: GRE + MPLS),
762 * SPEC length: GRE == tunnel.
763 * Actions: 1. 1 Mark OR Flag.
764 * 2. 1 Drop (if any).
765 * 3. No limitation for counters, but it makes no sense to support too
766 * many counters in a single device flow.
768 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
769 #define MLX5_VERBS_MAX_SPEC_SIZE \
771 (2 * (sizeof(struct ibv_flow_spec_eth) + \
772 sizeof(struct ibv_flow_spec_ipv6) + \
773 sizeof(struct ibv_flow_spec_tcp_udp)) + \
774 sizeof(struct ibv_flow_spec_gre) + \
775 sizeof(struct ibv_flow_spec_mpls)) \
778 #define MLX5_VERBS_MAX_SPEC_SIZE \
780 (2 * (sizeof(struct ibv_flow_spec_eth) + \
781 sizeof(struct ibv_flow_spec_ipv6) + \
782 sizeof(struct ibv_flow_spec_tcp_udp)) + \
783 sizeof(struct ibv_flow_spec_tunnel)) \
787 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
788 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
789 #define MLX5_VERBS_MAX_ACT_SIZE \
791 sizeof(struct ibv_flow_spec_action_tag) + \
792 sizeof(struct ibv_flow_spec_action_drop) + \
793 sizeof(struct ibv_flow_spec_counter_action) * 4 \
796 #define MLX5_VERBS_MAX_ACT_SIZE \
798 sizeof(struct ibv_flow_spec_action_tag) + \
799 sizeof(struct ibv_flow_spec_action_drop) \
803 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
804 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
806 /** Device flow structure only for Verbs flow creation. */
807 struct mlx5_flow_verbs_workspace {
808 unsigned int size; /**< Size of the attribute. */
809 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
810 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
811 /**< Specifications & actions buffer of verbs flow. */
813 #endif /* HAVE_INFINIBAND_VERBS_H */
815 #define MLX5_SCALE_FLOW_GROUP_BIT 0
816 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
818 /** Maximal number of device sub-flows supported. */
819 #define MLX5_NUM_MAX_DEV_FLOWS 32
822 * tunnel offload rules type
824 enum mlx5_tof_rule_type {
825 MLX5_TUNNEL_OFFLOAD_NONE = 0,
826 MLX5_TUNNEL_OFFLOAD_SET_RULE,
827 MLX5_TUNNEL_OFFLOAD_MATCH_RULE,
828 MLX5_TUNNEL_OFFLOAD_MISS_RULE,
831 /** Device flow structure. */
834 struct rte_flow *flow; /**< Pointer to the main flow. */
835 uint32_t flow_idx; /**< The memory pool index to the main flow. */
836 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
838 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
839 bool external; /**< true if the flow is created external to PMD. */
840 uint8_t ingress:1; /**< 1 if the flow is ingress. */
841 uint8_t skip_scale:2;
843 * Each Bit be set to 1 if Skip the scale the flow group with factor.
844 * If bit0 be set to 1, then skip the scale the original flow group;
845 * If bit1 be set to 1, then skip the scale the jump flow group if
846 * having jump action.
847 * 00: Enable scale in a flow, default value.
848 * 01: Skip scale the flow group with factor, enable scale the group
850 * 10: Enable scale the group with factor, skip scale the group of
852 * 11: Skip scale the table with factor both for flow group and jump
856 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
857 struct mlx5_flow_dv_workspace dv;
859 #ifdef HAVE_INFINIBAND_VERBS_H
860 struct mlx5_flow_verbs_workspace verbs;
863 struct mlx5_flow_handle *handle;
864 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
865 const struct mlx5_flow_tunnel *tunnel;
866 enum mlx5_tof_rule_type tof_type;
869 /* Flow meter state. */
870 #define MLX5_FLOW_METER_DISABLE 0
871 #define MLX5_FLOW_METER_ENABLE 1
873 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
874 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
876 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
878 #define MLX5_MAN_WIDTH 8
879 /* Legacy Meter parameter structure. */
880 struct mlx5_legacy_flow_meter {
881 struct mlx5_flow_meter_info fm;
882 /* Must be the first in struct. */
883 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
884 /**< Pointer to the next flow meter structure. */
886 /* Index to meter object. */
889 #define MLX5_MAX_TUNNELS 256
890 #define MLX5_TNL_MISS_RULE_PRIORITY 3
891 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
894 * When tunnel offload is active, all JUMP group ids are converted
895 * using the same method. That conversion is applied both to tunnel and
896 * regular rule types.
897 * Group ids used in tunnel rules are relative to it's tunnel (!).
898 * Application can create number of steer rules, using the same
899 * tunnel, with different group id in each rule.
900 * Each tunnel stores its groups internally in PMD tunnel object.
901 * Groups used in regular rules do not belong to any tunnel and are stored
905 struct mlx5_flow_tunnel {
906 LIST_ENTRY(mlx5_flow_tunnel) chain;
907 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
908 uint32_t tunnel_id; /** unique tunnel ID */
910 struct rte_flow_action action;
911 struct rte_flow_item item;
912 struct mlx5_hlist *groups; /** tunnel groups */
915 /** PMD tunnel related context */
916 struct mlx5_flow_tunnel_hub {
918 * Access to the list MUST be MT protected
920 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
921 /* protect access to the tunnels list */
923 struct mlx5_hlist *groups; /** non tunnel groups */
926 /* convert jump group to flow table ID in tunnel rules */
927 struct tunnel_tbl_entry {
928 struct mlx5_list_entry hash;
934 static inline uint32_t
935 tunnel_id_to_flow_tbl(uint32_t id)
937 return id | (1u << 16);
940 static inline uint32_t
941 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
943 return flow_tbl & ~(1u << 16);
946 union tunnel_tbl_key {
954 static inline struct mlx5_flow_tunnel_hub *
955 mlx5_tunnel_hub(struct rte_eth_dev *dev)
957 struct mlx5_priv *priv = dev->data->dev_private;
958 return priv->sh->tunnel_hub;
962 is_tunnel_offload_active(const struct rte_eth_dev *dev)
964 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
965 const struct mlx5_priv *priv = dev->data->dev_private;
966 return !!priv->config.dv_miss_info;
974 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type)
976 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE;
980 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type)
982 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE;
985 static inline const struct mlx5_flow_tunnel *
986 flow_actions_to_tunnel(const struct rte_flow_action actions[])
988 return actions[0].conf;
991 static inline const struct mlx5_flow_tunnel *
992 flow_items_to_tunnel(const struct rte_flow_item items[])
994 return items[0].spec;
997 /* Flow structure. */
999 uint32_t dev_handles;
1000 /**< Device flow handles that are part of the flow. */
1002 uint32_t drv_type:2; /**< Driver type. */
1004 uint32_t meter:24; /**< Holds flow meter id. */
1005 uint32_t indirect_type:2; /**< Indirect action type. */
1006 uint32_t rix_mreg_copy;
1007 /**< Index to metadata register copy table resource. */
1008 uint32_t counter; /**< Holds flow counter. */
1009 uint32_t tunnel_id; /**< Tunnel id */
1011 uint32_t age; /**< Holds ASO age bit index. */
1012 uint32_t ct; /**< Holds ASO CT index. */
1014 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1018 * Define list of valid combinations of RX Hash fields
1019 * (see enum ibv_rx_hash_fields).
1021 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1022 #define MLX5_RSS_HASH_IPV4_TCP \
1023 (MLX5_RSS_HASH_IPV4 | \
1024 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1025 #define MLX5_RSS_HASH_IPV4_UDP \
1026 (MLX5_RSS_HASH_IPV4 | \
1027 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1028 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1029 #define MLX5_RSS_HASH_IPV6_TCP \
1030 (MLX5_RSS_HASH_IPV6 | \
1031 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1032 #define MLX5_RSS_HASH_IPV6_UDP \
1033 (MLX5_RSS_HASH_IPV6 | \
1034 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1035 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1036 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1037 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1038 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1039 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1040 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1041 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1042 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1043 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1044 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1045 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1046 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1047 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1048 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1049 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1050 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1051 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1052 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1053 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1054 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1055 #define MLX5_RSS_HASH_NONE 0ULL
1058 /* extract next protocol type from Ethernet & VLAN headers */
1059 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1060 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1061 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1062 (_prt) = rte_be_to_cpu_16((_prt)); \
1065 /* array of valid combinations of RX Hash fields for RSS */
1066 static const uint64_t mlx5_rss_hash_fields[] = {
1068 MLX5_RSS_HASH_IPV4_TCP,
1069 MLX5_RSS_HASH_IPV4_UDP,
1071 MLX5_RSS_HASH_IPV6_TCP,
1072 MLX5_RSS_HASH_IPV6_UDP,
1076 /* Shared RSS action structure */
1077 struct mlx5_shared_action_rss {
1078 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1079 uint32_t refcnt; /**< Atomically accessed refcnt. */
1080 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1081 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1082 struct mlx5_ind_table_obj *ind_tbl;
1083 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1084 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1085 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1086 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1089 struct rte_flow_action_handle {
1093 /* Thread specific flow workspace intermediate data. */
1094 struct mlx5_flow_workspace {
1095 /* If creating another flow in same thread, push new as stack. */
1096 struct mlx5_flow_workspace *prev;
1097 struct mlx5_flow_workspace *next;
1098 uint32_t inuse; /* can't create new flow with current. */
1099 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1100 struct mlx5_flow_rss_desc rss_desc;
1101 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1102 uint32_t flow_idx; /* Intermediate device flow index. */
1103 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1104 struct mlx5_flow_meter_policy *policy;
1105 /* The meter policy used by meter in flow. */
1106 struct mlx5_flow_meter_policy *final_policy;
1107 /* The final policy when meter policy is hierarchy. */
1108 uint32_t skip_matcher_reg:1;
1109 /* Indicates if need to skip matcher register in translate. */
1110 uint32_t mark:1; /* Indicates if flow contains mark action. */
1113 struct mlx5_flow_split_info {
1114 uint32_t external:1;
1115 /**< True if flow is created by request external to PMD. */
1116 uint32_t prefix_mark:1; /**< Prefix subflow mark flag. */
1117 uint32_t skip_scale:8; /**< Skip the scale the table with factor. */
1118 uint32_t flow_idx; /**< This memory pool index to the flow. */
1119 uint32_t table_id; /**< Flow table identifier. */
1120 uint64_t prefix_layers; /**< Prefix subflow layers. */
1123 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1124 const struct rte_flow_attr *attr,
1125 const struct rte_flow_item items[],
1126 const struct rte_flow_action actions[],
1129 struct rte_flow_error *error);
1130 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1131 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1132 const struct rte_flow_item items[],
1133 const struct rte_flow_action actions[], struct rte_flow_error *error);
1134 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1135 struct mlx5_flow *dev_flow,
1136 const struct rte_flow_attr *attr,
1137 const struct rte_flow_item items[],
1138 const struct rte_flow_action actions[],
1139 struct rte_flow_error *error);
1140 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1141 struct rte_flow_error *error);
1142 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1143 struct rte_flow *flow);
1144 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1145 struct rte_flow *flow);
1146 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1147 struct rte_flow *flow,
1148 const struct rte_flow_action *actions,
1150 struct rte_flow_error *error);
1151 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1152 struct mlx5_flow_meter_info *fm,
1154 uint8_t domain_bitmap);
1155 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1156 struct mlx5_flow_meter_info *fm);
1157 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1158 typedef struct mlx5_flow_meter_sub_policy *
1159 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1160 (struct rte_eth_dev *dev,
1161 struct mlx5_flow_meter_policy *mtr_policy,
1162 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1163 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t)
1164 (struct rte_eth_dev *dev,
1165 struct mlx5_flow_meter_info *fm,
1167 const struct rte_flow_item *item,
1168 struct rte_flow_error *error);
1169 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t)
1170 (struct rte_eth_dev *dev,
1171 struct mlx5_flow_meter_policy *mtr_policy);
1172 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1173 (struct rte_eth_dev *dev);
1174 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1176 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1177 (struct rte_eth_dev *dev);
1178 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1180 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1182 bool clear, uint64_t *pkts,
1184 typedef int (*mlx5_flow_get_aged_flows_t)
1185 (struct rte_eth_dev *dev,
1187 uint32_t nb_contexts,
1188 struct rte_flow_error *error);
1189 typedef int (*mlx5_flow_action_validate_t)
1190 (struct rte_eth_dev *dev,
1191 const struct rte_flow_indir_action_conf *conf,
1192 const struct rte_flow_action *action,
1193 struct rte_flow_error *error);
1194 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1195 (struct rte_eth_dev *dev,
1196 const struct rte_flow_indir_action_conf *conf,
1197 const struct rte_flow_action *action,
1198 struct rte_flow_error *error);
1199 typedef int (*mlx5_flow_action_destroy_t)
1200 (struct rte_eth_dev *dev,
1201 struct rte_flow_action_handle *action,
1202 struct rte_flow_error *error);
1203 typedef int (*mlx5_flow_action_update_t)
1204 (struct rte_eth_dev *dev,
1205 struct rte_flow_action_handle *action,
1207 struct rte_flow_error *error);
1208 typedef int (*mlx5_flow_action_query_t)
1209 (struct rte_eth_dev *dev,
1210 const struct rte_flow_action_handle *action,
1212 struct rte_flow_error *error);
1213 typedef int (*mlx5_flow_sync_domain_t)
1214 (struct rte_eth_dev *dev,
1217 typedef int (*mlx5_flow_validate_mtr_acts_t)
1218 (struct rte_eth_dev *dev,
1219 const struct rte_flow_action *actions[RTE_COLORS],
1220 struct rte_flow_attr *attr,
1222 uint8_t *domain_bitmap,
1223 uint8_t *policy_mode,
1224 struct rte_mtr_error *error);
1225 typedef int (*mlx5_flow_create_mtr_acts_t)
1226 (struct rte_eth_dev *dev,
1227 struct mlx5_flow_meter_policy *mtr_policy,
1228 const struct rte_flow_action *actions[RTE_COLORS],
1229 struct rte_mtr_error *error);
1230 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1231 (struct rte_eth_dev *dev,
1232 struct mlx5_flow_meter_policy *mtr_policy);
1233 typedef int (*mlx5_flow_create_policy_rules_t)
1234 (struct rte_eth_dev *dev,
1235 struct mlx5_flow_meter_policy *mtr_policy);
1236 typedef void (*mlx5_flow_destroy_policy_rules_t)
1237 (struct rte_eth_dev *dev,
1238 struct mlx5_flow_meter_policy *mtr_policy);
1239 typedef int (*mlx5_flow_create_def_policy_t)
1240 (struct rte_eth_dev *dev);
1241 typedef void (*mlx5_flow_destroy_def_policy_t)
1242 (struct rte_eth_dev *dev);
1243 typedef int (*mlx5_flow_discover_priorities_t)
1244 (struct rte_eth_dev *dev,
1245 const uint16_t *vprio, int vprio_n);
1246 typedef struct rte_flow_item_flex_handle *(*mlx5_flow_item_create_t)
1247 (struct rte_eth_dev *dev,
1248 const struct rte_flow_item_flex_conf *conf,
1249 struct rte_flow_error *error);
1250 typedef int (*mlx5_flow_item_release_t)
1251 (struct rte_eth_dev *dev,
1252 const struct rte_flow_item_flex_handle *handle,
1253 struct rte_flow_error *error);
1254 typedef int (*mlx5_flow_item_update_t)
1255 (struct rte_eth_dev *dev,
1256 const struct rte_flow_item_flex_handle *handle,
1257 const struct rte_flow_item_flex_conf *conf,
1258 struct rte_flow_error *error);
1260 struct mlx5_flow_driver_ops {
1261 mlx5_flow_validate_t validate;
1262 mlx5_flow_prepare_t prepare;
1263 mlx5_flow_translate_t translate;
1264 mlx5_flow_apply_t apply;
1265 mlx5_flow_remove_t remove;
1266 mlx5_flow_destroy_t destroy;
1267 mlx5_flow_query_t query;
1268 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1269 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1270 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1271 mlx5_flow_mtr_alloc_t create_meter;
1272 mlx5_flow_mtr_free_t free_meter;
1273 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1274 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1275 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1276 mlx5_flow_create_policy_rules_t create_policy_rules;
1277 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1278 mlx5_flow_create_def_policy_t create_def_policy;
1279 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1280 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1281 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create;
1282 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq;
1283 mlx5_flow_counter_alloc_t counter_alloc;
1284 mlx5_flow_counter_free_t counter_free;
1285 mlx5_flow_counter_query_t counter_query;
1286 mlx5_flow_get_aged_flows_t get_aged_flows;
1287 mlx5_flow_action_validate_t action_validate;
1288 mlx5_flow_action_create_t action_create;
1289 mlx5_flow_action_destroy_t action_destroy;
1290 mlx5_flow_action_update_t action_update;
1291 mlx5_flow_action_query_t action_query;
1292 mlx5_flow_sync_domain_t sync_domain;
1293 mlx5_flow_discover_priorities_t discover_priorities;
1294 mlx5_flow_item_create_t item_create;
1295 mlx5_flow_item_release_t item_release;
1296 mlx5_flow_item_update_t item_update;
1301 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1303 struct flow_grp_info {
1304 uint64_t external:1;
1305 uint64_t transfer:1;
1306 uint64_t fdb_def_rule:1;
1307 /* force standard group translation */
1308 uint64_t std_tbl_fix:1;
1309 uint64_t skip_scale:2;
1313 tunnel_use_standard_attr_group_translate
1314 (const struct rte_eth_dev *dev,
1315 const struct rte_flow_attr *attr,
1316 const struct mlx5_flow_tunnel *tunnel,
1317 enum mlx5_tof_rule_type tof_rule_type)
1321 if (!is_tunnel_offload_active(dev))
1322 /* no tunnel offload API */
1326 * OvS will use jump to group 0 in tunnel steer rule.
1327 * If tunnel steer rule starts from group 0 (attr.group == 0)
1328 * that 0 group must be translated with standard method.
1329 * attr.group == 0 in tunnel match rule translated with tunnel
1332 verdict = !attr->group &&
1333 is_flow_tunnel_steer_rule(tof_rule_type);
1336 * non-tunnel group translation uses standard method for
1337 * root group only: attr.group == 0
1339 verdict = !attr->group;
1346 * Get DV flow aso meter by index.
1349 * Pointer to the Ethernet device structure.
1351 * mlx5 flow aso meter index in the container.
1353 * mlx5 flow aso meter pool in the container,
1356 * Pointer to the aso meter, NULL otherwise.
1358 static inline struct mlx5_aso_mtr *
1359 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1361 struct mlx5_aso_mtr_pool *pool;
1362 struct mlx5_aso_mtr_pools_mng *pools_mng =
1363 &priv->sh->mtrmng->pools_mng;
1365 /* Decrease to original index. */
1367 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1368 rte_rwlock_read_lock(&pools_mng->resize_mtrwl);
1369 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1370 rte_rwlock_read_unlock(&pools_mng->resize_mtrwl);
1371 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1374 static __rte_always_inline const struct rte_flow_item *
1375 mlx5_find_end_item(const struct rte_flow_item *item)
1377 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1381 static __rte_always_inline bool
1382 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1384 struct rte_flow_item_integrity test = *item;
1387 test.ipv4_csum_ok = 0;
1388 test.l4_csum_ok = 0;
1389 return (test.value == 0);
1393 * Get ASO CT action by device and index.
1396 * Pointer to the Ethernet device structure.
1398 * Index to the ASO CT action.
1401 * The specified ASO CT action pointer.
1403 static inline struct mlx5_aso_ct_action *
1404 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx)
1406 struct mlx5_priv *priv = dev->data->dev_private;
1407 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
1408 struct mlx5_aso_ct_pool *pool;
1411 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n);
1412 /* Bit operation AND could be used. */
1413 rte_rwlock_read_lock(&mng->resize_rwl);
1414 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL];
1415 rte_rwlock_read_unlock(&mng->resize_rwl);
1416 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];
1420 * Get ASO CT action by owner & index.
1423 * Pointer to the Ethernet device structure.
1425 * Index to the ASO CT action and owner port combination.
1428 * The specified ASO CT action pointer.
1430 static inline struct mlx5_aso_ct_action *
1431 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx)
1433 struct mlx5_priv *priv = dev->data->dev_private;
1434 struct mlx5_aso_ct_action *ct;
1435 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
1436 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
1438 if (owner == PORT_ID(priv)) {
1439 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
1441 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
1443 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
1444 if (dev->data->dev_started != 1)
1446 ct = flow_aso_ct_get_by_dev_idx(owndev, idx);
1447 if (ct->peer != PORT_ID(priv))
1453 static inline uint16_t
1454 mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
1456 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
1457 return RTE_ETHER_TYPE_TEB;
1458 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
1459 return RTE_ETHER_TYPE_IPV4;
1460 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
1461 return RTE_ETHER_TYPE_IPV6;
1462 else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
1463 return RTE_ETHER_TYPE_MPLS;
1467 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1468 const struct mlx5_flow_tunnel *tunnel,
1469 uint32_t group, uint32_t *table,
1470 const struct flow_grp_info *flags,
1471 struct rte_flow_error *error);
1472 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1473 int tunnel, uint64_t layer_types,
1474 uint64_t hash_fields);
1475 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1476 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1477 uint32_t subpriority);
1478 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1479 const struct rte_flow_attr *attr);
1480 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1481 const struct rte_flow_attr *attr,
1482 uint32_t subpriority, bool external);
1483 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1484 enum mlx5_feature_name feature,
1486 struct rte_flow_error *error);
1487 const struct rte_flow_action *mlx5_flow_find_action
1488 (const struct rte_flow_action *actions,
1489 enum rte_flow_action_type action);
1490 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1491 const struct rte_flow_action *action,
1492 struct rte_flow_error *error);
1493 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1494 const struct rte_flow_attr *attr,
1495 struct rte_flow_error *error);
1496 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1497 const struct rte_flow_attr *attr,
1498 struct rte_flow_error *error);
1499 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1500 const struct rte_flow_attr *attr,
1501 struct rte_flow_error *error);
1502 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1503 uint64_t action_flags,
1504 const struct rte_flow_attr *attr,
1505 struct rte_flow_error *error);
1506 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1507 uint64_t action_flags,
1508 struct rte_eth_dev *dev,
1509 const struct rte_flow_attr *attr,
1510 struct rte_flow_error *error);
1511 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1512 uint64_t action_flags,
1513 struct rte_eth_dev *dev,
1514 const struct rte_flow_attr *attr,
1515 uint64_t item_flags,
1516 struct rte_flow_error *error);
1517 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1518 const struct rte_flow_attr *attr,
1519 struct rte_flow_error *error);
1520 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1521 const struct rte_flow_attr *attributes,
1522 struct rte_flow_error *error);
1523 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1524 const uint8_t *mask,
1525 const uint8_t *nic_mask,
1527 bool range_accepted,
1528 struct rte_flow_error *error);
1529 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1530 uint64_t item_flags, bool ext_vlan_sup,
1531 struct rte_flow_error *error);
1532 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1533 uint64_t item_flags,
1534 uint8_t target_protocol,
1535 struct rte_flow_error *error);
1536 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1537 uint64_t item_flags,
1538 const struct rte_flow_item *gre_item,
1539 struct rte_flow_error *error);
1540 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1541 uint64_t item_flags,
1543 uint16_t ether_type,
1544 const struct rte_flow_item_ipv4 *acc_mask,
1545 bool range_accepted,
1546 struct rte_flow_error *error);
1547 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1548 uint64_t item_flags,
1550 uint16_t ether_type,
1551 const struct rte_flow_item_ipv6 *acc_mask,
1552 struct rte_flow_error *error);
1553 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1554 const struct rte_flow_item *item,
1555 uint64_t item_flags,
1556 uint64_t prev_layer,
1557 struct rte_flow_error *error);
1558 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1559 uint64_t item_flags,
1560 uint8_t target_protocol,
1561 const struct rte_flow_item_tcp *flow_mask,
1562 struct rte_flow_error *error);
1563 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1564 uint64_t item_flags,
1565 uint8_t target_protocol,
1566 struct rte_flow_error *error);
1567 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1568 uint64_t item_flags,
1569 struct rte_eth_dev *dev,
1570 struct rte_flow_error *error);
1571 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev,
1573 const struct rte_flow_item *item,
1574 uint64_t item_flags,
1575 const struct rte_flow_attr *attr,
1576 struct rte_flow_error *error);
1577 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1578 uint64_t item_flags,
1579 struct rte_eth_dev *dev,
1580 struct rte_flow_error *error);
1581 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1582 uint64_t item_flags,
1583 uint8_t target_protocol,
1584 struct rte_flow_error *error);
1585 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1586 uint64_t item_flags,
1587 uint8_t target_protocol,
1588 struct rte_flow_error *error);
1589 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1590 uint64_t item_flags,
1591 uint8_t target_protocol,
1592 struct rte_flow_error *error);
1593 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1594 uint64_t item_flags,
1595 struct rte_eth_dev *dev,
1596 struct rte_flow_error *error);
1597 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1599 const struct rte_flow_item *geneve_item,
1600 struct rte_eth_dev *dev,
1601 struct rte_flow_error *error);
1602 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1603 uint64_t item_flags,
1605 uint16_t ether_type,
1606 const struct rte_flow_item_ecpri *acc_mask,
1607 struct rte_flow_error *error);
1608 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1609 struct mlx5_flow_meter_info *fm,
1611 uint8_t domain_bitmap);
1612 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1613 struct mlx5_flow_meter_info *fm);
1614 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1615 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1616 (struct rte_eth_dev *dev,
1617 struct mlx5_flow_meter_policy *mtr_policy,
1618 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1619 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
1620 struct mlx5_flow_meter_policy *mtr_policy);
1621 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1622 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev);
1623 int mlx5_action_handle_attach(struct rte_eth_dev *dev);
1624 int mlx5_action_handle_detach(struct rte_eth_dev *dev);
1625 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1626 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1627 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1629 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx);
1630 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1632 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1633 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx,
1634 struct mlx5_list_entry *oentry,
1636 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1637 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1638 uint32_t table_level, uint8_t egress, uint8_t transfer,
1639 bool external, const struct mlx5_flow_tunnel *tunnel,
1640 uint32_t group_id, uint8_t dummy,
1641 uint32_t table_id, struct rte_flow_error *error);
1643 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx);
1644 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1646 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1647 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx,
1648 struct mlx5_list_entry *oentry,
1650 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1652 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1654 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx);
1655 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1656 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx,
1657 struct mlx5_list_entry *oentry,
1659 void flow_dv_modify_clone_free_cb(void *tool_ctx,
1660 struct mlx5_list_entry *entry);
1662 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx);
1663 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1665 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1666 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx,
1667 struct mlx5_list_entry *entry,
1669 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1671 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1673 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx,
1675 void flow_dv_encap_decap_remove_cb(void *tool_ctx,
1676 struct mlx5_list_entry *entry);
1677 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx,
1678 struct mlx5_list_entry *entry,
1680 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx,
1681 struct mlx5_list_entry *entry);
1683 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1685 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx);
1686 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1688 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1690 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx);
1691 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1692 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx,
1693 struct mlx5_list_entry *entry, void *cb_ctx);
1694 void flow_dv_port_id_clone_free_cb(void *tool_ctx,
1695 struct mlx5_list_entry *entry);
1697 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1699 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx,
1701 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1702 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx,
1703 struct mlx5_list_entry *entry, void *cb_ctx);
1704 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx,
1705 struct mlx5_list_entry *entry);
1707 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1709 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx);
1710 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1711 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx,
1712 struct mlx5_list_entry *entry, void *cb_ctx);
1713 void flow_dv_sample_clone_free_cb(void *tool_ctx,
1714 struct mlx5_list_entry *entry);
1716 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1718 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx,
1720 void flow_dv_dest_array_remove_cb(void *tool_ctx,
1721 struct mlx5_list_entry *entry);
1722 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx,
1723 struct mlx5_list_entry *entry, void *cb_ctx);
1724 void flow_dv_dest_array_clone_free_cb(void *tool_ctx,
1725 struct mlx5_list_entry *entry);
1726 int flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
1727 void **action, struct rte_flow_error *error);
1729 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
1730 struct rte_flow_error *error);
1732 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1734 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1735 const struct rte_flow_item *item,
1736 struct rte_flow_error *error);
1737 void flow_release_workspace(void *data);
1738 int mlx5_flow_os_init_workspace_once(void);
1739 void *mlx5_flow_os_get_specific_workspace(void);
1740 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1741 void mlx5_flow_os_release_workspace(void);
1742 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1743 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1744 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1745 const struct rte_flow_action *actions[RTE_COLORS],
1746 struct rte_flow_attr *attr,
1748 uint8_t *domain_bitmap,
1749 uint8_t *policy_mode,
1750 struct rte_mtr_error *error);
1751 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1752 struct mlx5_flow_meter_policy *mtr_policy);
1753 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1754 struct mlx5_flow_meter_policy *mtr_policy,
1755 const struct rte_flow_action *actions[RTE_COLORS],
1756 struct rte_mtr_error *error);
1757 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1758 struct mlx5_flow_meter_policy *mtr_policy);
1759 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1760 struct mlx5_flow_meter_policy *mtr_policy);
1761 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1762 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1763 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1764 struct mlx5_flow_handle *dev_handle);
1765 const struct mlx5_flow_tunnel *
1766 mlx5_get_tof(const struct rte_flow_item *items,
1767 const struct rte_flow_action *actions,
1768 enum mlx5_tof_rule_type *rule_type);
1769 #endif /* RTE_PMD_MLX5_FLOW_H_ */