1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_alarm.h>
17 #include <mlx5_glue.h>
22 /* Private rte flow items. */
23 enum mlx5_rte_flow_item_type {
24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
25 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
38 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
39 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 #define MLX5_SHARED_ACTION_TYPE_OFFSET 30
45 MLX5_SHARED_ACTION_TYPE_RSS,
46 MLX5_SHARED_ACTION_TYPE_AGE,
49 /* Matches on selected register. */
50 struct mlx5_rte_flow_item_tag {
55 /* Modify selected register. */
56 struct mlx5_rte_flow_action_set_tag {
61 struct mlx5_flow_action_copy_mreg {
66 /* Matches on source queue. */
67 struct mlx5_rte_flow_item_tx_queue {
71 /* Feature name to allocate metadata register. */
72 enum mlx5_feature_name {
86 /* Default queue number. */
87 #define MLX5_RSSQ_DEFAULT_NUM 16
89 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
90 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
91 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
92 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
93 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
94 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
96 /* Pattern inner Layer bits. */
97 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
98 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
99 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
100 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
101 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
102 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
104 /* Pattern tunnel Layer bits. */
105 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
106 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
107 #define MLX5_FLOW_LAYER_GRE (1u << 14)
108 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
109 /* List of tunnel Layer bits continued below. */
111 /* General pattern items bits. */
112 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
113 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
114 #define MLX5_FLOW_ITEM_TAG (1u << 18)
115 #define MLX5_FLOW_ITEM_MARK (1u << 19)
117 /* Pattern MISC bits. */
118 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
119 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
120 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
122 /* Pattern tunnel Layer bits (continued). */
123 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
124 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
125 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
126 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
129 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
131 /* Pattern tunnel Layer bits (continued). */
132 #define MLX5_FLOW_LAYER_GTP (1u << 28)
134 /* Pattern eCPRI Layer bit. */
135 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
137 /* IPv6 Fragment Extension Header bit. */
138 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
139 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
141 /* Pattern tunnel Layer bits (continued). */
142 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
143 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
146 #define MLX5_FLOW_LAYER_OUTER_L3 \
147 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
148 #define MLX5_FLOW_LAYER_OUTER_L4 \
149 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
150 #define MLX5_FLOW_LAYER_OUTER \
151 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
152 MLX5_FLOW_LAYER_OUTER_L4)
155 #define MLX5_FLOW_LAYER_TUNNEL \
156 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
157 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
158 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
159 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
162 #define MLX5_FLOW_LAYER_INNER_L3 \
163 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
164 #define MLX5_FLOW_LAYER_INNER_L4 \
165 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
166 #define MLX5_FLOW_LAYER_INNER \
167 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
168 MLX5_FLOW_LAYER_INNER_L4)
171 #define MLX5_FLOW_LAYER_L2 \
172 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
173 #define MLX5_FLOW_LAYER_L3_IPV4 \
174 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
175 #define MLX5_FLOW_LAYER_L3_IPV6 \
176 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
177 #define MLX5_FLOW_LAYER_L3 \
178 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
179 #define MLX5_FLOW_LAYER_L4 \
180 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
183 #define MLX5_FLOW_ACTION_DROP (1u << 0)
184 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
185 #define MLX5_FLOW_ACTION_RSS (1u << 2)
186 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
187 #define MLX5_FLOW_ACTION_MARK (1u << 4)
188 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
189 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
190 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
191 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
192 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
193 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
194 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
195 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
196 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
197 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
198 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
199 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
200 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
201 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
202 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
203 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
204 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
205 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
206 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
207 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
208 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
209 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
210 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
211 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
212 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
213 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
214 #define MLX5_FLOW_ACTION_METER (1ull << 31)
215 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
216 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
217 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
218 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
219 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
220 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
221 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
223 #define MLX5_FLOW_FATE_ACTIONS \
224 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
225 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
226 MLX5_FLOW_ACTION_DEFAULT_MISS)
228 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
229 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
230 MLX5_FLOW_ACTION_JUMP)
233 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
234 MLX5_FLOW_ACTION_SET_IPV4_DST | \
235 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
236 MLX5_FLOW_ACTION_SET_IPV6_DST | \
237 MLX5_FLOW_ACTION_SET_TP_SRC | \
238 MLX5_FLOW_ACTION_SET_TP_DST | \
239 MLX5_FLOW_ACTION_SET_TTL | \
240 MLX5_FLOW_ACTION_DEC_TTL | \
241 MLX5_FLOW_ACTION_SET_MAC_SRC | \
242 MLX5_FLOW_ACTION_SET_MAC_DST | \
243 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
244 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
245 MLX5_FLOW_ACTION_INC_TCP_ACK | \
246 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
247 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
248 MLX5_FLOW_ACTION_SET_TAG | \
249 MLX5_FLOW_ACTION_MARK_EXT | \
250 MLX5_FLOW_ACTION_SET_META | \
251 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
252 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
254 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
255 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
257 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
260 #define IPPROTO_MPLS 137
263 /* UDP port number for MPLS */
264 #define MLX5_UDP_PORT_MPLS 6635
266 /* UDP port numbers for VxLAN. */
267 #define MLX5_UDP_PORT_VXLAN 4789
268 #define MLX5_UDP_PORT_VXLAN_GPE 4790
270 /* UDP port numbers for GENEVE. */
271 #define MLX5_UDP_PORT_GENEVE 6081
273 /* Priority reserved for default flows. */
274 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
277 * Number of sub priorities.
278 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
279 * matching on the NIC (firmware dependent) L4 most have the higher priority
280 * followed by L3 and ending with L2.
282 #define MLX5_PRIORITY_MAP_L2 2
283 #define MLX5_PRIORITY_MAP_L3 1
284 #define MLX5_PRIORITY_MAP_L4 0
285 #define MLX5_PRIORITY_MAP_MAX 3
287 /* Valid layer type for IPV4 RSS. */
288 #define MLX5_IPV4_LAYER_TYPES \
289 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
290 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
291 ETH_RSS_NONFRAG_IPV4_OTHER)
293 /* IBV hash source bits for IPV4. */
294 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
296 /* Valid layer type for IPV6 RSS. */
297 #define MLX5_IPV6_LAYER_TYPES \
298 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
299 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
300 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
302 /* IBV hash source bits for IPV6. */
303 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
305 /* IBV hash bits for L3 SRC. */
306 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
308 /* IBV hash bits for L3 DST. */
309 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
311 /* IBV hash bits for TCP. */
312 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
313 IBV_RX_HASH_DST_PORT_TCP)
315 /* IBV hash bits for UDP. */
316 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
317 IBV_RX_HASH_DST_PORT_UDP)
319 /* IBV hash bits for L4 SRC. */
320 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
321 IBV_RX_HASH_SRC_PORT_UDP)
323 /* IBV hash bits for L4 DST. */
324 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
325 IBV_RX_HASH_DST_PORT_UDP)
327 /* Geneve header first 16Bit */
328 #define MLX5_GENEVE_VER_MASK 0x3
329 #define MLX5_GENEVE_VER_SHIFT 14
330 #define MLX5_GENEVE_VER_VAL(a) \
331 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
332 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
333 #define MLX5_GENEVE_OPTLEN_SHIFT 8
334 #define MLX5_GENEVE_OPTLEN_VAL(a) \
335 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
336 #define MLX5_GENEVE_OAMF_MASK 0x1
337 #define MLX5_GENEVE_OAMF_SHIFT 7
338 #define MLX5_GENEVE_OAMF_VAL(a) \
339 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
340 #define MLX5_GENEVE_CRITO_MASK 0x1
341 #define MLX5_GENEVE_CRITO_SHIFT 6
342 #define MLX5_GENEVE_CRITO_VAL(a) \
343 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
344 #define MLX5_GENEVE_RSVD_MASK 0x3F
345 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
347 * The length of the Geneve options fields, expressed in four byte multiples,
348 * not including the eight byte fixed tunnel.
350 #define MLX5_GENEVE_OPT_LEN_0 14
351 #define MLX5_GENEVE_OPT_LEN_1 63
353 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
354 sizeof(struct rte_ipv4_hdr))
355 /* GTP extension header flag. */
356 #define MLX5_GTP_EXT_HEADER_FLAG 4
358 /* GTP extension header max PDU type value. */
359 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
361 /* GTP extension header PDU type shift. */
362 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
364 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
365 #define MLX5_IPV4_FRAG_OFFSET_MASK \
366 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
368 /* Specific item's fields can accept a range of values (using spec and last). */
369 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
370 #define MLX5_ITEM_RANGE_ACCEPTED true
372 /* Software header modify action numbers of a flow. */
373 #define MLX5_ACT_NUM_MDF_IPV4 1
374 #define MLX5_ACT_NUM_MDF_IPV6 4
375 #define MLX5_ACT_NUM_MDF_MAC 2
376 #define MLX5_ACT_NUM_MDF_VID 1
377 #define MLX5_ACT_NUM_MDF_PORT 2
378 #define MLX5_ACT_NUM_MDF_TTL 1
379 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
380 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
381 #define MLX5_ACT_NUM_MDF_TCPACK 1
382 #define MLX5_ACT_NUM_SET_REG 1
383 #define MLX5_ACT_NUM_SET_TAG 1
384 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
385 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
386 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
387 #define MLX5_ACT_NUM_SET_DSCP 1
389 enum mlx5_flow_drv_type {
392 MLX5_FLOW_TYPE_VERBS,
396 /* Fate action type. */
397 enum mlx5_flow_fate_type {
398 MLX5_FLOW_FATE_NONE, /* Egress flow. */
399 MLX5_FLOW_FATE_QUEUE,
401 MLX5_FLOW_FATE_PORT_ID,
403 MLX5_FLOW_FATE_DEFAULT_MISS,
404 MLX5_FLOW_FATE_SHARED_RSS,
408 /* Matcher PRM representation */
409 struct mlx5_flow_dv_match_params {
411 /**< Size of match value. Do NOT split size and key! */
412 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
413 /**< Matcher value. This value is used as the mask or as a key. */
416 /* Matcher structure. */
417 struct mlx5_flow_dv_matcher {
418 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
419 struct mlx5_flow_tbl_resource *tbl;
420 /**< Pointer to the table(group) the matcher associated with. */
421 void *matcher_object; /**< Pointer to DV matcher */
422 uint16_t crc; /**< CRC of key. */
423 uint16_t priority; /**< Priority of matcher. */
424 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
427 #define MLX5_ENCAP_MAX_LEN 132
429 /* Encap/decap resource structure. */
430 struct mlx5_flow_dv_encap_decap_resource {
431 struct mlx5_hlist_entry entry;
432 /* Pointer to next element. */
433 uint32_t refcnt; /**< Reference counter. */
435 /**< Encap/decap action object. */
436 uint8_t buf[MLX5_ENCAP_MAX_LEN];
438 uint8_t reformat_type;
440 uint64_t flags; /**< Flags for RDMA API. */
441 uint32_t idx; /**< Index for the index memory pool. */
444 /* Tag resource structure. */
445 struct mlx5_flow_dv_tag_resource {
446 struct mlx5_hlist_entry entry;
447 /**< hash list entry for tag resource, tag value as the key. */
449 /**< Tag action object. */
450 uint32_t refcnt; /**< Reference counter. */
451 uint32_t idx; /**< Index for the index memory pool. */
452 uint32_t tag_id; /**< Tag ID. */
456 * Number of modification commands.
457 * The maximal actions amount in FW is some constant, and it is 16 in the
458 * latest releases. In some old releases, it will be limited to 8.
459 * Since there is no interface to query the capacity, the maximal value should
460 * be used to allow PMD to create the flow. The validation will be done in the
461 * lower driver layer or FW. A failure will be returned if exceeds the maximal
462 * supported actions number on the root table.
463 * On non-root tables, there is no limitation, but 32 is enough right now.
465 #define MLX5_MAX_MODIFY_NUM 32
466 #define MLX5_ROOT_TBL_MODIFY_NUM 16
468 /* Modify resource structure */
469 struct mlx5_flow_dv_modify_hdr_resource {
470 struct mlx5_hlist_entry entry;
471 void *action; /**< Modify header action object. */
472 /* Key area for hash list matching: */
473 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
474 uint32_t actions_num; /**< Number of modification actions. */
475 uint64_t flags; /**< Flags for RDMA API. */
476 struct mlx5_modification_cmd actions[];
477 /**< Modification actions. */
480 /* Modify resource key of the hash organization. */
481 union mlx5_flow_modify_hdr_key {
483 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
484 uint32_t actions_num:5; /**< Number of modification actions. */
485 uint32_t group:19; /**< Flow group id. */
486 uint32_t cksum; /**< Actions check sum. */
488 uint64_t v64; /**< full 64bits value of key */
491 /* Jump action resource structure. */
492 struct mlx5_flow_dv_jump_tbl_resource {
493 void *action; /**< Pointer to the rdma core action. */
496 /* Port ID resource structure. */
497 struct mlx5_flow_dv_port_id_action_resource {
498 struct mlx5_cache_entry entry;
499 void *action; /**< Action object. */
500 uint32_t port_id; /**< Port ID value. */
501 uint32_t idx; /**< Indexed pool memory index. */
504 /* Push VLAN action resource structure */
505 struct mlx5_flow_dv_push_vlan_action_resource {
506 struct mlx5_cache_entry entry; /* Cache entry. */
507 void *action; /**< Action object. */
508 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
509 rte_be32_t vlan_tag; /**< VLAN tag value. */
510 uint32_t idx; /**< Indexed pool memory index. */
513 /* Metadata register copy table entry. */
514 struct mlx5_flow_mreg_copy_resource {
516 * Hash list entry for copy table.
517 * - Key is 32/64-bit MARK action ID.
518 * - MUST be the first entry.
520 struct mlx5_hlist_entry hlist_ent;
521 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
522 /* List entry for device flows. */
524 uint32_t rix_flow; /* Built flow for copy. */
528 /* Table tunnel parameter. */
529 struct mlx5_flow_tbl_tunnel_prm {
530 const struct mlx5_flow_tunnel *tunnel;
535 /* Table data structure of the hash organization. */
536 struct mlx5_flow_tbl_data_entry {
537 struct mlx5_hlist_entry entry;
538 /**< hash list entry, 64-bits key inside. */
539 struct mlx5_flow_tbl_resource tbl;
540 /**< flow table resource. */
541 struct mlx5_cache_list matchers;
542 /**< matchers' header associated with the flow table. */
543 struct mlx5_flow_dv_jump_tbl_resource jump;
544 /**< jump resource, at most one for each table created. */
545 uint32_t idx; /**< index for the indexed mempool. */
546 /**< tunnel offload */
547 const struct mlx5_flow_tunnel *tunnel;
550 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
551 uint32_t is_egress:1; /**< Egress table. */
552 uint32_t is_transfer:1; /**< Transfer table. */
553 uint32_t dummy:1; /**< DR table. */
554 uint32_t reserve:27; /**< Reserved to future using. */
555 uint32_t table_id; /**< Table ID. */
558 /* Sub rdma-core actions list. */
559 struct mlx5_flow_sub_actions_list {
560 uint32_t actions_num; /**< Number of sample actions. */
561 uint64_t action_flags;
562 void *dr_queue_action;
565 void *dr_port_id_action;
566 void *dr_encap_action;
567 void *dr_jump_action;
570 /* Sample sub-actions resource list. */
571 struct mlx5_flow_sub_actions_idx {
572 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
573 uint32_t rix_tag; /**< Index to the tag action. */
575 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
576 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
577 uint32_t rix_jump; /**< Index to the jump action resource. */
580 /* Sample action resource structure. */
581 struct mlx5_flow_dv_sample_resource {
582 struct mlx5_cache_entry entry; /**< Cache entry. */
584 void *verbs_action; /**< Verbs sample action object. */
585 void **sub_actions; /**< Sample sub-action array. */
587 struct rte_eth_dev *dev; /**< Device registers the action. */
588 uint32_t idx; /** Sample object index. */
589 uint8_t ft_type; /** Flow Table Type */
590 uint32_t ft_id; /** Flow Table Level */
591 uint32_t ratio; /** Sample Ratio */
592 uint64_t set_action; /** Restore reg_c0 value */
593 void *normal_path_tbl; /** Flow Table pointer */
594 void *default_miss; /** default_miss dr_action. */
595 struct mlx5_flow_sub_actions_idx sample_idx;
596 /**< Action index resources. */
597 struct mlx5_flow_sub_actions_list sample_act;
598 /**< Action resources. */
601 #define MLX5_MAX_DEST_NUM 2
603 /* Destination array action resource structure. */
604 struct mlx5_flow_dv_dest_array_resource {
605 struct mlx5_cache_entry entry; /**< Cache entry. */
606 uint32_t idx; /** Destination array action object index. */
607 uint8_t ft_type; /** Flow Table Type */
608 uint8_t num_of_dest; /**< Number of destination actions. */
609 struct rte_eth_dev *dev; /**< Device registers the action. */
610 void *action; /**< Pointer to the rdma core action. */
611 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
612 /**< Action index resources. */
613 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
614 /**< Action resources. */
617 /* PMD flow priority for tunnel */
618 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
619 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
622 /** Device flow handle structure for DV mode only. */
623 struct mlx5_flow_handle_dv {
625 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
626 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
627 /**< Pointer to modify header resource in cache. */
628 uint32_t rix_encap_decap;
629 /**< Index to encap/decap resource in cache. */
630 uint32_t rix_push_vlan;
631 /**< Index to push VLAN action resource in cache. */
633 /**< Index to the tag action. */
635 /**< Index to sample action resource in cache. */
636 uint32_t rix_dest_array;
637 /**< Index to destination array resource in cache. */
640 /** Device flow handle structure: used both for creating & destroying. */
641 struct mlx5_flow_handle {
642 SILIST_ENTRY(uint32_t)next;
643 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
644 /**< Index to next device flow handle. */
646 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
647 void *drv_flow; /**< pointer to driver flow object. */
648 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
649 uint32_t mark:1; /**< Metadate rxq mark flag. */
650 uint32_t fate_action:3; /**< Fate action type. */
652 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
653 uint32_t rix_jump; /**< Index to the jump action resource. */
654 uint32_t rix_port_id_action;
655 /**< Index to port ID action resource. */
657 /**< Generic value indicates the fate action. */
658 uint32_t rix_default_fate;
659 /**< Indicates default miss fate action. */
661 /**< Indicates shared RSS fate action. */
663 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
664 struct mlx5_flow_handle_dv dvh;
669 * Size for Verbs device flow handle structure only. Do not use the DV only
670 * structure in Verbs. No DV flows attributes will be accessed.
671 * Macro offsetof() could also be used here.
673 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
674 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
675 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
677 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
681 * Max number of actions per DV flow.
682 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
683 * in rdma-core file providers/mlx5/verbs.c.
685 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
687 /** Device flow structure only for DV flow creation. */
688 struct mlx5_flow_dv_workspace {
689 uint32_t group; /**< The group index. */
690 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
691 int actions_n; /**< number of actions. */
692 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
693 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
694 /**< Pointer to encap/decap resource in cache. */
695 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
696 /**< Pointer to push VLAN action resource in cache. */
697 struct mlx5_flow_dv_tag_resource *tag_resource;
698 /**< pointer to the tag action. */
699 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
700 /**< Pointer to port ID action resource. */
701 struct mlx5_flow_dv_jump_tbl_resource *jump;
702 /**< Pointer to the jump action resource. */
703 struct mlx5_flow_dv_match_params value;
704 /**< Holds the value that the packet is compared to. */
705 struct mlx5_flow_dv_sample_resource *sample_res;
706 /**< Pointer to the sample action resource. */
707 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
708 /**< Pointer to the destination array resource. */
711 #ifdef HAVE_INFINIBAND_VERBS_H
713 * Maximal Verbs flow specifications & actions size.
714 * Some elements are mutually exclusive, but enough space should be allocated.
715 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
716 * 2. One tunnel header (exception: GRE + MPLS),
717 * SPEC length: GRE == tunnel.
718 * Actions: 1. 1 Mark OR Flag.
719 * 2. 1 Drop (if any).
720 * 3. No limitation for counters, but it makes no sense to support too
721 * many counters in a single device flow.
723 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
724 #define MLX5_VERBS_MAX_SPEC_SIZE \
726 (2 * (sizeof(struct ibv_flow_spec_eth) + \
727 sizeof(struct ibv_flow_spec_ipv6) + \
728 sizeof(struct ibv_flow_spec_tcp_udp)) + \
729 sizeof(struct ibv_flow_spec_gre) + \
730 sizeof(struct ibv_flow_spec_mpls)) \
733 #define MLX5_VERBS_MAX_SPEC_SIZE \
735 (2 * (sizeof(struct ibv_flow_spec_eth) + \
736 sizeof(struct ibv_flow_spec_ipv6) + \
737 sizeof(struct ibv_flow_spec_tcp_udp)) + \
738 sizeof(struct ibv_flow_spec_tunnel)) \
742 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
743 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
744 #define MLX5_VERBS_MAX_ACT_SIZE \
746 sizeof(struct ibv_flow_spec_action_tag) + \
747 sizeof(struct ibv_flow_spec_action_drop) + \
748 sizeof(struct ibv_flow_spec_counter_action) * 4 \
751 #define MLX5_VERBS_MAX_ACT_SIZE \
753 sizeof(struct ibv_flow_spec_action_tag) + \
754 sizeof(struct ibv_flow_spec_action_drop) \
758 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
759 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
761 /** Device flow structure only for Verbs flow creation. */
762 struct mlx5_flow_verbs_workspace {
763 unsigned int size; /**< Size of the attribute. */
764 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
765 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
766 /**< Specifications & actions buffer of verbs flow. */
768 #endif /* HAVE_INFINIBAND_VERBS_H */
770 /** Maximal number of device sub-flows supported. */
771 #define MLX5_NUM_MAX_DEV_FLOWS 32
773 /** Device flow structure. */
776 struct rte_flow *flow; /**< Pointer to the main flow. */
777 uint32_t flow_idx; /**< The memory pool index to the main flow. */
778 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
780 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
781 bool external; /**< true if the flow is created external to PMD. */
782 uint8_t ingress:1; /**< 1 if the flow is ingress. */
783 uint8_t skip_scale:1;
784 /**< 1 if skip the scale the table with factor. */
786 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
787 struct mlx5_flow_dv_workspace dv;
789 #ifdef HAVE_INFINIBAND_VERBS_H
790 struct mlx5_flow_verbs_workspace verbs;
793 struct mlx5_flow_handle *handle;
794 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
795 const struct mlx5_flow_tunnel *tunnel;
798 /* Flow meter state. */
799 #define MLX5_FLOW_METER_DISABLE 0
800 #define MLX5_FLOW_METER_ENABLE 1
802 #define MLX5_MAN_WIDTH 8
803 /* Modify this value if enum rte_mtr_color changes. */
804 #define RTE_MTR_DROPPED RTE_COLORS
806 /* Meter policer statistics */
807 struct mlx5_flow_policer_stats {
808 uint32_t cnt[RTE_COLORS + 1];
809 /**< Color counter, extra for drop. */
811 /**< Statistics mask for the colors. */
814 /* Meter table structure. */
815 struct mlx5_meter_domain_info {
816 struct mlx5_flow_tbl_resource *tbl;
818 struct mlx5_flow_tbl_resource *sfx_tbl;
819 /**< Meter suffix table. */
821 /**< Meter color not match default criteria. */
823 /**< Meter color match criteria. */
825 /**< Meter match action. */
826 void *policer_rules[RTE_MTR_DROPPED + 1];
827 /**< Meter policer for the match. */
830 /* Meter table set for TX RX FDB. */
831 struct mlx5_meter_domains_infos {
833 /**< Table user count. */
834 struct mlx5_meter_domain_info egress;
835 /**< TX meter table. */
836 struct mlx5_meter_domain_info ingress;
837 /**< RX meter table. */
838 struct mlx5_meter_domain_info transfer;
839 /**< FDB meter table. */
841 /**< Drop action as not matched. */
842 void *count_actns[RTE_MTR_DROPPED + 1];
843 /**< Counters for match and unmatched statistics. */
844 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
845 /**< Flow meter parameter. */
847 /**< Flow meter parameter size. */
849 /**< Flow meter action. */
852 /* Meter parameter structure. */
853 struct mlx5_flow_meter {
854 TAILQ_ENTRY(mlx5_flow_meter) next;
855 /**< Pointer to the next flow meter structure. */
856 uint32_t idx; /* Index to meter object. */
859 struct mlx5_flow_meter_profile *profile;
860 /**< Meter profile parameters. */
862 rte_spinlock_t sl; /**< Meter action spinlock. */
864 /** Policer actions (per meter output color). */
865 enum rte_mtr_policer_action action[RTE_COLORS];
867 /** Set of stats counters to be enabled.
868 * @see enum rte_mtr_stats_type
872 /**< Rule applies to ingress traffic. */
875 /**< Rule applies to egress traffic. */
878 * Instead of simply matching the properties of traffic as it would
879 * appear on a given DPDK port ID, enabling this attribute transfers
880 * a flow rule to the lowest possible level of any device endpoints
881 * found in the pattern.
883 * When supported, this effectively enables an application to
884 * re-route traffic not necessarily intended for it (e.g. coming
885 * from or addressed to different physical ports, VFs or
886 * applications) at the device level.
888 * It complements the behavior of some pattern items such as
889 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
891 * When transferring flow rules, ingress and egress attributes keep
892 * their original meaning, as if processing traffic emitted or
893 * received by the application.
896 struct mlx5_meter_domains_infos *mfts;
897 /**< Flow table created for this meter. */
898 struct mlx5_flow_policer_stats policer_stats;
899 /**< Meter policer statistics. */
902 uint32_t active_state:1;
905 /**< Meter shared or not. */
908 /* RFC2697 parameter structure. */
909 struct mlx5_flow_meter_srtcm_rfc2697_prm {
910 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
911 uint32_t cbs_exponent:5;
912 uint32_t cbs_mantissa:8;
913 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
914 uint32_t cir_exponent:5;
915 uint32_t cir_mantissa:8;
916 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
917 uint32_t ebs_exponent:5;
918 uint32_t ebs_mantissa:8;
921 /* Flow meter profile structure. */
922 struct mlx5_flow_meter_profile {
923 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
924 /**< Pointer to the next flow meter structure. */
925 uint32_t meter_profile_id; /**< Profile id. */
926 struct rte_mtr_meter_profile profile; /**< Profile detail. */
928 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
929 /**< srtcm_rfc2697 struct. */
931 uint32_t ref_cnt; /**< Use count. */
934 #define MLX5_MAX_TUNNELS 256
935 #define MLX5_TNL_MISS_RULE_PRIORITY 3
936 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
939 * When tunnel offload is active, all JUMP group ids are converted
940 * using the same method. That conversion is applied both to tunnel and
941 * regular rule types.
942 * Group ids used in tunnel rules are relative to it's tunnel (!).
943 * Application can create number of steer rules, using the same
944 * tunnel, with different group id in each rule.
945 * Each tunnel stores its groups internally in PMD tunnel object.
946 * Groups used in regular rules do not belong to any tunnel and are stored
950 struct mlx5_flow_tunnel {
951 LIST_ENTRY(mlx5_flow_tunnel) chain;
952 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
953 uint32_t tunnel_id; /** unique tunnel ID */
955 struct rte_flow_action action;
956 struct rte_flow_item item;
957 struct mlx5_hlist *groups; /** tunnel groups */
960 /** PMD tunnel related context */
961 struct mlx5_flow_tunnel_hub {
963 * Access to the list MUST be MT protected
965 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
966 /* protect access to the tunnels list */
968 struct mlx5_hlist *groups; /** non tunnel groups */
971 /* convert jump group to flow table ID in tunnel rules */
972 struct tunnel_tbl_entry {
973 struct mlx5_hlist_entry hash;
979 static inline uint32_t
980 tunnel_id_to_flow_tbl(uint32_t id)
982 return id | (1u << 16);
985 static inline uint32_t
986 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
988 return flow_tbl & ~(1u << 16);
991 union tunnel_tbl_key {
999 static inline struct mlx5_flow_tunnel_hub *
1000 mlx5_tunnel_hub(struct rte_eth_dev *dev)
1002 struct mlx5_priv *priv = dev->data->dev_private;
1003 return priv->sh->tunnel_hub;
1007 is_tunnel_offload_active(struct rte_eth_dev *dev)
1009 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1010 struct mlx5_priv *priv = dev->data->dev_private;
1011 return !!priv->config.dv_miss_info;
1019 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
1020 __rte_unused const struct rte_flow_attr *attr,
1021 __rte_unused const struct rte_flow_item items[],
1022 __rte_unused const struct rte_flow_action actions[])
1024 return (items[0].type == (typeof(items[0].type))
1025 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1029 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1030 __rte_unused const struct rte_flow_attr *attr,
1031 __rte_unused const struct rte_flow_item items[],
1032 __rte_unused const struct rte_flow_action actions[])
1034 return (actions[0].type == (typeof(actions[0].type))
1035 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1038 static inline const struct mlx5_flow_tunnel *
1039 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1041 return actions[0].conf;
1044 static inline const struct mlx5_flow_tunnel *
1045 flow_items_to_tunnel(const struct rte_flow_item items[])
1047 return items[0].spec;
1050 /* Flow structure. */
1052 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1053 uint32_t dev_handles;
1054 /**< Device flow handles that are part of the flow. */
1055 uint32_t drv_type:2; /**< Driver type. */
1057 uint32_t meter:16; /**< Holds flow meter id. */
1058 uint32_t rix_mreg_copy;
1059 /**< Index to metadata register copy table resource. */
1060 uint32_t counter; /**< Holds flow counter. */
1061 uint32_t tunnel_id; /**< Tunnel id */
1062 uint32_t age; /**< Holds ASO age bit index. */
1063 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1067 * Define list of valid combinations of RX Hash fields
1068 * (see enum ibv_rx_hash_fields).
1070 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1071 #define MLX5_RSS_HASH_IPV4_TCP \
1072 (MLX5_RSS_HASH_IPV4 | \
1073 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1074 #define MLX5_RSS_HASH_IPV4_UDP \
1075 (MLX5_RSS_HASH_IPV4 | \
1076 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1077 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1078 #define MLX5_RSS_HASH_IPV6_TCP \
1079 (MLX5_RSS_HASH_IPV6 | \
1080 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1081 #define MLX5_RSS_HASH_IPV6_UDP \
1082 (MLX5_RSS_HASH_IPV6 | \
1083 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1084 #define MLX5_RSS_HASH_NONE 0ULL
1086 /* array of valid combinations of RX Hash fields for RSS */
1087 static const uint64_t mlx5_rss_hash_fields[] = {
1089 MLX5_RSS_HASH_IPV4_TCP,
1090 MLX5_RSS_HASH_IPV4_UDP,
1092 MLX5_RSS_HASH_IPV6_TCP,
1093 MLX5_RSS_HASH_IPV6_UDP,
1097 /* Shared RSS action structure */
1098 struct mlx5_shared_action_rss {
1099 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1100 uint32_t refcnt; /**< Atomically accessed refcnt. */
1101 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1102 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1103 struct mlx5_ind_table_obj *ind_tbl;
1104 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1105 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1106 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1107 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
1108 /**< Hash RX queue indexes for tunneled RSS */
1109 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1112 struct rte_flow_shared_action {
1116 /* Thread specific flow workspace intermediate data. */
1117 struct mlx5_flow_workspace {
1118 /* If creating another flow in same thread, push new as stack. */
1119 struct mlx5_flow_workspace *prev;
1120 struct mlx5_flow_workspace *next;
1121 uint32_t inuse; /* can't create new flow with current. */
1122 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1123 struct mlx5_flow_rss_desc rss_desc;
1124 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1125 uint32_t flow_idx; /* Intermediate device flow index. */
1128 struct mlx5_flow_split_info {
1130 /**< True if flow is created by request external to PMD. */
1131 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1132 uint32_t flow_idx; /**< This memory pool index to the flow. */
1133 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1134 uint64_t prefix_layers; /**< Prefix subflow layers. */
1137 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1138 const struct rte_flow_attr *attr,
1139 const struct rte_flow_item items[],
1140 const struct rte_flow_action actions[],
1143 struct rte_flow_error *error);
1144 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1145 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1146 const struct rte_flow_item items[],
1147 const struct rte_flow_action actions[], struct rte_flow_error *error);
1148 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1149 struct mlx5_flow *dev_flow,
1150 const struct rte_flow_attr *attr,
1151 const struct rte_flow_item items[],
1152 const struct rte_flow_action actions[],
1153 struct rte_flow_error *error);
1154 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1155 struct rte_flow_error *error);
1156 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1157 struct rte_flow *flow);
1158 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1159 struct rte_flow *flow);
1160 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1161 struct rte_flow *flow,
1162 const struct rte_flow_action *actions,
1164 struct rte_flow_error *error);
1165 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1166 (struct rte_eth_dev *dev,
1167 const struct mlx5_flow_meter *fm);
1168 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1169 struct mlx5_meter_domains_infos *tbls);
1170 typedef int (*mlx5_flow_create_policer_rules_t)
1171 (struct rte_eth_dev *dev,
1172 struct mlx5_flow_meter *fm,
1173 const struct rte_flow_attr *attr);
1174 typedef int (*mlx5_flow_destroy_policer_rules_t)
1175 (struct rte_eth_dev *dev,
1176 const struct mlx5_flow_meter *fm,
1177 const struct rte_flow_attr *attr);
1178 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1179 (struct rte_eth_dev *dev);
1180 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1182 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1184 bool clear, uint64_t *pkts,
1186 typedef int (*mlx5_flow_get_aged_flows_t)
1187 (struct rte_eth_dev *dev,
1189 uint32_t nb_contexts,
1190 struct rte_flow_error *error);
1191 typedef int (*mlx5_flow_action_validate_t)
1192 (struct rte_eth_dev *dev,
1193 const struct rte_flow_shared_action_conf *conf,
1194 const struct rte_flow_action *action,
1195 struct rte_flow_error *error);
1196 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1197 (struct rte_eth_dev *dev,
1198 const struct rte_flow_shared_action_conf *conf,
1199 const struct rte_flow_action *action,
1200 struct rte_flow_error *error);
1201 typedef int (*mlx5_flow_action_destroy_t)
1202 (struct rte_eth_dev *dev,
1203 struct rte_flow_shared_action *action,
1204 struct rte_flow_error *error);
1205 typedef int (*mlx5_flow_action_update_t)
1206 (struct rte_eth_dev *dev,
1207 struct rte_flow_shared_action *action,
1208 const void *action_conf,
1209 struct rte_flow_error *error);
1210 typedef int (*mlx5_flow_action_query_t)
1211 (struct rte_eth_dev *dev,
1212 const struct rte_flow_shared_action *action,
1214 struct rte_flow_error *error);
1215 typedef int (*mlx5_flow_sync_domain_t)
1216 (struct rte_eth_dev *dev,
1220 struct mlx5_flow_driver_ops {
1221 mlx5_flow_validate_t validate;
1222 mlx5_flow_prepare_t prepare;
1223 mlx5_flow_translate_t translate;
1224 mlx5_flow_apply_t apply;
1225 mlx5_flow_remove_t remove;
1226 mlx5_flow_destroy_t destroy;
1227 mlx5_flow_query_t query;
1228 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1229 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1230 mlx5_flow_create_policer_rules_t create_policer_rules;
1231 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1232 mlx5_flow_counter_alloc_t counter_alloc;
1233 mlx5_flow_counter_free_t counter_free;
1234 mlx5_flow_counter_query_t counter_query;
1235 mlx5_flow_get_aged_flows_t get_aged_flows;
1236 mlx5_flow_action_validate_t action_validate;
1237 mlx5_flow_action_create_t action_create;
1238 mlx5_flow_action_destroy_t action_destroy;
1239 mlx5_flow_action_update_t action_update;
1240 mlx5_flow_action_query_t action_query;
1241 mlx5_flow_sync_domain_t sync_domain;
1246 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1248 struct flow_grp_info {
1249 uint64_t external:1;
1250 uint64_t transfer:1;
1251 uint64_t fdb_def_rule:1;
1252 /* force standard group translation */
1253 uint64_t std_tbl_fix:1;
1254 uint64_t skip_scale:1;
1258 tunnel_use_standard_attr_group_translate
1259 (struct rte_eth_dev *dev,
1260 const struct mlx5_flow_tunnel *tunnel,
1261 const struct rte_flow_attr *attr,
1262 const struct rte_flow_item items[],
1263 const struct rte_flow_action actions[])
1267 if (!is_tunnel_offload_active(dev))
1268 /* no tunnel offload API */
1272 * OvS will use jump to group 0 in tunnel steer rule.
1273 * If tunnel steer rule starts from group 0 (attr.group == 0)
1274 * that 0 group must be translated with standard method.
1275 * attr.group == 0 in tunnel match rule translated with tunnel
1278 verdict = !attr->group &&
1279 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1282 * non-tunnel group translation uses standard method for
1283 * root group only: attr.group == 0
1285 verdict = !attr->group;
1291 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1292 const struct mlx5_flow_tunnel *tunnel,
1293 uint32_t group, uint32_t *table,
1294 const struct flow_grp_info *flags,
1295 struct rte_flow_error *error);
1296 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1297 int tunnel, uint64_t layer_types,
1298 uint64_t hash_fields);
1299 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1300 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1301 uint32_t subpriority);
1302 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1303 enum mlx5_feature_name feature,
1305 struct rte_flow_error *error);
1306 const struct rte_flow_action *mlx5_flow_find_action
1307 (const struct rte_flow_action *actions,
1308 enum rte_flow_action_type action);
1309 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1310 const struct rte_flow_action *action,
1311 struct rte_flow_error *error);
1312 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1313 const struct rte_flow_attr *attr,
1314 struct rte_flow_error *error);
1315 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1316 const struct rte_flow_attr *attr,
1317 struct rte_flow_error *error);
1318 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1319 const struct rte_flow_attr *attr,
1320 struct rte_flow_error *error);
1321 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1322 uint64_t action_flags,
1323 const struct rte_flow_attr *attr,
1324 struct rte_flow_error *error);
1325 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1326 uint64_t action_flags,
1327 struct rte_eth_dev *dev,
1328 const struct rte_flow_attr *attr,
1329 struct rte_flow_error *error);
1330 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1331 uint64_t action_flags,
1332 struct rte_eth_dev *dev,
1333 const struct rte_flow_attr *attr,
1334 uint64_t item_flags,
1335 struct rte_flow_error *error);
1336 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1337 const struct rte_flow_attr *attr,
1338 struct rte_flow_error *error);
1339 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1340 const struct rte_flow_attr *attributes,
1341 struct rte_flow_error *error);
1342 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1343 const uint8_t *mask,
1344 const uint8_t *nic_mask,
1346 bool range_accepted,
1347 struct rte_flow_error *error);
1348 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1349 uint64_t item_flags, bool ext_vlan_sup,
1350 struct rte_flow_error *error);
1351 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1352 uint64_t item_flags,
1353 uint8_t target_protocol,
1354 struct rte_flow_error *error);
1355 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1356 uint64_t item_flags,
1357 const struct rte_flow_item *gre_item,
1358 struct rte_flow_error *error);
1359 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1360 uint64_t item_flags,
1362 uint16_t ether_type,
1363 const struct rte_flow_item_ipv4 *acc_mask,
1364 bool range_accepted,
1365 struct rte_flow_error *error);
1366 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1367 uint64_t item_flags,
1369 uint16_t ether_type,
1370 const struct rte_flow_item_ipv6 *acc_mask,
1371 struct rte_flow_error *error);
1372 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1373 const struct rte_flow_item *item,
1374 uint64_t item_flags,
1375 uint64_t prev_layer,
1376 struct rte_flow_error *error);
1377 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1378 uint64_t item_flags,
1379 uint8_t target_protocol,
1380 const struct rte_flow_item_tcp *flow_mask,
1381 struct rte_flow_error *error);
1382 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1383 uint64_t item_flags,
1384 uint8_t target_protocol,
1385 struct rte_flow_error *error);
1386 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1387 uint64_t item_flags,
1388 struct rte_eth_dev *dev,
1389 struct rte_flow_error *error);
1390 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1391 uint64_t item_flags,
1392 struct rte_flow_error *error);
1393 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1394 uint64_t item_flags,
1395 struct rte_eth_dev *dev,
1396 struct rte_flow_error *error);
1397 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1398 uint64_t item_flags,
1399 uint8_t target_protocol,
1400 struct rte_flow_error *error);
1401 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1402 uint64_t item_flags,
1403 uint8_t target_protocol,
1404 struct rte_flow_error *error);
1405 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1406 uint64_t item_flags,
1407 uint8_t target_protocol,
1408 struct rte_flow_error *error);
1409 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1410 uint64_t item_flags,
1411 struct rte_eth_dev *dev,
1412 struct rte_flow_error *error);
1413 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1415 const struct rte_flow_item *geneve_item,
1416 struct rte_eth_dev *dev,
1417 struct rte_flow_error *error);
1418 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1419 uint64_t item_flags,
1421 uint16_t ether_type,
1422 const struct rte_flow_item_ecpri *acc_mask,
1423 struct rte_flow_error *error);
1424 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1425 (struct rte_eth_dev *dev,
1426 const struct mlx5_flow_meter *fm);
1427 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1428 struct mlx5_meter_domains_infos *tbl);
1429 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1430 struct mlx5_flow_meter *fm,
1431 const struct rte_flow_attr *attr);
1432 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1433 struct mlx5_flow_meter *fm,
1434 const struct rte_flow_attr *attr);
1435 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1436 struct rte_mtr_error *error);
1437 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1438 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1439 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1440 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1442 /* Hash list callbacks for flow tables: */
1443 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1444 uint64_t key, void *entry_ctx);
1445 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1446 struct mlx5_hlist_entry *entry, uint64_t key,
1448 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1449 struct mlx5_hlist_entry *entry);
1450 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1451 uint32_t table_id, uint8_t egress, uint8_t transfer,
1452 bool external, const struct mlx5_flow_tunnel *tunnel,
1453 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error);
1455 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1456 uint64_t key, void *cb_ctx);
1457 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1458 struct mlx5_hlist_entry *entry, uint64_t key,
1460 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1461 struct mlx5_hlist_entry *entry);
1463 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1464 struct mlx5_hlist_entry *entry,
1465 uint64_t key, void *cb_ctx);
1466 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1467 uint64_t key, void *ctx);
1468 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1469 struct mlx5_hlist_entry *entry);
1471 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1472 uint64_t key, void *ctx);
1473 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1474 struct mlx5_hlist_entry *entry, uint64_t key,
1476 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1477 struct mlx5_hlist_entry *entry);
1479 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1480 struct mlx5_hlist_entry *entry,
1481 uint64_t key, void *cb_ctx);
1482 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1483 uint64_t key, void *cb_ctx);
1484 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1485 struct mlx5_hlist_entry *entry);
1487 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1488 struct mlx5_cache_entry *entry, void *ctx);
1489 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1490 struct mlx5_cache_entry *entry, void *ctx);
1491 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1492 struct mlx5_cache_entry *entry);
1494 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1495 struct mlx5_cache_entry *entry, void *cb_ctx);
1496 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1497 struct mlx5_cache_entry *entry, void *cb_ctx);
1498 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1499 struct mlx5_cache_entry *entry);
1501 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1502 struct mlx5_cache_entry *entry, void *cb_ctx);
1503 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1504 (struct mlx5_cache_list *list,
1505 struct mlx5_cache_entry *entry, void *cb_ctx);
1506 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1507 struct mlx5_cache_entry *entry);
1509 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1510 struct mlx5_cache_entry *entry, void *cb_ctx);
1511 struct mlx5_cache_entry *flow_dv_sample_create_cb
1512 (struct mlx5_cache_list *list,
1513 struct mlx5_cache_entry *entry, void *cb_ctx);
1514 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1515 struct mlx5_cache_entry *entry);
1517 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1518 struct mlx5_cache_entry *entry, void *cb_ctx);
1519 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1520 (struct mlx5_cache_list *list,
1521 struct mlx5_cache_entry *entry, void *cb_ctx);
1522 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1523 struct mlx5_cache_entry *entry);
1524 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1526 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1527 const struct rte_flow_item *item,
1528 struct rte_flow_error *error);
1530 void flow_release_workspace(void *data);
1531 int mlx5_flow_os_init_workspace_once(void);
1532 void *mlx5_flow_os_get_specific_workspace(void);
1533 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1534 void mlx5_flow_os_release_workspace(void);
1537 #endif /* RTE_PMD_MLX5_FLOW_H_ */