1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
31 /* Private rte flow items. */
32 enum mlx5_rte_flow_item_type {
33 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
35 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
38 /* Private (internal) rte flow actions. */
39 enum mlx5_rte_flow_action_type {
40 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
41 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
42 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
43 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
46 /* Matches on selected register. */
47 struct mlx5_rte_flow_item_tag {
52 /* Modify selected register. */
53 struct mlx5_rte_flow_action_set_tag {
58 struct mlx5_flow_action_copy_mreg {
63 /* Matches on source queue. */
64 struct mlx5_rte_flow_item_tx_queue {
68 /* Feature name to allocate metadata register. */
69 enum mlx5_feature_name {
82 /* Pattern outer Layer bits. */
83 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
84 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
85 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
86 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
87 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
88 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
90 /* Pattern inner Layer bits. */
91 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
92 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
93 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
94 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
95 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
96 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
98 /* Pattern tunnel Layer bits. */
99 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
100 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
101 #define MLX5_FLOW_LAYER_GRE (1u << 14)
102 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
103 /* List of tunnel Layer bits continued below. */
105 /* General pattern items bits. */
106 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
107 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
108 #define MLX5_FLOW_ITEM_TAG (1u << 18)
109 #define MLX5_FLOW_ITEM_MARK (1u << 19)
111 /* Pattern MISC bits. */
112 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
113 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
114 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
116 /* Pattern tunnel Layer bits (continued). */
117 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
118 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
119 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
120 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
123 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
126 #define MLX5_FLOW_LAYER_OUTER_L3 \
127 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
128 #define MLX5_FLOW_LAYER_OUTER_L4 \
129 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
130 #define MLX5_FLOW_LAYER_OUTER \
131 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
132 MLX5_FLOW_LAYER_OUTER_L4)
134 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
135 #define MLX5_FLOW_LAYER_IPV4_LRO \
136 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
137 #define MLX5_FLOW_LAYER_IPV6_LRO \
138 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
141 #define MLX5_FLOW_LAYER_TUNNEL \
142 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
143 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
144 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
145 MLX5_FLOW_LAYER_GENEVE)
148 #define MLX5_FLOW_LAYER_INNER_L3 \
149 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
150 #define MLX5_FLOW_LAYER_INNER_L4 \
151 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
152 #define MLX5_FLOW_LAYER_INNER \
153 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
154 MLX5_FLOW_LAYER_INNER_L4)
157 #define MLX5_FLOW_LAYER_L2 \
158 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
159 #define MLX5_FLOW_LAYER_L3_IPV4 \
160 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
161 #define MLX5_FLOW_LAYER_L3_IPV6 \
162 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
163 #define MLX5_FLOW_LAYER_L3 \
164 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
165 #define MLX5_FLOW_LAYER_L4 \
166 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
169 #define MLX5_FLOW_ACTION_DROP (1u << 0)
170 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
171 #define MLX5_FLOW_ACTION_RSS (1u << 2)
172 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
173 #define MLX5_FLOW_ACTION_MARK (1u << 4)
174 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
175 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
176 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
177 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
178 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
179 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
180 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
181 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
182 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
183 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
184 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
185 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
186 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
187 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
188 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
189 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
190 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
191 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
192 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
193 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
194 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
195 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
196 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
197 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
198 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
199 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
200 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
201 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
202 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33)
203 #define MLX5_FLOW_ACTION_SET_META (1ull << 34)
204 #define MLX5_FLOW_ACTION_METER (1ull << 35)
206 #define MLX5_FLOW_FATE_ACTIONS \
207 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
208 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
210 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
211 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
212 MLX5_FLOW_ACTION_JUMP)
214 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
215 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
216 MLX5_FLOW_ACTION_RAW_ENCAP | \
217 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
219 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
220 MLX5_FLOW_ACTION_NVGRE_DECAP | \
221 MLX5_FLOW_ACTION_RAW_DECAP | \
222 MLX5_FLOW_ACTION_OF_POP_VLAN)
224 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
225 MLX5_FLOW_ACTION_SET_IPV4_DST | \
226 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
227 MLX5_FLOW_ACTION_SET_IPV6_DST | \
228 MLX5_FLOW_ACTION_SET_TP_SRC | \
229 MLX5_FLOW_ACTION_SET_TP_DST | \
230 MLX5_FLOW_ACTION_SET_TTL | \
231 MLX5_FLOW_ACTION_DEC_TTL | \
232 MLX5_FLOW_ACTION_SET_MAC_SRC | \
233 MLX5_FLOW_ACTION_SET_MAC_DST | \
234 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
235 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
236 MLX5_FLOW_ACTION_INC_TCP_ACK | \
237 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
238 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
239 MLX5_FLOW_ACTION_SET_TAG | \
240 MLX5_FLOW_ACTION_MARK_EXT | \
241 MLX5_FLOW_ACTION_SET_META)
243 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
244 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
246 #define IPPROTO_MPLS 137
249 /* UDP port number for MPLS */
250 #define MLX5_UDP_PORT_MPLS 6635
252 /* UDP port numbers for VxLAN. */
253 #define MLX5_UDP_PORT_VXLAN 4789
254 #define MLX5_UDP_PORT_VXLAN_GPE 4790
256 /* UDP port numbers for GENEVE. */
257 #define MLX5_UDP_PORT_GENEVE 6081
259 /* Priority reserved for default flows. */
260 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
263 * Number of sub priorities.
264 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
265 * matching on the NIC (firmware dependent) L4 most have the higher priority
266 * followed by L3 and ending with L2.
268 #define MLX5_PRIORITY_MAP_L2 2
269 #define MLX5_PRIORITY_MAP_L3 1
270 #define MLX5_PRIORITY_MAP_L4 0
271 #define MLX5_PRIORITY_MAP_MAX 3
273 /* Valid layer type for IPV4 RSS. */
274 #define MLX5_IPV4_LAYER_TYPES \
275 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
276 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
277 ETH_RSS_NONFRAG_IPV4_OTHER)
279 /* IBV hash source bits for IPV4. */
280 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
282 /* Valid layer type for IPV6 RSS. */
283 #define MLX5_IPV6_LAYER_TYPES \
284 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
285 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
286 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
288 /* IBV hash source bits for IPV6. */
289 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
292 /* Geneve header first 16Bit */
293 #define MLX5_GENEVE_VER_MASK 0x3
294 #define MLX5_GENEVE_VER_SHIFT 14
295 #define MLX5_GENEVE_VER_VAL(a) \
296 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
297 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
298 #define MLX5_GENEVE_OPTLEN_SHIFT 7
299 #define MLX5_GENEVE_OPTLEN_VAL(a) \
300 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
301 #define MLX5_GENEVE_OAMF_MASK 0x1
302 #define MLX5_GENEVE_OAMF_SHIFT 7
303 #define MLX5_GENEVE_OAMF_VAL(a) \
304 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
305 #define MLX5_GENEVE_CRITO_MASK 0x1
306 #define MLX5_GENEVE_CRITO_SHIFT 6
307 #define MLX5_GENEVE_CRITO_VAL(a) \
308 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
309 #define MLX5_GENEVE_RSVD_MASK 0x3F
310 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
312 * The length of the Geneve options fields, expressed in four byte multiples,
313 * not including the eight byte fixed tunnel.
315 #define MLX5_GENEVE_OPT_LEN_0 14
316 #define MLX5_GENEVE_OPT_LEN_1 63
318 enum mlx5_flow_drv_type {
321 MLX5_FLOW_TYPE_VERBS,
325 /* Matcher PRM representation */
326 struct mlx5_flow_dv_match_params {
328 /**< Size of match value. Do NOT split size and key! */
329 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
330 /**< Matcher value. This value is used as the mask or as a key. */
333 /* Matcher structure. */
334 struct mlx5_flow_dv_matcher {
335 LIST_ENTRY(mlx5_flow_dv_matcher) next;
336 /* Pointer to the next element. */
337 rte_atomic32_t refcnt; /**< Reference counter. */
338 void *matcher_object; /**< Pointer to DV matcher */
339 uint16_t crc; /**< CRC of key. */
340 uint16_t priority; /**< Priority of matcher. */
341 uint8_t egress; /**< Egress matcher. */
342 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
343 uint32_t group; /**< The matcher group. */
344 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
347 #define MLX5_ENCAP_MAX_LEN 132
349 /* Encap/decap resource structure. */
350 struct mlx5_flow_dv_encap_decap_resource {
351 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
352 /* Pointer to next element. */
353 rte_atomic32_t refcnt; /**< Reference counter. */
355 /**< Verbs encap/decap action object. */
356 uint8_t buf[MLX5_ENCAP_MAX_LEN];
358 uint8_t reformat_type;
360 uint64_t flags; /**< Flags for RDMA API. */
363 /* Tag resource structure. */
364 struct mlx5_flow_dv_tag_resource {
365 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
366 /* Pointer to next element. */
367 rte_atomic32_t refcnt; /**< Reference counter. */
369 /**< Verbs tag action object. */
370 uint32_t tag; /**< the tag value. */
374 * Number of modification commands.
375 * If extensive metadata registers are supported
376 * the maximal actions amount is 16 and 8 otherwise.
378 #define MLX5_MODIFY_NUM 16
379 #define MLX5_MODIFY_NUM_NO_MREG 8
381 /* Modify resource structure */
382 struct mlx5_flow_dv_modify_hdr_resource {
383 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
384 /* Pointer to next element. */
385 rte_atomic32_t refcnt; /**< Reference counter. */
386 struct ibv_flow_action *verbs_action;
387 /**< Verbs modify header action object. */
388 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
389 uint32_t actions_num; /**< Number of modification actions. */
390 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
391 /**< Modification actions. */
392 uint64_t flags; /**< Flags for RDMA API. */
395 /* Jump action resource structure. */
396 struct mlx5_flow_dv_jump_tbl_resource {
397 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
398 /* Pointer to next element. */
399 rte_atomic32_t refcnt; /**< Reference counter. */
400 void *action; /**< Pointer to the rdma core action. */
401 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
402 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
405 /* Port ID resource structure. */
406 struct mlx5_flow_dv_port_id_action_resource {
407 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
408 /* Pointer to next element. */
409 rte_atomic32_t refcnt; /**< Reference counter. */
411 /**< Verbs tag action object. */
412 uint32_t port_id; /**< Port ID value. */
415 /* Push VLAN action resource structure */
416 struct mlx5_flow_dv_push_vlan_action_resource {
417 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
418 /* Pointer to next element. */
419 rte_atomic32_t refcnt; /**< Reference counter. */
420 void *action; /**< Direct verbs action object. */
421 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
422 rte_be32_t vlan_tag; /**< VLAN tag value. */
425 /* Metadata register copy table entry. */
426 struct mlx5_flow_mreg_copy_resource {
428 * Hash list entry for copy table.
429 * - Key is 32/64-bit MARK action ID.
430 * - MUST be the first entry.
432 struct mlx5_hlist_entry hlist_ent;
433 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
434 /* List entry for device flows. */
435 uint32_t refcnt; /* Reference counter. */
436 uint32_t appcnt; /* Apply/Remove counter. */
437 struct rte_flow *flow; /* Built flow for copy. */
441 * Max number of actions per DV flow.
442 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
443 * In rdma-core file providers/mlx5/verbs.c
445 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
447 /* DV flows structure. */
448 struct mlx5_flow_dv {
449 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
451 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
452 struct mlx5_flow_dv_match_params value;
453 /**< Holds the value that the packet is compared to. */
454 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
455 /**< Pointer to encap/decap resource in cache. */
456 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
457 /**< Pointer to modify header resource in cache. */
458 struct ibv_flow *flow; /**< Installed flow. */
459 struct mlx5_flow_dv_jump_tbl_resource *jump;
460 /**< Pointer to the jump action resource. */
461 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
462 /**< Pointer to port ID action resource. */
463 struct mlx5_vf_vlan vf_vlan;
464 /**< Structure for VF VLAN workaround. */
465 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
466 /**< Pointer to push VLAN action resource in cache. */
467 struct mlx5_flow_dv_tag_resource *tag_resource;
468 /**< pointer to the tag action. */
469 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
470 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
473 int actions_n; /**< number of actions. */
476 /* Verbs specification header. */
477 struct ibv_spec_header {
478 enum ibv_flow_spec_type type;
482 /** Handles information leading to a drop fate. */
483 struct mlx5_flow_verbs {
484 LIST_ENTRY(mlx5_flow_verbs) next;
485 unsigned int size; /**< Size of the attribute. */
487 struct ibv_flow_attr *attr;
488 /**< Pointer to the Specification buffer. */
489 uint8_t *specs; /**< Pointer to the specifications. */
491 struct ibv_flow *flow; /**< Verbs flow pointer. */
492 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
493 struct mlx5_vf_vlan vf_vlan;
494 /**< Structure for VF VLAN workaround. */
497 struct mlx5_flow_rss {
499 uint32_t queue_num; /**< Number of entries in @p queue. */
500 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
501 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
502 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
505 /** Device flow structure. */
507 LIST_ENTRY(mlx5_flow) next;
508 struct rte_flow *flow; /**< Pointer to the main flow. */
510 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
512 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
513 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
514 uint8_t ingress; /**< 1 if the flow is ingress. */
515 uint32_t group; /**< The group index. */
516 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
518 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
519 struct mlx5_flow_dv dv;
521 struct mlx5_flow_verbs verbs;
524 uint32_t qrss_id; /**< Uniqie Q/RSS suffix subflow tag. */
525 uint32_t mtr_flow_id; /**< Unique meter match flow id. */
527 bool external; /**< true if the flow is created external to PMD. */
530 /* Flow meter state. */
531 #define MLX5_FLOW_METER_DISABLE 0
532 #define MLX5_FLOW_METER_ENABLE 1
534 #define MLX5_MAN_WIDTH 8
535 /* Modify this value if enum rte_mtr_color changes. */
536 #define RTE_MTR_DROPPED RTE_COLORS
538 /* Meter policer statistics */
539 struct mlx5_flow_policer_stats {
540 struct mlx5_flow_counter *cnt[RTE_COLORS + 1];
541 /**< Color counter, extra for drop. */
543 /**< Statistics mask for the colors. */
546 /* Meter table structure. */
547 struct mlx5_meter_domain_info {
548 struct mlx5_flow_tbl_resource *tbl;
551 /**< Meter color not match default criteria. */
553 /**< Meter color match criteria. */
555 /**< Meter match action. */
556 void *policer_rules[RTE_MTR_DROPPED + 1];
557 /**< Meter policer for the match. */
560 /* Meter table set for TX RX FDB. */
561 struct mlx5_meter_domains_infos {
563 /**< Table user count. */
564 struct mlx5_meter_domain_info egress;
565 /**< TX meter table. */
566 struct mlx5_meter_domain_info ingress;
567 /**< RX meter table. */
568 struct mlx5_meter_domain_info transfer;
569 /**< FDB meter table. */
571 /**< Drop action as not matched. */
572 void *count_actns[RTE_MTR_DROPPED + 1];
573 /**< Counters for match and unmatched statistics. */
574 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
575 /**< Flow meter parameter. */
577 /**< Flow meter parameter size. */
579 /**< Flow meter action. */
582 /* Meter parameter structure. */
583 struct mlx5_flow_meter {
584 TAILQ_ENTRY(mlx5_flow_meter) next;
585 /**< Pointer to the next flow meter structure. */
588 struct rte_mtr_params params;
589 /**< Meter rule parameters. */
590 struct mlx5_flow_meter_profile *profile;
591 /**< Meter profile parameters. */
592 struct rte_flow_attr attr;
593 /**< Flow attributes. */
594 struct mlx5_meter_domains_infos *mfts;
595 /**< Flow table created for this meter. */
596 struct mlx5_flow_policer_stats policer_stats;
597 /**< Meter policer statistics. */
600 uint32_t active_state:1;
603 /**< Meter shared or not. */
606 /* RFC2697 parameter structure. */
607 struct mlx5_flow_meter_srtcm_rfc2697_prm {
608 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
609 uint32_t cbs_exponent:5;
610 uint32_t cbs_mantissa:8;
611 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
612 uint32_t cir_exponent:5;
613 uint32_t cir_mantissa:8;
614 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
615 uint32_t ebs_exponent:5;
616 uint32_t ebs_mantissa:8;
619 /* Flow meter profile structure. */
620 struct mlx5_flow_meter_profile {
621 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
622 /**< Pointer to the next flow meter structure. */
623 uint32_t meter_profile_id; /**< Profile id. */
624 struct rte_mtr_meter_profile profile; /**< Profile detail. */
626 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
627 /**< srtcm_rfc2697 struct. */
629 uint32_t ref_cnt; /**< Use count. */
632 /* Flow structure. */
634 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
635 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
636 struct mlx5_flow_rss rss; /**< RSS context. */
637 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
638 struct mlx5_flow_mreg_copy_resource *mreg_copy;
639 /**< pointer to metadata register copy table resource. */
640 struct mlx5_flow_meter *meter; /**< Holds flow meter. */
641 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
642 /**< Device flows that are part of the flow. */
643 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
644 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
645 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
648 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
649 const struct rte_flow_attr *attr,
650 const struct rte_flow_item items[],
651 const struct rte_flow_action actions[],
653 struct rte_flow_error *error);
654 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
655 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
656 const struct rte_flow_action actions[], struct rte_flow_error *error);
657 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
658 struct mlx5_flow *dev_flow,
659 const struct rte_flow_attr *attr,
660 const struct rte_flow_item items[],
661 const struct rte_flow_action actions[],
662 struct rte_flow_error *error);
663 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
664 struct rte_flow_error *error);
665 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
666 struct rte_flow *flow);
667 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
668 struct rte_flow *flow);
669 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
670 struct rte_flow *flow,
671 const struct rte_flow_action *actions,
673 struct rte_flow_error *error);
674 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
675 (struct rte_eth_dev *dev,
676 const struct mlx5_flow_meter *fm);
677 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
678 struct mlx5_meter_domains_infos *tbls);
679 typedef int (*mlx5_flow_create_policer_rules_t)
680 (struct rte_eth_dev *dev,
681 struct mlx5_flow_meter *fm,
682 const struct rte_flow_attr *attr);
683 typedef int (*mlx5_flow_destroy_policer_rules_t)
684 (struct rte_eth_dev *dev,
685 const struct mlx5_flow_meter *fm,
686 const struct rte_flow_attr *attr);
687 typedef struct mlx5_flow_counter * (*mlx5_flow_counter_alloc_t)
688 (struct rte_eth_dev *dev);
689 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
690 struct mlx5_flow_counter *cnt);
691 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
692 struct mlx5_flow_counter *cnt,
693 bool clear, uint64_t *pkts,
695 struct mlx5_flow_driver_ops {
696 mlx5_flow_validate_t validate;
697 mlx5_flow_prepare_t prepare;
698 mlx5_flow_translate_t translate;
699 mlx5_flow_apply_t apply;
700 mlx5_flow_remove_t remove;
701 mlx5_flow_destroy_t destroy;
702 mlx5_flow_query_t query;
703 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
704 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
705 mlx5_flow_create_policer_rules_t create_policer_rules;
706 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
707 mlx5_flow_counter_alloc_t counter_alloc;
708 mlx5_flow_counter_free_t counter_free;
709 mlx5_flow_counter_query_t counter_query;
713 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
714 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
715 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
716 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
720 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
721 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
722 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
723 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
725 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
726 bool external, uint32_t group, uint32_t *table,
727 struct rte_flow_error *error);
728 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
729 uint64_t layer_types,
730 uint64_t hash_fields);
731 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
732 uint32_t subpriority);
733 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
734 enum mlx5_feature_name feature,
736 struct rte_flow_error *error);
737 const struct rte_flow_action *mlx5_flow_find_action
738 (const struct rte_flow_action *actions,
739 enum rte_flow_action_type action);
740 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
741 const struct rte_flow_attr *attr,
742 struct rte_flow_error *error);
743 int mlx5_flow_validate_action_drop(uint64_t action_flags,
744 const struct rte_flow_attr *attr,
745 struct rte_flow_error *error);
746 int mlx5_flow_validate_action_flag(uint64_t action_flags,
747 const struct rte_flow_attr *attr,
748 struct rte_flow_error *error);
749 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
750 uint64_t action_flags,
751 const struct rte_flow_attr *attr,
752 struct rte_flow_error *error);
753 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
754 uint64_t action_flags,
755 struct rte_eth_dev *dev,
756 const struct rte_flow_attr *attr,
757 struct rte_flow_error *error);
758 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
759 uint64_t action_flags,
760 struct rte_eth_dev *dev,
761 const struct rte_flow_attr *attr,
763 struct rte_flow_error *error);
764 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
765 const struct rte_flow_attr *attributes,
766 struct rte_flow_error *error);
767 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
769 const uint8_t *nic_mask,
771 struct rte_flow_error *error);
772 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
774 struct rte_flow_error *error);
775 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
777 uint8_t target_protocol,
778 struct rte_flow_error *error);
779 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
781 const struct rte_flow_item *gre_item,
782 struct rte_flow_error *error);
783 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
787 const struct rte_flow_item_ipv4 *acc_mask,
788 struct rte_flow_error *error);
789 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
793 const struct rte_flow_item_ipv6 *acc_mask,
794 struct rte_flow_error *error);
795 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
796 const struct rte_flow_item *item,
799 struct rte_flow_error *error);
800 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
802 uint8_t target_protocol,
803 const struct rte_flow_item_tcp *flow_mask,
804 struct rte_flow_error *error);
805 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
807 uint8_t target_protocol,
808 struct rte_flow_error *error);
809 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
811 struct rte_eth_dev *dev,
812 struct rte_flow_error *error);
813 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
815 struct rte_flow_error *error);
816 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
818 struct rte_eth_dev *dev,
819 struct rte_flow_error *error);
820 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
822 uint8_t target_protocol,
823 struct rte_flow_error *error);
824 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
826 uint8_t target_protocol,
827 struct rte_flow_error *error);
828 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
830 uint8_t target_protocol,
831 struct rte_flow_error *error);
832 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
834 struct rte_eth_dev *dev,
835 struct rte_flow_error *error);
836 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
837 (struct rte_eth_dev *dev,
838 const struct mlx5_flow_meter *fm);
839 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
840 struct mlx5_meter_domains_infos *tbl);
841 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
842 struct mlx5_flow_meter *fm,
843 const struct rte_flow_attr *attr);
844 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
845 struct mlx5_flow_meter *fm,
846 const struct rte_flow_attr *attr);
847 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
848 struct rte_mtr_error *error);
849 #endif /* RTE_PMD_MLX5_FLOW_H_ */