1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* E-Switch Manager port, used for rte_flow_item_port_id. */
22 #define MLX5_PORT_ESW_MGR UINT32_MAX
24 /* Private rte flow items. */
25 enum mlx5_rte_flow_item_type {
26 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
28 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
29 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
30 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
33 /* Private (internal) rte flow actions. */
34 enum mlx5_rte_flow_action_type {
35 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
36 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
37 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
38 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
39 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
41 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
43 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
46 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
49 MLX5_INDIRECT_ACTION_TYPE_RSS,
50 MLX5_INDIRECT_ACTION_TYPE_AGE,
51 MLX5_INDIRECT_ACTION_TYPE_COUNT,
52 MLX5_INDIRECT_ACTION_TYPE_CT,
55 /* Now, the maximal ports will be supported is 256, action number is 4M. */
56 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100
58 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22
59 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)
61 /* 30-31: type, 22-29: owner port, 0-21: index. */
62 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \
63 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \
64 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \
65 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index))
67 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \
68 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \
69 MLX5_INDIRECT_ACT_CT_OWNER_MASK)
71 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \
72 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))
74 /* Matches on selected register. */
75 struct mlx5_rte_flow_item_tag {
80 /* Modify selected register. */
81 struct mlx5_rte_flow_action_set_tag {
88 struct mlx5_flow_action_copy_mreg {
93 /* Matches on source queue. */
94 struct mlx5_rte_flow_item_tx_queue {
98 /* Feature name to allocate metadata register. */
99 enum mlx5_feature_name {
114 /* Default queue number. */
115 #define MLX5_RSSQ_DEFAULT_NUM 16
117 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
118 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
119 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
120 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
121 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
122 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
124 /* Pattern inner Layer bits. */
125 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
126 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
127 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
128 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
129 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
130 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
132 /* Pattern tunnel Layer bits. */
133 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
134 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
135 #define MLX5_FLOW_LAYER_GRE (1u << 14)
136 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
137 /* List of tunnel Layer bits continued below. */
139 /* General pattern items bits. */
140 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
141 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
142 #define MLX5_FLOW_ITEM_TAG (1u << 18)
143 #define MLX5_FLOW_ITEM_MARK (1u << 19)
145 /* Pattern MISC bits. */
146 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
147 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
148 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
150 /* Pattern tunnel Layer bits (continued). */
151 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
152 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
153 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
154 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
157 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
159 /* Pattern tunnel Layer bits (continued). */
160 #define MLX5_FLOW_LAYER_GTP (1u << 28)
162 /* Pattern eCPRI Layer bit. */
163 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
165 /* IPv6 Fragment Extension Header bit. */
166 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
167 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
169 /* Pattern tunnel Layer bits (continued). */
170 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
171 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
173 /* INTEGRITY item bits */
174 #define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34)
175 #define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35)
176 #define MLX5_FLOW_ITEM_INTEGRITY \
177 (MLX5_FLOW_ITEM_OUTER_INTEGRITY | MLX5_FLOW_ITEM_INNER_INTEGRITY)
179 /* Conntrack item. */
180 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36)
183 #define MLX5_FLOW_LAYER_OUTER_L3 \
184 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
185 #define MLX5_FLOW_LAYER_OUTER_L4 \
186 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
187 #define MLX5_FLOW_LAYER_OUTER \
188 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
189 MLX5_FLOW_LAYER_OUTER_L4)
192 #define MLX5_FLOW_LAYER_TUNNEL \
193 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
194 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
195 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
196 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
199 #define MLX5_FLOW_LAYER_INNER_L3 \
200 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
201 #define MLX5_FLOW_LAYER_INNER_L4 \
202 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
203 #define MLX5_FLOW_LAYER_INNER \
204 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
205 MLX5_FLOW_LAYER_INNER_L4)
208 #define MLX5_FLOW_LAYER_L2 \
209 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
210 #define MLX5_FLOW_LAYER_L3_IPV4 \
211 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
212 #define MLX5_FLOW_LAYER_L3_IPV6 \
213 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
214 #define MLX5_FLOW_LAYER_L3 \
215 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
216 #define MLX5_FLOW_LAYER_L4 \
217 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
220 #define MLX5_FLOW_ACTION_DROP (1u << 0)
221 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
222 #define MLX5_FLOW_ACTION_RSS (1u << 2)
223 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
224 #define MLX5_FLOW_ACTION_MARK (1u << 4)
225 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
226 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
227 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
228 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
229 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
230 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
231 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
232 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
233 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
234 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
235 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
236 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
237 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
238 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
239 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
240 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
241 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
242 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
243 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
244 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
245 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
246 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
247 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
248 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
249 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
250 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
251 #define MLX5_FLOW_ACTION_METER (1ull << 31)
252 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
253 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
254 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
255 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
256 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
257 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
258 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
259 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
260 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
261 #define MLX5_FLOW_ACTION_CT (1ull << 41)
263 #define MLX5_FLOW_FATE_ACTIONS \
264 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
265 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
266 MLX5_FLOW_ACTION_DEFAULT_MISS | \
267 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
269 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
270 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
271 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
273 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
274 MLX5_FLOW_ACTION_SET_IPV4_DST | \
275 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
276 MLX5_FLOW_ACTION_SET_IPV6_DST | \
277 MLX5_FLOW_ACTION_SET_TP_SRC | \
278 MLX5_FLOW_ACTION_SET_TP_DST | \
279 MLX5_FLOW_ACTION_SET_TTL | \
280 MLX5_FLOW_ACTION_DEC_TTL | \
281 MLX5_FLOW_ACTION_SET_MAC_SRC | \
282 MLX5_FLOW_ACTION_SET_MAC_DST | \
283 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
284 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
285 MLX5_FLOW_ACTION_INC_TCP_ACK | \
286 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
287 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
288 MLX5_FLOW_ACTION_SET_TAG | \
289 MLX5_FLOW_ACTION_MARK_EXT | \
290 MLX5_FLOW_ACTION_SET_META | \
291 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
292 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
293 MLX5_FLOW_ACTION_MODIFY_FIELD)
295 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
296 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
298 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
301 #define IPPROTO_MPLS 137
304 /* UDP port number for MPLS */
305 #define MLX5_UDP_PORT_MPLS 6635
307 /* UDP port numbers for VxLAN. */
308 #define MLX5_UDP_PORT_VXLAN 4789
309 #define MLX5_UDP_PORT_VXLAN_GPE 4790
311 /* UDP port numbers for GENEVE. */
312 #define MLX5_UDP_PORT_GENEVE 6081
314 /* Lowest priority indicator. */
315 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
318 * Max priority for ingress\egress flow groups
319 * greater than 0 and for any transfer flow group.
320 * From user configation: 0 - 21843.
322 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
325 * Number of sub priorities.
326 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
327 * matching on the NIC (firmware dependent) L4 most have the higher priority
328 * followed by L3 and ending with L2.
330 #define MLX5_PRIORITY_MAP_L2 2
331 #define MLX5_PRIORITY_MAP_L3 1
332 #define MLX5_PRIORITY_MAP_L4 0
333 #define MLX5_PRIORITY_MAP_MAX 3
335 /* Valid layer type for IPV4 RSS. */
336 #define MLX5_IPV4_LAYER_TYPES \
337 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \
338 RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
339 RTE_ETH_RSS_NONFRAG_IPV4_OTHER)
341 /* IBV hash source bits for IPV4. */
342 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
344 /* Valid layer type for IPV6 RSS. */
345 #define MLX5_IPV6_LAYER_TYPES \
346 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
347 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | \
348 RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER)
350 /* IBV hash source bits for IPV6. */
351 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
353 /* IBV hash bits for L3 SRC. */
354 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
356 /* IBV hash bits for L3 DST. */
357 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
359 /* IBV hash bits for TCP. */
360 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
361 IBV_RX_HASH_DST_PORT_TCP)
363 /* IBV hash bits for UDP. */
364 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
365 IBV_RX_HASH_DST_PORT_UDP)
367 /* IBV hash bits for L4 SRC. */
368 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
369 IBV_RX_HASH_SRC_PORT_UDP)
371 /* IBV hash bits for L4 DST. */
372 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
373 IBV_RX_HASH_DST_PORT_UDP)
375 /* Geneve header first 16Bit */
376 #define MLX5_GENEVE_VER_MASK 0x3
377 #define MLX5_GENEVE_VER_SHIFT 14
378 #define MLX5_GENEVE_VER_VAL(a) \
379 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
380 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
381 #define MLX5_GENEVE_OPTLEN_SHIFT 8
382 #define MLX5_GENEVE_OPTLEN_VAL(a) \
383 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
384 #define MLX5_GENEVE_OAMF_MASK 0x1
385 #define MLX5_GENEVE_OAMF_SHIFT 7
386 #define MLX5_GENEVE_OAMF_VAL(a) \
387 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
388 #define MLX5_GENEVE_CRITO_MASK 0x1
389 #define MLX5_GENEVE_CRITO_SHIFT 6
390 #define MLX5_GENEVE_CRITO_VAL(a) \
391 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
392 #define MLX5_GENEVE_RSVD_MASK 0x3F
393 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
395 * The length of the Geneve options fields, expressed in four byte multiples,
396 * not including the eight byte fixed tunnel.
398 #define MLX5_GENEVE_OPT_LEN_0 14
399 #define MLX5_GENEVE_OPT_LEN_1 63
401 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
402 sizeof(struct rte_ipv4_hdr))
403 /* GTP extension header flag. */
404 #define MLX5_GTP_EXT_HEADER_FLAG 4
406 /* GTP extension header PDU type shift. */
407 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
409 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
410 #define MLX5_IPV4_FRAG_OFFSET_MASK \
411 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
413 /* Specific item's fields can accept a range of values (using spec and last). */
414 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
415 #define MLX5_ITEM_RANGE_ACCEPTED true
417 /* Software header modify action numbers of a flow. */
418 #define MLX5_ACT_NUM_MDF_IPV4 1
419 #define MLX5_ACT_NUM_MDF_IPV6 4
420 #define MLX5_ACT_NUM_MDF_MAC 2
421 #define MLX5_ACT_NUM_MDF_VID 1
422 #define MLX5_ACT_NUM_MDF_PORT 2
423 #define MLX5_ACT_NUM_MDF_TTL 1
424 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
425 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
426 #define MLX5_ACT_NUM_MDF_TCPACK 1
427 #define MLX5_ACT_NUM_SET_REG 1
428 #define MLX5_ACT_NUM_SET_TAG 1
429 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
430 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
431 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
432 #define MLX5_ACT_NUM_SET_DSCP 1
434 /* Maximum number of fields to modify in MODIFY_FIELD */
435 #define MLX5_ACT_MAX_MOD_FIELDS 5
437 /* Syndrome bits definition for connection tracking. */
438 #define MLX5_CT_SYNDROME_VALID (0x0 << 6)
439 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6)
440 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6)
441 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1)
442 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0)
444 enum mlx5_flow_drv_type {
447 MLX5_FLOW_TYPE_VERBS,
451 /* Fate action type. */
452 enum mlx5_flow_fate_type {
453 MLX5_FLOW_FATE_NONE, /* Egress flow. */
454 MLX5_FLOW_FATE_QUEUE,
456 MLX5_FLOW_FATE_PORT_ID,
458 MLX5_FLOW_FATE_DEFAULT_MISS,
459 MLX5_FLOW_FATE_SHARED_RSS,
464 /* Matcher PRM representation */
465 struct mlx5_flow_dv_match_params {
467 /**< Size of match value. Do NOT split size and key! */
468 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
469 /**< Matcher value. This value is used as the mask or as a key. */
472 /* Matcher structure. */
473 struct mlx5_flow_dv_matcher {
474 struct mlx5_list_entry entry; /**< Pointer to the next element. */
475 struct mlx5_flow_tbl_resource *tbl;
476 /**< Pointer to the table(group) the matcher associated with. */
477 void *matcher_object; /**< Pointer to DV matcher */
478 uint16_t crc; /**< CRC of key. */
479 uint16_t priority; /**< Priority of matcher. */
480 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
483 #define MLX5_ENCAP_MAX_LEN 132
485 /* Encap/decap resource structure. */
486 struct mlx5_flow_dv_encap_decap_resource {
487 struct mlx5_list_entry entry;
488 /* Pointer to next element. */
489 uint32_t refcnt; /**< Reference counter. */
491 /**< Encap/decap action object. */
492 uint8_t buf[MLX5_ENCAP_MAX_LEN];
494 uint8_t reformat_type;
496 uint64_t flags; /**< Flags for RDMA API. */
497 uint32_t idx; /**< Index for the index memory pool. */
500 /* Tag resource structure. */
501 struct mlx5_flow_dv_tag_resource {
502 struct mlx5_list_entry entry;
503 /**< hash list entry for tag resource, tag value as the key. */
505 /**< Tag action object. */
506 uint32_t refcnt; /**< Reference counter. */
507 uint32_t idx; /**< Index for the index memory pool. */
508 uint32_t tag_id; /**< Tag ID. */
511 /* Modify resource structure */
512 struct mlx5_flow_dv_modify_hdr_resource {
513 struct mlx5_list_entry entry;
514 void *action; /**< Modify header action object. */
516 /* Key area for hash list matching: */
517 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
518 uint8_t actions_num; /**< Number of modification actions. */
519 bool root; /**< Whether action is in root table. */
520 struct mlx5_modification_cmd actions[];
521 /**< Modification actions. */
524 /* Modify resource key of the hash organization. */
525 union mlx5_flow_modify_hdr_key {
527 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
528 uint32_t actions_num:5; /**< Number of modification actions. */
529 uint32_t group:19; /**< Flow group id. */
530 uint32_t cksum; /**< Actions check sum. */
532 uint64_t v64; /**< full 64bits value of key */
535 /* Jump action resource structure. */
536 struct mlx5_flow_dv_jump_tbl_resource {
537 void *action; /**< Pointer to the rdma core action. */
540 /* Port ID resource structure. */
541 struct mlx5_flow_dv_port_id_action_resource {
542 struct mlx5_list_entry entry;
543 void *action; /**< Action object. */
544 uint32_t port_id; /**< Port ID value. */
545 uint32_t idx; /**< Indexed pool memory index. */
548 /* Push VLAN action resource structure */
549 struct mlx5_flow_dv_push_vlan_action_resource {
550 struct mlx5_list_entry entry; /* Cache entry. */
551 void *action; /**< Action object. */
552 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
553 rte_be32_t vlan_tag; /**< VLAN tag value. */
554 uint32_t idx; /**< Indexed pool memory index. */
557 /* Metadata register copy table entry. */
558 struct mlx5_flow_mreg_copy_resource {
560 * Hash list entry for copy table.
561 * - Key is 32/64-bit MARK action ID.
562 * - MUST be the first entry.
564 struct mlx5_list_entry hlist_ent;
565 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
566 /* List entry for device flows. */
568 uint32_t rix_flow; /* Built flow for copy. */
572 /* Table tunnel parameter. */
573 struct mlx5_flow_tbl_tunnel_prm {
574 const struct mlx5_flow_tunnel *tunnel;
579 /* Table data structure of the hash organization. */
580 struct mlx5_flow_tbl_data_entry {
581 struct mlx5_list_entry entry;
582 /**< hash list entry, 64-bits key inside. */
583 struct mlx5_flow_tbl_resource tbl;
584 /**< flow table resource. */
585 struct mlx5_list *matchers;
586 /**< matchers' header associated with the flow table. */
587 struct mlx5_flow_dv_jump_tbl_resource jump;
588 /**< jump resource, at most one for each table created. */
589 uint32_t idx; /**< index for the indexed mempool. */
590 /**< tunnel offload */
591 const struct mlx5_flow_tunnel *tunnel;
594 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
595 uint32_t is_egress:1; /**< Egress table. */
596 uint32_t is_transfer:1; /**< Transfer table. */
597 uint32_t dummy:1; /**< DR table. */
598 uint32_t id:22; /**< Table ID. */
599 uint32_t reserve:5; /**< Reserved to future using. */
600 uint32_t level; /**< Table level. */
603 /* Sub rdma-core actions list. */
604 struct mlx5_flow_sub_actions_list {
605 uint32_t actions_num; /**< Number of sample actions. */
606 uint64_t action_flags;
607 void *dr_queue_action;
610 void *dr_port_id_action;
611 void *dr_encap_action;
612 void *dr_jump_action;
615 /* Sample sub-actions resource list. */
616 struct mlx5_flow_sub_actions_idx {
617 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
618 uint32_t rix_tag; /**< Index to the tag action. */
619 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
620 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
621 uint32_t rix_jump; /**< Index to the jump action resource. */
624 /* Sample action resource structure. */
625 struct mlx5_flow_dv_sample_resource {
626 struct mlx5_list_entry entry; /**< Cache entry. */
628 void *verbs_action; /**< Verbs sample action object. */
629 void **sub_actions; /**< Sample sub-action array. */
631 struct rte_eth_dev *dev; /**< Device registers the action. */
632 uint32_t idx; /** Sample object index. */
633 uint8_t ft_type; /** Flow Table Type */
634 uint32_t ft_id; /** Flow Table Level */
635 uint32_t ratio; /** Sample Ratio */
636 uint64_t set_action; /** Restore reg_c0 value */
637 void *normal_path_tbl; /** Flow Table pointer */
638 struct mlx5_flow_sub_actions_idx sample_idx;
639 /**< Action index resources. */
640 struct mlx5_flow_sub_actions_list sample_act;
641 /**< Action resources. */
644 #define MLX5_MAX_DEST_NUM 2
646 /* Destination array action resource structure. */
647 struct mlx5_flow_dv_dest_array_resource {
648 struct mlx5_list_entry entry; /**< Cache entry. */
649 uint32_t idx; /** Destination array action object index. */
650 uint8_t ft_type; /** Flow Table Type */
651 uint8_t num_of_dest; /**< Number of destination actions. */
652 struct rte_eth_dev *dev; /**< Device registers the action. */
653 void *action; /**< Pointer to the rdma core action. */
654 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
655 /**< Action index resources. */
656 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
657 /**< Action resources. */
660 /* PMD flow priority for tunnel */
661 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
662 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
665 /** Device flow handle structure for DV mode only. */
666 struct mlx5_flow_handle_dv {
668 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
669 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
670 /**< Pointer to modify header resource in cache. */
671 uint32_t rix_encap_decap;
672 /**< Index to encap/decap resource in cache. */
673 uint32_t rix_push_vlan;
674 /**< Index to push VLAN action resource in cache. */
676 /**< Index to the tag action. */
678 /**< Index to sample action resource in cache. */
679 uint32_t rix_dest_array;
680 /**< Index to destination array resource in cache. */
683 /** Device flow handle structure: used both for creating & destroying. */
684 struct mlx5_flow_handle {
685 SILIST_ENTRY(uint32_t)next;
686 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
687 /**< Index to next device flow handle. */
689 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
690 void *drv_flow; /**< pointer to driver flow object. */
691 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
692 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
693 uint32_t mark:1; /**< Metadate rxq mark flag. */
694 uint32_t fate_action:3; /**< Fate action type. */
696 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
697 uint32_t rix_jump; /**< Index to the jump action resource. */
698 uint32_t rix_port_id_action;
699 /**< Index to port ID action resource. */
701 /**< Generic value indicates the fate action. */
702 uint32_t rix_default_fate;
703 /**< Indicates default miss fate action. */
705 /**< Indicates shared RSS fate action. */
707 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
708 struct mlx5_flow_handle_dv dvh;
713 * Size for Verbs device flow handle structure only. Do not use the DV only
714 * structure in Verbs. No DV flows attributes will be accessed.
715 * Macro offsetof() could also be used here.
717 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
718 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
719 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
721 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
724 /** Device flow structure only for DV flow creation. */
725 struct mlx5_flow_dv_workspace {
726 uint32_t group; /**< The group index. */
727 uint32_t table_id; /**< Flow table identifier. */
728 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
729 int actions_n; /**< number of actions. */
730 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
731 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
732 /**< Pointer to encap/decap resource in cache. */
733 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
734 /**< Pointer to push VLAN action resource in cache. */
735 struct mlx5_flow_dv_tag_resource *tag_resource;
736 /**< pointer to the tag action. */
737 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
738 /**< Pointer to port ID action resource. */
739 struct mlx5_flow_dv_jump_tbl_resource *jump;
740 /**< Pointer to the jump action resource. */
741 struct mlx5_flow_dv_match_params value;
742 /**< Holds the value that the packet is compared to. */
743 struct mlx5_flow_dv_sample_resource *sample_res;
744 /**< Pointer to the sample action resource. */
745 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
746 /**< Pointer to the destination array resource. */
749 #ifdef HAVE_INFINIBAND_VERBS_H
751 * Maximal Verbs flow specifications & actions size.
752 * Some elements are mutually exclusive, but enough space should be allocated.
753 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
754 * 2. One tunnel header (exception: GRE + MPLS),
755 * SPEC length: GRE == tunnel.
756 * Actions: 1. 1 Mark OR Flag.
757 * 2. 1 Drop (if any).
758 * 3. No limitation for counters, but it makes no sense to support too
759 * many counters in a single device flow.
761 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
762 #define MLX5_VERBS_MAX_SPEC_SIZE \
764 (2 * (sizeof(struct ibv_flow_spec_eth) + \
765 sizeof(struct ibv_flow_spec_ipv6) + \
766 sizeof(struct ibv_flow_spec_tcp_udp)) + \
767 sizeof(struct ibv_flow_spec_gre) + \
768 sizeof(struct ibv_flow_spec_mpls)) \
771 #define MLX5_VERBS_MAX_SPEC_SIZE \
773 (2 * (sizeof(struct ibv_flow_spec_eth) + \
774 sizeof(struct ibv_flow_spec_ipv6) + \
775 sizeof(struct ibv_flow_spec_tcp_udp)) + \
776 sizeof(struct ibv_flow_spec_tunnel)) \
780 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
781 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
782 #define MLX5_VERBS_MAX_ACT_SIZE \
784 sizeof(struct ibv_flow_spec_action_tag) + \
785 sizeof(struct ibv_flow_spec_action_drop) + \
786 sizeof(struct ibv_flow_spec_counter_action) * 4 \
789 #define MLX5_VERBS_MAX_ACT_SIZE \
791 sizeof(struct ibv_flow_spec_action_tag) + \
792 sizeof(struct ibv_flow_spec_action_drop) \
796 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
797 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
799 /** Device flow structure only for Verbs flow creation. */
800 struct mlx5_flow_verbs_workspace {
801 unsigned int size; /**< Size of the attribute. */
802 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
803 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
804 /**< Specifications & actions buffer of verbs flow. */
806 #endif /* HAVE_INFINIBAND_VERBS_H */
808 #define MLX5_SCALE_FLOW_GROUP_BIT 0
809 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
811 /** Maximal number of device sub-flows supported. */
812 #define MLX5_NUM_MAX_DEV_FLOWS 32
815 * tunnel offload rules type
817 enum mlx5_tof_rule_type {
818 MLX5_TUNNEL_OFFLOAD_NONE = 0,
819 MLX5_TUNNEL_OFFLOAD_SET_RULE,
820 MLX5_TUNNEL_OFFLOAD_MATCH_RULE,
821 MLX5_TUNNEL_OFFLOAD_MISS_RULE,
824 /** Device flow structure. */
827 struct rte_flow *flow; /**< Pointer to the main flow. */
828 uint32_t flow_idx; /**< The memory pool index to the main flow. */
829 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
831 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
832 bool external; /**< true if the flow is created external to PMD. */
833 uint8_t ingress:1; /**< 1 if the flow is ingress. */
834 uint8_t skip_scale:2;
836 * Each Bit be set to 1 if Skip the scale the flow group with factor.
837 * If bit0 be set to 1, then skip the scale the original flow group;
838 * If bit1 be set to 1, then skip the scale the jump flow group if
839 * having jump action.
840 * 00: Enable scale in a flow, default value.
841 * 01: Skip scale the flow group with factor, enable scale the group
843 * 10: Enable scale the group with factor, skip scale the group of
845 * 11: Skip scale the table with factor both for flow group and jump
849 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
850 struct mlx5_flow_dv_workspace dv;
852 #ifdef HAVE_INFINIBAND_VERBS_H
853 struct mlx5_flow_verbs_workspace verbs;
856 struct mlx5_flow_handle *handle;
857 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
858 const struct mlx5_flow_tunnel *tunnel;
859 enum mlx5_tof_rule_type tof_type;
862 /* Flow meter state. */
863 #define MLX5_FLOW_METER_DISABLE 0
864 #define MLX5_FLOW_METER_ENABLE 1
866 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
867 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
869 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
871 #define MLX5_MAN_WIDTH 8
872 /* Legacy Meter parameter structure. */
873 struct mlx5_legacy_flow_meter {
874 struct mlx5_flow_meter_info fm;
875 /* Must be the first in struct. */
876 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
877 /**< Pointer to the next flow meter structure. */
879 /* Index to meter object. */
882 #define MLX5_MAX_TUNNELS 256
883 #define MLX5_TNL_MISS_RULE_PRIORITY 3
884 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
887 * When tunnel offload is active, all JUMP group ids are converted
888 * using the same method. That conversion is applied both to tunnel and
889 * regular rule types.
890 * Group ids used in tunnel rules are relative to it's tunnel (!).
891 * Application can create number of steer rules, using the same
892 * tunnel, with different group id in each rule.
893 * Each tunnel stores its groups internally in PMD tunnel object.
894 * Groups used in regular rules do not belong to any tunnel and are stored
898 struct mlx5_flow_tunnel {
899 LIST_ENTRY(mlx5_flow_tunnel) chain;
900 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
901 uint32_t tunnel_id; /** unique tunnel ID */
903 struct rte_flow_action action;
904 struct rte_flow_item item;
905 struct mlx5_hlist *groups; /** tunnel groups */
908 /** PMD tunnel related context */
909 struct mlx5_flow_tunnel_hub {
911 * Access to the list MUST be MT protected
913 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
914 /* protect access to the tunnels list */
916 struct mlx5_hlist *groups; /** non tunnel groups */
919 /* convert jump group to flow table ID in tunnel rules */
920 struct tunnel_tbl_entry {
921 struct mlx5_list_entry hash;
927 static inline uint32_t
928 tunnel_id_to_flow_tbl(uint32_t id)
930 return id | (1u << 16);
933 static inline uint32_t
934 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
936 return flow_tbl & ~(1u << 16);
939 union tunnel_tbl_key {
947 static inline struct mlx5_flow_tunnel_hub *
948 mlx5_tunnel_hub(struct rte_eth_dev *dev)
950 struct mlx5_priv *priv = dev->data->dev_private;
951 return priv->sh->tunnel_hub;
955 is_tunnel_offload_active(const struct rte_eth_dev *dev)
957 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
958 const struct mlx5_priv *priv = dev->data->dev_private;
959 return !!priv->config.dv_miss_info;
967 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type)
969 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE;
973 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type)
975 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE;
978 static inline const struct mlx5_flow_tunnel *
979 flow_actions_to_tunnel(const struct rte_flow_action actions[])
981 return actions[0].conf;
984 static inline const struct mlx5_flow_tunnel *
985 flow_items_to_tunnel(const struct rte_flow_item items[])
987 return items[0].spec;
990 /* Flow structure. */
992 uint32_t dev_handles;
993 /**< Device flow handles that are part of the flow. */
995 uint32_t drv_type:2; /**< Driver type. */
997 uint32_t meter:24; /**< Holds flow meter id. */
998 uint32_t indirect_type:2; /**< Indirect action type. */
999 uint32_t rix_mreg_copy;
1000 /**< Index to metadata register copy table resource. */
1001 uint32_t counter; /**< Holds flow counter. */
1002 uint32_t tunnel_id; /**< Tunnel id */
1004 uint32_t age; /**< Holds ASO age bit index. */
1005 uint32_t ct; /**< Holds ASO CT index. */
1007 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1011 * Define list of valid combinations of RX Hash fields
1012 * (see enum ibv_rx_hash_fields).
1014 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1015 #define MLX5_RSS_HASH_IPV4_TCP \
1016 (MLX5_RSS_HASH_IPV4 | \
1017 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1018 #define MLX5_RSS_HASH_IPV4_UDP \
1019 (MLX5_RSS_HASH_IPV4 | \
1020 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1021 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1022 #define MLX5_RSS_HASH_IPV6_TCP \
1023 (MLX5_RSS_HASH_IPV6 | \
1024 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1025 #define MLX5_RSS_HASH_IPV6_UDP \
1026 (MLX5_RSS_HASH_IPV6 | \
1027 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1028 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1029 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1030 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1031 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1032 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1033 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1034 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1035 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1036 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1037 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1038 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1039 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1040 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1041 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1042 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1043 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1044 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1045 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1046 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1047 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1048 #define MLX5_RSS_HASH_NONE 0ULL
1051 /* extract next protocol type from Ethernet & VLAN headers */
1052 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1053 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1054 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1055 (_prt) = rte_be_to_cpu_16((_prt)); \
1058 /* array of valid combinations of RX Hash fields for RSS */
1059 static const uint64_t mlx5_rss_hash_fields[] = {
1061 MLX5_RSS_HASH_IPV4_TCP,
1062 MLX5_RSS_HASH_IPV4_UDP,
1064 MLX5_RSS_HASH_IPV6_TCP,
1065 MLX5_RSS_HASH_IPV6_UDP,
1069 /* Shared RSS action structure */
1070 struct mlx5_shared_action_rss {
1071 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1072 uint32_t refcnt; /**< Atomically accessed refcnt. */
1073 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1074 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1075 struct mlx5_ind_table_obj *ind_tbl;
1076 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1077 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1078 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1079 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1082 struct rte_flow_action_handle {
1086 /* Thread specific flow workspace intermediate data. */
1087 struct mlx5_flow_workspace {
1088 /* If creating another flow in same thread, push new as stack. */
1089 struct mlx5_flow_workspace *prev;
1090 struct mlx5_flow_workspace *next;
1091 uint32_t inuse; /* can't create new flow with current. */
1092 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1093 struct mlx5_flow_rss_desc rss_desc;
1094 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1095 uint32_t flow_idx; /* Intermediate device flow index. */
1096 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1097 struct mlx5_flow_meter_policy *policy;
1098 /* The meter policy used by meter in flow. */
1099 struct mlx5_flow_meter_policy *final_policy;
1100 /* The final policy when meter policy is hierarchy. */
1101 uint32_t skip_matcher_reg:1;
1102 /* Indicates if need to skip matcher register in translate. */
1105 struct mlx5_flow_split_info {
1107 /**< True if flow is created by request external to PMD. */
1108 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1109 uint32_t flow_idx; /**< This memory pool index to the flow. */
1110 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1111 uint64_t prefix_layers; /**< Prefix subflow layers. */
1112 uint32_t table_id; /**< Flow table identifier. */
1115 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1116 const struct rte_flow_attr *attr,
1117 const struct rte_flow_item items[],
1118 const struct rte_flow_action actions[],
1121 struct rte_flow_error *error);
1122 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1123 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1124 const struct rte_flow_item items[],
1125 const struct rte_flow_action actions[], struct rte_flow_error *error);
1126 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1127 struct mlx5_flow *dev_flow,
1128 const struct rte_flow_attr *attr,
1129 const struct rte_flow_item items[],
1130 const struct rte_flow_action actions[],
1131 struct rte_flow_error *error);
1132 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1133 struct rte_flow_error *error);
1134 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1135 struct rte_flow *flow);
1136 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1137 struct rte_flow *flow);
1138 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1139 struct rte_flow *flow,
1140 const struct rte_flow_action *actions,
1142 struct rte_flow_error *error);
1143 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1144 struct mlx5_flow_meter_info *fm,
1146 uint8_t domain_bitmap);
1147 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1148 struct mlx5_flow_meter_info *fm);
1149 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1150 typedef struct mlx5_flow_meter_sub_policy *
1151 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1152 (struct rte_eth_dev *dev,
1153 struct mlx5_flow_meter_policy *mtr_policy,
1154 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1155 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t)
1156 (struct rte_eth_dev *dev,
1157 struct mlx5_flow_meter_info *fm,
1159 const struct rte_flow_item *item,
1160 struct rte_flow_error *error);
1161 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t)
1162 (struct rte_eth_dev *dev,
1163 struct mlx5_flow_meter_policy *mtr_policy);
1164 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1165 (struct rte_eth_dev *dev);
1166 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1168 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1169 (struct rte_eth_dev *dev);
1170 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1172 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1174 bool clear, uint64_t *pkts,
1176 typedef int (*mlx5_flow_get_aged_flows_t)
1177 (struct rte_eth_dev *dev,
1179 uint32_t nb_contexts,
1180 struct rte_flow_error *error);
1181 typedef int (*mlx5_flow_action_validate_t)
1182 (struct rte_eth_dev *dev,
1183 const struct rte_flow_indir_action_conf *conf,
1184 const struct rte_flow_action *action,
1185 struct rte_flow_error *error);
1186 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1187 (struct rte_eth_dev *dev,
1188 const struct rte_flow_indir_action_conf *conf,
1189 const struct rte_flow_action *action,
1190 struct rte_flow_error *error);
1191 typedef int (*mlx5_flow_action_destroy_t)
1192 (struct rte_eth_dev *dev,
1193 struct rte_flow_action_handle *action,
1194 struct rte_flow_error *error);
1195 typedef int (*mlx5_flow_action_update_t)
1196 (struct rte_eth_dev *dev,
1197 struct rte_flow_action_handle *action,
1199 struct rte_flow_error *error);
1200 typedef int (*mlx5_flow_action_query_t)
1201 (struct rte_eth_dev *dev,
1202 const struct rte_flow_action_handle *action,
1204 struct rte_flow_error *error);
1205 typedef int (*mlx5_flow_sync_domain_t)
1206 (struct rte_eth_dev *dev,
1209 typedef int (*mlx5_flow_validate_mtr_acts_t)
1210 (struct rte_eth_dev *dev,
1211 const struct rte_flow_action *actions[RTE_COLORS],
1212 struct rte_flow_attr *attr,
1214 uint8_t *domain_bitmap,
1215 uint8_t *policy_mode,
1216 struct rte_mtr_error *error);
1217 typedef int (*mlx5_flow_create_mtr_acts_t)
1218 (struct rte_eth_dev *dev,
1219 struct mlx5_flow_meter_policy *mtr_policy,
1220 const struct rte_flow_action *actions[RTE_COLORS],
1221 struct rte_mtr_error *error);
1222 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1223 (struct rte_eth_dev *dev,
1224 struct mlx5_flow_meter_policy *mtr_policy);
1225 typedef int (*mlx5_flow_create_policy_rules_t)
1226 (struct rte_eth_dev *dev,
1227 struct mlx5_flow_meter_policy *mtr_policy);
1228 typedef void (*mlx5_flow_destroy_policy_rules_t)
1229 (struct rte_eth_dev *dev,
1230 struct mlx5_flow_meter_policy *mtr_policy);
1231 typedef int (*mlx5_flow_create_def_policy_t)
1232 (struct rte_eth_dev *dev);
1233 typedef void (*mlx5_flow_destroy_def_policy_t)
1234 (struct rte_eth_dev *dev);
1235 typedef int (*mlx5_flow_discover_priorities_t)
1236 (struct rte_eth_dev *dev,
1237 const uint16_t *vprio, int vprio_n);
1239 struct mlx5_flow_driver_ops {
1240 mlx5_flow_validate_t validate;
1241 mlx5_flow_prepare_t prepare;
1242 mlx5_flow_translate_t translate;
1243 mlx5_flow_apply_t apply;
1244 mlx5_flow_remove_t remove;
1245 mlx5_flow_destroy_t destroy;
1246 mlx5_flow_query_t query;
1247 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1248 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1249 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1250 mlx5_flow_mtr_alloc_t create_meter;
1251 mlx5_flow_mtr_free_t free_meter;
1252 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1253 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1254 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1255 mlx5_flow_create_policy_rules_t create_policy_rules;
1256 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1257 mlx5_flow_create_def_policy_t create_def_policy;
1258 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1259 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1260 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create;
1261 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq;
1262 mlx5_flow_counter_alloc_t counter_alloc;
1263 mlx5_flow_counter_free_t counter_free;
1264 mlx5_flow_counter_query_t counter_query;
1265 mlx5_flow_get_aged_flows_t get_aged_flows;
1266 mlx5_flow_action_validate_t action_validate;
1267 mlx5_flow_action_create_t action_create;
1268 mlx5_flow_action_destroy_t action_destroy;
1269 mlx5_flow_action_update_t action_update;
1270 mlx5_flow_action_query_t action_query;
1271 mlx5_flow_sync_domain_t sync_domain;
1272 mlx5_flow_discover_priorities_t discover_priorities;
1277 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1279 struct flow_grp_info {
1280 uint64_t external:1;
1281 uint64_t transfer:1;
1282 uint64_t fdb_def_rule:1;
1283 /* force standard group translation */
1284 uint64_t std_tbl_fix:1;
1285 uint64_t skip_scale:2;
1289 tunnel_use_standard_attr_group_translate
1290 (const struct rte_eth_dev *dev,
1291 const struct rte_flow_attr *attr,
1292 const struct mlx5_flow_tunnel *tunnel,
1293 enum mlx5_tof_rule_type tof_rule_type)
1297 if (!is_tunnel_offload_active(dev))
1298 /* no tunnel offload API */
1302 * OvS will use jump to group 0 in tunnel steer rule.
1303 * If tunnel steer rule starts from group 0 (attr.group == 0)
1304 * that 0 group must be translated with standard method.
1305 * attr.group == 0 in tunnel match rule translated with tunnel
1308 verdict = !attr->group &&
1309 is_flow_tunnel_steer_rule(tof_rule_type);
1312 * non-tunnel group translation uses standard method for
1313 * root group only: attr.group == 0
1315 verdict = !attr->group;
1322 * Get DV flow aso meter by index.
1325 * Pointer to the Ethernet device structure.
1327 * mlx5 flow aso meter index in the container.
1329 * mlx5 flow aso meter pool in the container,
1332 * Pointer to the aso meter, NULL otherwise.
1334 static inline struct mlx5_aso_mtr *
1335 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1337 struct mlx5_aso_mtr_pool *pool;
1338 struct mlx5_aso_mtr_pools_mng *pools_mng =
1339 &priv->sh->mtrmng->pools_mng;
1341 /* Decrease to original index. */
1343 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1344 rte_rwlock_read_lock(&pools_mng->resize_mtrwl);
1345 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1346 rte_rwlock_read_unlock(&pools_mng->resize_mtrwl);
1347 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1350 static __rte_always_inline const struct rte_flow_item *
1351 mlx5_find_end_item(const struct rte_flow_item *item)
1353 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1357 static __rte_always_inline bool
1358 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1360 struct rte_flow_item_integrity test = *item;
1363 test.ipv4_csum_ok = 0;
1364 test.l4_csum_ok = 0;
1365 return (test.value == 0);
1369 * Get ASO CT action by device and index.
1372 * Pointer to the Ethernet device structure.
1374 * Index to the ASO CT action.
1377 * The specified ASO CT action pointer.
1379 static inline struct mlx5_aso_ct_action *
1380 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx)
1382 struct mlx5_priv *priv = dev->data->dev_private;
1383 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
1384 struct mlx5_aso_ct_pool *pool;
1387 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n);
1388 /* Bit operation AND could be used. */
1389 rte_rwlock_read_lock(&mng->resize_rwl);
1390 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL];
1391 rte_rwlock_read_unlock(&mng->resize_rwl);
1392 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];
1396 * Get ASO CT action by owner & index.
1399 * Pointer to the Ethernet device structure.
1401 * Index to the ASO CT action and owner port combination.
1404 * The specified ASO CT action pointer.
1406 static inline struct mlx5_aso_ct_action *
1407 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx)
1409 struct mlx5_priv *priv = dev->data->dev_private;
1410 struct mlx5_aso_ct_action *ct;
1411 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
1412 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
1414 if (owner == PORT_ID(priv)) {
1415 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
1417 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
1419 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
1420 if (dev->data->dev_started != 1)
1422 ct = flow_aso_ct_get_by_dev_idx(owndev, idx);
1423 if (ct->peer != PORT_ID(priv))
1429 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1430 const struct mlx5_flow_tunnel *tunnel,
1431 uint32_t group, uint32_t *table,
1432 const struct flow_grp_info *flags,
1433 struct rte_flow_error *error);
1434 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1435 int tunnel, uint64_t layer_types,
1436 uint64_t hash_fields);
1437 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1438 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1439 uint32_t subpriority);
1440 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1441 const struct rte_flow_attr *attr);
1442 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1443 const struct rte_flow_attr *attr,
1444 uint32_t subpriority, bool external);
1445 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1446 enum mlx5_feature_name feature,
1448 struct rte_flow_error *error);
1449 const struct rte_flow_action *mlx5_flow_find_action
1450 (const struct rte_flow_action *actions,
1451 enum rte_flow_action_type action);
1452 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1453 const struct rte_flow_action *action,
1454 struct rte_flow_error *error);
1455 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1456 const struct rte_flow_attr *attr,
1457 struct rte_flow_error *error);
1458 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1459 const struct rte_flow_attr *attr,
1460 struct rte_flow_error *error);
1461 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1462 const struct rte_flow_attr *attr,
1463 struct rte_flow_error *error);
1464 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1465 uint64_t action_flags,
1466 const struct rte_flow_attr *attr,
1467 struct rte_flow_error *error);
1468 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1469 uint64_t action_flags,
1470 struct rte_eth_dev *dev,
1471 const struct rte_flow_attr *attr,
1472 struct rte_flow_error *error);
1473 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1474 uint64_t action_flags,
1475 struct rte_eth_dev *dev,
1476 const struct rte_flow_attr *attr,
1477 uint64_t item_flags,
1478 struct rte_flow_error *error);
1479 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1480 const struct rte_flow_attr *attr,
1481 struct rte_flow_error *error);
1482 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1483 const struct rte_flow_attr *attributes,
1484 struct rte_flow_error *error);
1485 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1486 const uint8_t *mask,
1487 const uint8_t *nic_mask,
1489 bool range_accepted,
1490 struct rte_flow_error *error);
1491 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1492 uint64_t item_flags, bool ext_vlan_sup,
1493 struct rte_flow_error *error);
1494 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1495 uint64_t item_flags,
1496 uint8_t target_protocol,
1497 struct rte_flow_error *error);
1498 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1499 uint64_t item_flags,
1500 const struct rte_flow_item *gre_item,
1501 struct rte_flow_error *error);
1502 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1503 uint64_t item_flags,
1505 uint16_t ether_type,
1506 const struct rte_flow_item_ipv4 *acc_mask,
1507 bool range_accepted,
1508 struct rte_flow_error *error);
1509 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1510 uint64_t item_flags,
1512 uint16_t ether_type,
1513 const struct rte_flow_item_ipv6 *acc_mask,
1514 struct rte_flow_error *error);
1515 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1516 const struct rte_flow_item *item,
1517 uint64_t item_flags,
1518 uint64_t prev_layer,
1519 struct rte_flow_error *error);
1520 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1521 uint64_t item_flags,
1522 uint8_t target_protocol,
1523 const struct rte_flow_item_tcp *flow_mask,
1524 struct rte_flow_error *error);
1525 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1526 uint64_t item_flags,
1527 uint8_t target_protocol,
1528 struct rte_flow_error *error);
1529 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1530 uint64_t item_flags,
1531 struct rte_eth_dev *dev,
1532 struct rte_flow_error *error);
1533 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev,
1535 const struct rte_flow_item *item,
1536 uint64_t item_flags,
1537 const struct rte_flow_attr *attr,
1538 struct rte_flow_error *error);
1539 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1540 uint64_t item_flags,
1541 struct rte_eth_dev *dev,
1542 struct rte_flow_error *error);
1543 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1544 uint64_t item_flags,
1545 uint8_t target_protocol,
1546 struct rte_flow_error *error);
1547 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1548 uint64_t item_flags,
1549 uint8_t target_protocol,
1550 struct rte_flow_error *error);
1551 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1552 uint64_t item_flags,
1553 uint8_t target_protocol,
1554 struct rte_flow_error *error);
1555 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1556 uint64_t item_flags,
1557 struct rte_eth_dev *dev,
1558 struct rte_flow_error *error);
1559 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1561 const struct rte_flow_item *geneve_item,
1562 struct rte_eth_dev *dev,
1563 struct rte_flow_error *error);
1564 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1565 uint64_t item_flags,
1567 uint16_t ether_type,
1568 const struct rte_flow_item_ecpri *acc_mask,
1569 struct rte_flow_error *error);
1570 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1571 struct mlx5_flow_meter_info *fm,
1573 uint8_t domain_bitmap);
1574 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1575 struct mlx5_flow_meter_info *fm);
1576 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1577 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1578 (struct rte_eth_dev *dev,
1579 struct mlx5_flow_meter_policy *mtr_policy,
1580 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1581 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
1582 struct mlx5_flow_meter_policy *mtr_policy);
1583 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1584 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev);
1585 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1586 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1587 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1589 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx);
1590 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1592 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1593 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx,
1594 struct mlx5_list_entry *oentry,
1596 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1597 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1598 uint32_t table_level, uint8_t egress, uint8_t transfer,
1599 bool external, const struct mlx5_flow_tunnel *tunnel,
1600 uint32_t group_id, uint8_t dummy,
1601 uint32_t table_id, struct rte_flow_error *error);
1603 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx);
1604 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1606 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1607 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx,
1608 struct mlx5_list_entry *oentry,
1610 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1612 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1614 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx);
1615 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1616 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx,
1617 struct mlx5_list_entry *oentry,
1619 void flow_dv_modify_clone_free_cb(void *tool_ctx,
1620 struct mlx5_list_entry *entry);
1622 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx);
1623 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1625 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1626 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx,
1627 struct mlx5_list_entry *entry,
1629 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1631 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1633 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx,
1635 void flow_dv_encap_decap_remove_cb(void *tool_ctx,
1636 struct mlx5_list_entry *entry);
1637 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx,
1638 struct mlx5_list_entry *entry,
1640 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx,
1641 struct mlx5_list_entry *entry);
1643 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1645 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx);
1646 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1648 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1650 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx);
1651 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1652 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx,
1653 struct mlx5_list_entry *entry, void *cb_ctx);
1654 void flow_dv_port_id_clone_free_cb(void *tool_ctx,
1655 struct mlx5_list_entry *entry);
1657 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1659 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx,
1661 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1662 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx,
1663 struct mlx5_list_entry *entry, void *cb_ctx);
1664 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx,
1665 struct mlx5_list_entry *entry);
1667 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1669 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx);
1670 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1671 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx,
1672 struct mlx5_list_entry *entry, void *cb_ctx);
1673 void flow_dv_sample_clone_free_cb(void *tool_ctx,
1674 struct mlx5_list_entry *entry);
1676 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1678 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx,
1680 void flow_dv_dest_array_remove_cb(void *tool_ctx,
1681 struct mlx5_list_entry *entry);
1682 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx,
1683 struct mlx5_list_entry *entry, void *cb_ctx);
1684 void flow_dv_dest_array_clone_free_cb(void *tool_ctx,
1685 struct mlx5_list_entry *entry);
1686 int flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
1687 void **action, struct rte_flow_error *error);
1689 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
1690 struct rte_flow_error *error);
1692 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1694 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1695 const struct rte_flow_item *item,
1696 struct rte_flow_error *error);
1697 void flow_release_workspace(void *data);
1698 int mlx5_flow_os_init_workspace_once(void);
1699 void *mlx5_flow_os_get_specific_workspace(void);
1700 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1701 void mlx5_flow_os_release_workspace(void);
1702 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1703 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1704 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1705 const struct rte_flow_action *actions[RTE_COLORS],
1706 struct rte_flow_attr *attr,
1708 uint8_t *domain_bitmap,
1709 uint8_t *policy_mode,
1710 struct rte_mtr_error *error);
1711 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1712 struct mlx5_flow_meter_policy *mtr_policy);
1713 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1714 struct mlx5_flow_meter_policy *mtr_policy,
1715 const struct rte_flow_action *actions[RTE_COLORS],
1716 struct rte_mtr_error *error);
1717 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1718 struct mlx5_flow_meter_policy *mtr_policy);
1719 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1720 struct mlx5_flow_meter_policy *mtr_policy);
1721 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1722 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1723 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1724 struct mlx5_flow_handle *dev_handle);
1725 const struct mlx5_flow_tunnel *
1726 mlx5_get_tof(const struct rte_flow_item *items,
1727 const struct rte_flow_action *actions,
1728 enum mlx5_tof_rule_type *rule_type);
1731 #endif /* RTE_PMD_MLX5_FLOW_H_ */