1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* Private rte flow items. */
22 enum mlx5_rte_flow_item_type {
23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
24 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
30 /* Private (internal) rte flow actions. */
31 enum mlx5_rte_flow_action_type {
32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
34 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
38 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
41 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
44 MLX5_INDIRECT_ACTION_TYPE_RSS,
45 MLX5_INDIRECT_ACTION_TYPE_AGE,
48 /* Matches on selected register. */
49 struct mlx5_rte_flow_item_tag {
54 /* Modify selected register. */
55 struct mlx5_rte_flow_action_set_tag {
62 struct mlx5_flow_action_copy_mreg {
67 /* Matches on source queue. */
68 struct mlx5_rte_flow_item_tx_queue {
72 /* Feature name to allocate metadata register. */
73 enum mlx5_feature_name {
87 /* Default queue number. */
88 #define MLX5_RSSQ_DEFAULT_NUM 16
90 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
91 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
92 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
93 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
94 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
95 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
97 /* Pattern inner Layer bits. */
98 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
99 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
100 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
101 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
102 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
103 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
105 /* Pattern tunnel Layer bits. */
106 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
107 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
108 #define MLX5_FLOW_LAYER_GRE (1u << 14)
109 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
110 /* List of tunnel Layer bits continued below. */
112 /* General pattern items bits. */
113 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
114 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
115 #define MLX5_FLOW_ITEM_TAG (1u << 18)
116 #define MLX5_FLOW_ITEM_MARK (1u << 19)
118 /* Pattern MISC bits. */
119 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
120 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
121 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
123 /* Pattern tunnel Layer bits (continued). */
124 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
125 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
126 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
127 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
130 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
132 /* Pattern tunnel Layer bits (continued). */
133 #define MLX5_FLOW_LAYER_GTP (1u << 28)
135 /* Pattern eCPRI Layer bit. */
136 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
138 /* IPv6 Fragment Extension Header bit. */
139 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
140 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
142 /* Pattern tunnel Layer bits (continued). */
143 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
144 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
147 #define MLX5_FLOW_LAYER_OUTER_L3 \
148 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
149 #define MLX5_FLOW_LAYER_OUTER_L4 \
150 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
151 #define MLX5_FLOW_LAYER_OUTER \
152 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
153 MLX5_FLOW_LAYER_OUTER_L4)
156 #define MLX5_FLOW_LAYER_TUNNEL \
157 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
158 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
159 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
160 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
163 #define MLX5_FLOW_LAYER_INNER_L3 \
164 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
165 #define MLX5_FLOW_LAYER_INNER_L4 \
166 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
167 #define MLX5_FLOW_LAYER_INNER \
168 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
169 MLX5_FLOW_LAYER_INNER_L4)
172 #define MLX5_FLOW_LAYER_L2 \
173 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
174 #define MLX5_FLOW_LAYER_L3_IPV4 \
175 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
176 #define MLX5_FLOW_LAYER_L3_IPV6 \
177 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
178 #define MLX5_FLOW_LAYER_L3 \
179 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
180 #define MLX5_FLOW_LAYER_L4 \
181 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
184 #define MLX5_FLOW_ACTION_DROP (1u << 0)
185 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
186 #define MLX5_FLOW_ACTION_RSS (1u << 2)
187 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
188 #define MLX5_FLOW_ACTION_MARK (1u << 4)
189 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
190 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
191 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
192 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
193 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
194 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
195 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
196 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
197 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
198 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
199 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
200 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
201 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
202 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
203 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
204 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
205 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
206 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
207 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
208 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
209 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
210 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
211 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
212 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
213 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
214 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
215 #define MLX5_FLOW_ACTION_METER (1ull << 31)
216 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
217 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
218 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
219 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
220 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
221 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
222 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
223 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
224 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
226 #define MLX5_FLOW_FATE_ACTIONS \
227 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
228 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
229 MLX5_FLOW_ACTION_DEFAULT_MISS | \
230 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
232 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
233 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
234 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
236 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
237 MLX5_FLOW_ACTION_SET_IPV4_DST | \
238 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
239 MLX5_FLOW_ACTION_SET_IPV6_DST | \
240 MLX5_FLOW_ACTION_SET_TP_SRC | \
241 MLX5_FLOW_ACTION_SET_TP_DST | \
242 MLX5_FLOW_ACTION_SET_TTL | \
243 MLX5_FLOW_ACTION_DEC_TTL | \
244 MLX5_FLOW_ACTION_SET_MAC_SRC | \
245 MLX5_FLOW_ACTION_SET_MAC_DST | \
246 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
247 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
248 MLX5_FLOW_ACTION_INC_TCP_ACK | \
249 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
250 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
251 MLX5_FLOW_ACTION_SET_TAG | \
252 MLX5_FLOW_ACTION_MARK_EXT | \
253 MLX5_FLOW_ACTION_SET_META | \
254 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
255 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
256 MLX5_FLOW_ACTION_MODIFY_FIELD)
258 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
259 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
261 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
264 #define IPPROTO_MPLS 137
267 /* UDP port number for MPLS */
268 #define MLX5_UDP_PORT_MPLS 6635
270 /* UDP port numbers for VxLAN. */
271 #define MLX5_UDP_PORT_VXLAN 4789
272 #define MLX5_UDP_PORT_VXLAN_GPE 4790
274 /* UDP port numbers for GENEVE. */
275 #define MLX5_UDP_PORT_GENEVE 6081
277 /* Lowest priority indicator. */
278 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
281 * Max priority for ingress\egress flow groups
282 * greater than 0 and for any transfer flow group.
283 * From user configation: 0 - 21843.
285 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
288 * Number of sub priorities.
289 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
290 * matching on the NIC (firmware dependent) L4 most have the higher priority
291 * followed by L3 and ending with L2.
293 #define MLX5_PRIORITY_MAP_L2 2
294 #define MLX5_PRIORITY_MAP_L3 1
295 #define MLX5_PRIORITY_MAP_L4 0
296 #define MLX5_PRIORITY_MAP_MAX 3
298 /* Valid layer type for IPV4 RSS. */
299 #define MLX5_IPV4_LAYER_TYPES \
300 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
301 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
302 ETH_RSS_NONFRAG_IPV4_OTHER)
304 /* IBV hash source bits for IPV4. */
305 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
307 /* Valid layer type for IPV6 RSS. */
308 #define MLX5_IPV6_LAYER_TYPES \
309 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
310 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
311 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
313 /* IBV hash source bits for IPV6. */
314 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
316 /* IBV hash bits for L3 SRC. */
317 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
319 /* IBV hash bits for L3 DST. */
320 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
322 /* IBV hash bits for TCP. */
323 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
324 IBV_RX_HASH_DST_PORT_TCP)
326 /* IBV hash bits for UDP. */
327 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
328 IBV_RX_HASH_DST_PORT_UDP)
330 /* IBV hash bits for L4 SRC. */
331 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
332 IBV_RX_HASH_SRC_PORT_UDP)
334 /* IBV hash bits for L4 DST. */
335 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
336 IBV_RX_HASH_DST_PORT_UDP)
338 /* Geneve header first 16Bit */
339 #define MLX5_GENEVE_VER_MASK 0x3
340 #define MLX5_GENEVE_VER_SHIFT 14
341 #define MLX5_GENEVE_VER_VAL(a) \
342 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
343 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
344 #define MLX5_GENEVE_OPTLEN_SHIFT 8
345 #define MLX5_GENEVE_OPTLEN_VAL(a) \
346 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
347 #define MLX5_GENEVE_OAMF_MASK 0x1
348 #define MLX5_GENEVE_OAMF_SHIFT 7
349 #define MLX5_GENEVE_OAMF_VAL(a) \
350 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
351 #define MLX5_GENEVE_CRITO_MASK 0x1
352 #define MLX5_GENEVE_CRITO_SHIFT 6
353 #define MLX5_GENEVE_CRITO_VAL(a) \
354 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
355 #define MLX5_GENEVE_RSVD_MASK 0x3F
356 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
358 * The length of the Geneve options fields, expressed in four byte multiples,
359 * not including the eight byte fixed tunnel.
361 #define MLX5_GENEVE_OPT_LEN_0 14
362 #define MLX5_GENEVE_OPT_LEN_1 63
364 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
365 sizeof(struct rte_ipv4_hdr))
366 /* GTP extension header flag. */
367 #define MLX5_GTP_EXT_HEADER_FLAG 4
369 /* GTP extension header max PDU type value. */
370 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
372 /* GTP extension header PDU type shift. */
373 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
375 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
376 #define MLX5_IPV4_FRAG_OFFSET_MASK \
377 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
379 /* Specific item's fields can accept a range of values (using spec and last). */
380 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
381 #define MLX5_ITEM_RANGE_ACCEPTED true
383 /* Software header modify action numbers of a flow. */
384 #define MLX5_ACT_NUM_MDF_IPV4 1
385 #define MLX5_ACT_NUM_MDF_IPV6 4
386 #define MLX5_ACT_NUM_MDF_MAC 2
387 #define MLX5_ACT_NUM_MDF_VID 1
388 #define MLX5_ACT_NUM_MDF_PORT 2
389 #define MLX5_ACT_NUM_MDF_TTL 1
390 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
391 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
392 #define MLX5_ACT_NUM_MDF_TCPACK 1
393 #define MLX5_ACT_NUM_SET_REG 1
394 #define MLX5_ACT_NUM_SET_TAG 1
395 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
396 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
397 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
398 #define MLX5_ACT_NUM_SET_DSCP 1
400 /* Maximum number of fields to modify in MODIFY_FIELD */
401 #define MLX5_ACT_MAX_MOD_FIELDS 5
403 enum mlx5_flow_drv_type {
406 MLX5_FLOW_TYPE_VERBS,
410 /* Fate action type. */
411 enum mlx5_flow_fate_type {
412 MLX5_FLOW_FATE_NONE, /* Egress flow. */
413 MLX5_FLOW_FATE_QUEUE,
415 MLX5_FLOW_FATE_PORT_ID,
417 MLX5_FLOW_FATE_DEFAULT_MISS,
418 MLX5_FLOW_FATE_SHARED_RSS,
422 /* Matcher PRM representation */
423 struct mlx5_flow_dv_match_params {
425 /**< Size of match value. Do NOT split size and key! */
426 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
427 /**< Matcher value. This value is used as the mask or as a key. */
430 /* Matcher structure. */
431 struct mlx5_flow_dv_matcher {
432 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
433 struct mlx5_flow_tbl_resource *tbl;
434 /**< Pointer to the table(group) the matcher associated with. */
435 void *matcher_object; /**< Pointer to DV matcher */
436 uint16_t crc; /**< CRC of key. */
437 uint16_t priority; /**< Priority of matcher. */
438 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
441 #define MLX5_ENCAP_MAX_LEN 132
443 /* Encap/decap resource structure. */
444 struct mlx5_flow_dv_encap_decap_resource {
445 struct mlx5_hlist_entry entry;
446 /* Pointer to next element. */
447 uint32_t refcnt; /**< Reference counter. */
449 /**< Encap/decap action object. */
450 uint8_t buf[MLX5_ENCAP_MAX_LEN];
452 uint8_t reformat_type;
454 uint64_t flags; /**< Flags for RDMA API. */
455 uint32_t idx; /**< Index for the index memory pool. */
458 /* Tag resource structure. */
459 struct mlx5_flow_dv_tag_resource {
460 struct mlx5_hlist_entry entry;
461 /**< hash list entry for tag resource, tag value as the key. */
463 /**< Tag action object. */
464 uint32_t refcnt; /**< Reference counter. */
465 uint32_t idx; /**< Index for the index memory pool. */
466 uint32_t tag_id; /**< Tag ID. */
470 * Number of modification commands.
471 * The maximal actions amount in FW is some constant, and it is 16 in the
472 * latest releases. In some old releases, it will be limited to 8.
473 * Since there is no interface to query the capacity, the maximal value should
474 * be used to allow PMD to create the flow. The validation will be done in the
475 * lower driver layer or FW. A failure will be returned if exceeds the maximal
476 * supported actions number on the root table.
477 * On non-root tables, there is no limitation, but 32 is enough right now.
479 #define MLX5_MAX_MODIFY_NUM 32
480 #define MLX5_ROOT_TBL_MODIFY_NUM 16
482 /* Modify resource structure */
483 struct mlx5_flow_dv_modify_hdr_resource {
484 struct mlx5_hlist_entry entry;
485 void *action; /**< Modify header action object. */
486 /* Key area for hash list matching: */
487 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
488 uint32_t actions_num; /**< Number of modification actions. */
489 uint64_t flags; /**< Flags for RDMA API. */
490 struct mlx5_modification_cmd actions[];
491 /**< Modification actions. */
494 /* Modify resource key of the hash organization. */
495 union mlx5_flow_modify_hdr_key {
497 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
498 uint32_t actions_num:5; /**< Number of modification actions. */
499 uint32_t group:19; /**< Flow group id. */
500 uint32_t cksum; /**< Actions check sum. */
502 uint64_t v64; /**< full 64bits value of key */
505 /* Jump action resource structure. */
506 struct mlx5_flow_dv_jump_tbl_resource {
507 void *action; /**< Pointer to the rdma core action. */
510 /* Port ID resource structure. */
511 struct mlx5_flow_dv_port_id_action_resource {
512 struct mlx5_cache_entry entry;
513 void *action; /**< Action object. */
514 uint32_t port_id; /**< Port ID value. */
515 uint32_t idx; /**< Indexed pool memory index. */
518 /* Push VLAN action resource structure */
519 struct mlx5_flow_dv_push_vlan_action_resource {
520 struct mlx5_cache_entry entry; /* Cache entry. */
521 void *action; /**< Action object. */
522 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
523 rte_be32_t vlan_tag; /**< VLAN tag value. */
524 uint32_t idx; /**< Indexed pool memory index. */
527 /* Metadata register copy table entry. */
528 struct mlx5_flow_mreg_copy_resource {
530 * Hash list entry for copy table.
531 * - Key is 32/64-bit MARK action ID.
532 * - MUST be the first entry.
534 struct mlx5_hlist_entry hlist_ent;
535 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
536 /* List entry for device flows. */
538 uint32_t rix_flow; /* Built flow for copy. */
542 /* Table tunnel parameter. */
543 struct mlx5_flow_tbl_tunnel_prm {
544 const struct mlx5_flow_tunnel *tunnel;
549 /* Table data structure of the hash organization. */
550 struct mlx5_flow_tbl_data_entry {
551 struct mlx5_hlist_entry entry;
552 /**< hash list entry, 64-bits key inside. */
553 struct mlx5_flow_tbl_resource tbl;
554 /**< flow table resource. */
555 struct mlx5_cache_list matchers;
556 /**< matchers' header associated with the flow table. */
557 struct mlx5_flow_dv_jump_tbl_resource jump;
558 /**< jump resource, at most one for each table created. */
559 uint32_t idx; /**< index for the indexed mempool. */
560 /**< tunnel offload */
561 const struct mlx5_flow_tunnel *tunnel;
564 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
565 uint32_t is_egress:1; /**< Egress table. */
566 uint32_t is_transfer:1; /**< Transfer table. */
567 uint32_t dummy:1; /**< DR table. */
568 uint32_t id:22; /**< Table ID. */
569 uint32_t reserve:5; /**< Reserved to future using. */
570 uint32_t level; /**< Table level. */
573 /* Sub rdma-core actions list. */
574 struct mlx5_flow_sub_actions_list {
575 uint32_t actions_num; /**< Number of sample actions. */
576 uint64_t action_flags;
577 void *dr_queue_action;
580 void *dr_port_id_action;
581 void *dr_encap_action;
582 void *dr_jump_action;
585 /* Sample sub-actions resource list. */
586 struct mlx5_flow_sub_actions_idx {
587 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
588 uint32_t rix_tag; /**< Index to the tag action. */
589 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
590 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
591 uint32_t rix_jump; /**< Index to the jump action resource. */
594 /* Sample action resource structure. */
595 struct mlx5_flow_dv_sample_resource {
596 struct mlx5_cache_entry entry; /**< Cache entry. */
598 void *verbs_action; /**< Verbs sample action object. */
599 void **sub_actions; /**< Sample sub-action array. */
601 struct rte_eth_dev *dev; /**< Device registers the action. */
602 uint32_t idx; /** Sample object index. */
603 uint8_t ft_type; /** Flow Table Type */
604 uint32_t ft_id; /** Flow Table Level */
605 uint32_t ratio; /** Sample Ratio */
606 uint64_t set_action; /** Restore reg_c0 value */
607 void *normal_path_tbl; /** Flow Table pointer */
608 struct mlx5_flow_sub_actions_idx sample_idx;
609 /**< Action index resources. */
610 struct mlx5_flow_sub_actions_list sample_act;
611 /**< Action resources. */
614 #define MLX5_MAX_DEST_NUM 2
616 /* Destination array action resource structure. */
617 struct mlx5_flow_dv_dest_array_resource {
618 struct mlx5_cache_entry entry; /**< Cache entry. */
619 uint32_t idx; /** Destination array action object index. */
620 uint8_t ft_type; /** Flow Table Type */
621 uint8_t num_of_dest; /**< Number of destination actions. */
622 struct rte_eth_dev *dev; /**< Device registers the action. */
623 void *action; /**< Pointer to the rdma core action. */
624 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
625 /**< Action index resources. */
626 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
627 /**< Action resources. */
630 /* PMD flow priority for tunnel */
631 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
632 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
635 /** Device flow handle structure for DV mode only. */
636 struct mlx5_flow_handle_dv {
638 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
639 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
640 /**< Pointer to modify header resource in cache. */
641 uint32_t rix_encap_decap;
642 /**< Index to encap/decap resource in cache. */
643 uint32_t rix_push_vlan;
644 /**< Index to push VLAN action resource in cache. */
646 /**< Index to the tag action. */
648 /**< Index to sample action resource in cache. */
649 uint32_t rix_dest_array;
650 /**< Index to destination array resource in cache. */
653 /** Device flow handle structure: used both for creating & destroying. */
654 struct mlx5_flow_handle {
655 SILIST_ENTRY(uint32_t)next;
656 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
657 /**< Index to next device flow handle. */
659 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
660 void *drv_flow; /**< pointer to driver flow object. */
661 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
662 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
663 uint32_t mark:1; /**< Metadate rxq mark flag. */
664 uint32_t fate_action:3; /**< Fate action type. */
666 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
667 uint32_t rix_jump; /**< Index to the jump action resource. */
668 uint32_t rix_port_id_action;
669 /**< Index to port ID action resource. */
671 /**< Generic value indicates the fate action. */
672 uint32_t rix_default_fate;
673 /**< Indicates default miss fate action. */
675 /**< Indicates shared RSS fate action. */
677 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
678 struct mlx5_flow_handle_dv dvh;
683 * Size for Verbs device flow handle structure only. Do not use the DV only
684 * structure in Verbs. No DV flows attributes will be accessed.
685 * Macro offsetof() could also be used here.
687 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
688 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
689 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
691 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
694 /** Device flow structure only for DV flow creation. */
695 struct mlx5_flow_dv_workspace {
696 uint32_t group; /**< The group index. */
697 uint32_t table_id; /**< Flow table identifier. */
698 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
699 int actions_n; /**< number of actions. */
700 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
701 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
702 /**< Pointer to encap/decap resource in cache. */
703 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
704 /**< Pointer to push VLAN action resource in cache. */
705 struct mlx5_flow_dv_tag_resource *tag_resource;
706 /**< pointer to the tag action. */
707 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
708 /**< Pointer to port ID action resource. */
709 struct mlx5_flow_dv_jump_tbl_resource *jump;
710 /**< Pointer to the jump action resource. */
711 struct mlx5_flow_dv_match_params value;
712 /**< Holds the value that the packet is compared to. */
713 struct mlx5_flow_dv_sample_resource *sample_res;
714 /**< Pointer to the sample action resource. */
715 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
716 /**< Pointer to the destination array resource. */
719 #ifdef HAVE_INFINIBAND_VERBS_H
721 * Maximal Verbs flow specifications & actions size.
722 * Some elements are mutually exclusive, but enough space should be allocated.
723 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
724 * 2. One tunnel header (exception: GRE + MPLS),
725 * SPEC length: GRE == tunnel.
726 * Actions: 1. 1 Mark OR Flag.
727 * 2. 1 Drop (if any).
728 * 3. No limitation for counters, but it makes no sense to support too
729 * many counters in a single device flow.
731 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
732 #define MLX5_VERBS_MAX_SPEC_SIZE \
734 (2 * (sizeof(struct ibv_flow_spec_eth) + \
735 sizeof(struct ibv_flow_spec_ipv6) + \
736 sizeof(struct ibv_flow_spec_tcp_udp)) + \
737 sizeof(struct ibv_flow_spec_gre) + \
738 sizeof(struct ibv_flow_spec_mpls)) \
741 #define MLX5_VERBS_MAX_SPEC_SIZE \
743 (2 * (sizeof(struct ibv_flow_spec_eth) + \
744 sizeof(struct ibv_flow_spec_ipv6) + \
745 sizeof(struct ibv_flow_spec_tcp_udp)) + \
746 sizeof(struct ibv_flow_spec_tunnel)) \
750 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
751 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
752 #define MLX5_VERBS_MAX_ACT_SIZE \
754 sizeof(struct ibv_flow_spec_action_tag) + \
755 sizeof(struct ibv_flow_spec_action_drop) + \
756 sizeof(struct ibv_flow_spec_counter_action) * 4 \
759 #define MLX5_VERBS_MAX_ACT_SIZE \
761 sizeof(struct ibv_flow_spec_action_tag) + \
762 sizeof(struct ibv_flow_spec_action_drop) \
766 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
767 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
769 /** Device flow structure only for Verbs flow creation. */
770 struct mlx5_flow_verbs_workspace {
771 unsigned int size; /**< Size of the attribute. */
772 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
773 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
774 /**< Specifications & actions buffer of verbs flow. */
776 #endif /* HAVE_INFINIBAND_VERBS_H */
778 #define MLX5_SCALE_FLOW_GROUP_BIT 0
779 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
781 /** Maximal number of device sub-flows supported. */
782 #define MLX5_NUM_MAX_DEV_FLOWS 32
784 /** Device flow structure. */
787 struct rte_flow *flow; /**< Pointer to the main flow. */
788 uint32_t flow_idx; /**< The memory pool index to the main flow. */
789 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
791 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
792 bool external; /**< true if the flow is created external to PMD. */
793 uint8_t ingress:1; /**< 1 if the flow is ingress. */
794 uint8_t skip_scale:2;
796 * Each Bit be set to 1 if Skip the scale the flow group with factor.
797 * If bit0 be set to 1, then skip the scale the original flow group;
798 * If bit1 be set to 1, then skip the scale the jump flow group if
799 * having jump action.
800 * 00: Enable scale in a flow, default value.
801 * 01: Skip scale the flow group with factor, enable scale the group
803 * 10: Enable scale the group with factor, skip scale the group of
805 * 11: Skip scale the table with factor both for flow group and jump
809 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
810 struct mlx5_flow_dv_workspace dv;
812 #ifdef HAVE_INFINIBAND_VERBS_H
813 struct mlx5_flow_verbs_workspace verbs;
816 struct mlx5_flow_handle *handle;
817 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
818 const struct mlx5_flow_tunnel *tunnel;
821 /* Flow meter state. */
822 #define MLX5_FLOW_METER_DISABLE 0
823 #define MLX5_FLOW_METER_ENABLE 1
825 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
826 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
828 #define MLX5_MAN_WIDTH 8
829 /* Legacy Meter parameter structure. */
830 struct mlx5_legacy_flow_meter {
831 struct mlx5_flow_meter_info fm;
832 /* Must be the first in struct. */
833 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
834 /**< Pointer to the next flow meter structure. */
836 /* Index to meter object. */
839 #define MLX5_MAX_TUNNELS 256
840 #define MLX5_TNL_MISS_RULE_PRIORITY 3
841 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
844 * When tunnel offload is active, all JUMP group ids are converted
845 * using the same method. That conversion is applied both to tunnel and
846 * regular rule types.
847 * Group ids used in tunnel rules are relative to it's tunnel (!).
848 * Application can create number of steer rules, using the same
849 * tunnel, with different group id in each rule.
850 * Each tunnel stores its groups internally in PMD tunnel object.
851 * Groups used in regular rules do not belong to any tunnel and are stored
855 struct mlx5_flow_tunnel {
856 LIST_ENTRY(mlx5_flow_tunnel) chain;
857 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
858 uint32_t tunnel_id; /** unique tunnel ID */
860 struct rte_flow_action action;
861 struct rte_flow_item item;
862 struct mlx5_hlist *groups; /** tunnel groups */
865 /** PMD tunnel related context */
866 struct mlx5_flow_tunnel_hub {
868 * Access to the list MUST be MT protected
870 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
871 /* protect access to the tunnels list */
873 struct mlx5_hlist *groups; /** non tunnel groups */
876 /* convert jump group to flow table ID in tunnel rules */
877 struct tunnel_tbl_entry {
878 struct mlx5_hlist_entry hash;
884 static inline uint32_t
885 tunnel_id_to_flow_tbl(uint32_t id)
887 return id | (1u << 16);
890 static inline uint32_t
891 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
893 return flow_tbl & ~(1u << 16);
896 union tunnel_tbl_key {
904 static inline struct mlx5_flow_tunnel_hub *
905 mlx5_tunnel_hub(struct rte_eth_dev *dev)
907 struct mlx5_priv *priv = dev->data->dev_private;
908 return priv->sh->tunnel_hub;
912 is_tunnel_offload_active(struct rte_eth_dev *dev)
914 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
915 struct mlx5_priv *priv = dev->data->dev_private;
916 return !!priv->config.dv_miss_info;
924 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
925 __rte_unused const struct rte_flow_attr *attr,
926 __rte_unused const struct rte_flow_item items[],
927 __rte_unused const struct rte_flow_action actions[])
929 return (items[0].type == (typeof(items[0].type))
930 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
934 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
935 __rte_unused const struct rte_flow_attr *attr,
936 __rte_unused const struct rte_flow_item items[],
937 __rte_unused const struct rte_flow_action actions[])
939 return (actions[0].type == (typeof(actions[0].type))
940 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
943 static inline const struct mlx5_flow_tunnel *
944 flow_actions_to_tunnel(const struct rte_flow_action actions[])
946 return actions[0].conf;
949 static inline const struct mlx5_flow_tunnel *
950 flow_items_to_tunnel(const struct rte_flow_item items[])
952 return items[0].spec;
955 /* Flow structure. */
957 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
958 uint32_t dev_handles;
959 /**< Device flow handles that are part of the flow. */
960 uint32_t drv_type:2; /**< Driver type. */
962 uint32_t meter:24; /**< Holds flow meter id. */
963 uint32_t rix_mreg_copy;
964 /**< Index to metadata register copy table resource. */
965 uint32_t counter; /**< Holds flow counter. */
966 uint32_t tunnel_id; /**< Tunnel id */
967 uint32_t age; /**< Holds ASO age bit index. */
968 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
972 * Define list of valid combinations of RX Hash fields
973 * (see enum ibv_rx_hash_fields).
975 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
976 #define MLX5_RSS_HASH_IPV4_TCP \
977 (MLX5_RSS_HASH_IPV4 | \
978 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
979 #define MLX5_RSS_HASH_IPV4_UDP \
980 (MLX5_RSS_HASH_IPV4 | \
981 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
982 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
983 #define MLX5_RSS_HASH_IPV6_TCP \
984 (MLX5_RSS_HASH_IPV6 | \
985 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
986 #define MLX5_RSS_HASH_IPV6_UDP \
987 (MLX5_RSS_HASH_IPV6 | \
988 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
989 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
990 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
991 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
992 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
993 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
994 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
995 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
996 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
997 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
998 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
999 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1000 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1001 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1002 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1003 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1004 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1005 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1006 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1007 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1008 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1009 #define MLX5_RSS_HASH_NONE 0ULL
1011 /* array of valid combinations of RX Hash fields for RSS */
1012 static const uint64_t mlx5_rss_hash_fields[] = {
1014 MLX5_RSS_HASH_IPV4_TCP,
1015 MLX5_RSS_HASH_IPV4_UDP,
1017 MLX5_RSS_HASH_IPV6_TCP,
1018 MLX5_RSS_HASH_IPV6_UDP,
1022 /* Shared RSS action structure */
1023 struct mlx5_shared_action_rss {
1024 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1025 uint32_t refcnt; /**< Atomically accessed refcnt. */
1026 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1027 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1028 struct mlx5_ind_table_obj *ind_tbl;
1029 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1030 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1031 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1032 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1035 struct rte_flow_action_handle {
1039 /* Thread specific flow workspace intermediate data. */
1040 struct mlx5_flow_workspace {
1041 /* If creating another flow in same thread, push new as stack. */
1042 struct mlx5_flow_workspace *prev;
1043 struct mlx5_flow_workspace *next;
1044 uint32_t inuse; /* can't create new flow with current. */
1045 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1046 struct mlx5_flow_rss_desc rss_desc;
1047 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1048 uint32_t flow_idx; /* Intermediate device flow index. */
1049 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1052 struct mlx5_flow_split_info {
1054 /**< True if flow is created by request external to PMD. */
1055 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1056 uint32_t flow_idx; /**< This memory pool index to the flow. */
1057 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1058 uint64_t prefix_layers; /**< Prefix subflow layers. */
1059 uint32_t table_id; /**< Flow table identifier. */
1062 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1063 const struct rte_flow_attr *attr,
1064 const struct rte_flow_item items[],
1065 const struct rte_flow_action actions[],
1068 struct rte_flow_error *error);
1069 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1070 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1071 const struct rte_flow_item items[],
1072 const struct rte_flow_action actions[], struct rte_flow_error *error);
1073 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1074 struct mlx5_flow *dev_flow,
1075 const struct rte_flow_attr *attr,
1076 const struct rte_flow_item items[],
1077 const struct rte_flow_action actions[],
1078 struct rte_flow_error *error);
1079 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1080 struct rte_flow_error *error);
1081 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1082 struct rte_flow *flow);
1083 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1084 struct rte_flow *flow);
1085 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1086 struct rte_flow *flow,
1087 const struct rte_flow_action *actions,
1089 struct rte_flow_error *error);
1090 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1091 struct mlx5_flow_meter_info *fm,
1093 uint8_t domain_bitmap);
1094 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1095 struct mlx5_flow_meter_info *fm);
1096 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1097 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1098 (struct rte_eth_dev *dev);
1099 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1101 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1102 (struct rte_eth_dev *dev);
1103 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1105 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1107 bool clear, uint64_t *pkts,
1109 typedef int (*mlx5_flow_get_aged_flows_t)
1110 (struct rte_eth_dev *dev,
1112 uint32_t nb_contexts,
1113 struct rte_flow_error *error);
1114 typedef int (*mlx5_flow_action_validate_t)
1115 (struct rte_eth_dev *dev,
1116 const struct rte_flow_indir_action_conf *conf,
1117 const struct rte_flow_action *action,
1118 struct rte_flow_error *error);
1119 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1120 (struct rte_eth_dev *dev,
1121 const struct rte_flow_indir_action_conf *conf,
1122 const struct rte_flow_action *action,
1123 struct rte_flow_error *error);
1124 typedef int (*mlx5_flow_action_destroy_t)
1125 (struct rte_eth_dev *dev,
1126 struct rte_flow_action_handle *action,
1127 struct rte_flow_error *error);
1128 typedef int (*mlx5_flow_action_update_t)
1129 (struct rte_eth_dev *dev,
1130 struct rte_flow_action_handle *action,
1132 struct rte_flow_error *error);
1133 typedef int (*mlx5_flow_action_query_t)
1134 (struct rte_eth_dev *dev,
1135 const struct rte_flow_action_handle *action,
1137 struct rte_flow_error *error);
1138 typedef int (*mlx5_flow_sync_domain_t)
1139 (struct rte_eth_dev *dev,
1142 typedef int (*mlx5_flow_validate_mtr_acts_t)
1143 (struct rte_eth_dev *dev,
1144 const struct rte_flow_action *actions[RTE_COLORS],
1145 struct rte_flow_attr *attr,
1147 uint8_t *domain_bitmap,
1148 bool *is_def_policy,
1149 struct rte_mtr_error *error);
1150 typedef int (*mlx5_flow_create_mtr_acts_t)
1151 (struct rte_eth_dev *dev,
1152 struct mlx5_flow_meter_policy *mtr_policy,
1153 const struct rte_flow_action *actions[RTE_COLORS],
1154 struct rte_mtr_error *error);
1155 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1156 (struct rte_eth_dev *dev,
1157 struct mlx5_flow_meter_policy *mtr_policy);
1158 typedef int (*mlx5_flow_create_policy_rules_t)
1159 (struct rte_eth_dev *dev,
1160 struct mlx5_flow_meter_policy *mtr_policy);
1161 typedef void (*mlx5_flow_destroy_policy_rules_t)
1162 (struct rte_eth_dev *dev,
1163 struct mlx5_flow_meter_policy *mtr_policy);
1164 typedef int (*mlx5_flow_create_def_policy_t)
1165 (struct rte_eth_dev *dev);
1166 typedef void (*mlx5_flow_destroy_def_policy_t)
1167 (struct rte_eth_dev *dev);
1169 struct mlx5_flow_driver_ops {
1170 mlx5_flow_validate_t validate;
1171 mlx5_flow_prepare_t prepare;
1172 mlx5_flow_translate_t translate;
1173 mlx5_flow_apply_t apply;
1174 mlx5_flow_remove_t remove;
1175 mlx5_flow_destroy_t destroy;
1176 mlx5_flow_query_t query;
1177 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1178 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1179 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1180 mlx5_flow_mtr_alloc_t create_meter;
1181 mlx5_flow_mtr_free_t free_meter;
1182 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1183 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1184 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1185 mlx5_flow_create_policy_rules_t create_policy_rules;
1186 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1187 mlx5_flow_create_def_policy_t create_def_policy;
1188 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1189 mlx5_flow_counter_alloc_t counter_alloc;
1190 mlx5_flow_counter_free_t counter_free;
1191 mlx5_flow_counter_query_t counter_query;
1192 mlx5_flow_get_aged_flows_t get_aged_flows;
1193 mlx5_flow_action_validate_t action_validate;
1194 mlx5_flow_action_create_t action_create;
1195 mlx5_flow_action_destroy_t action_destroy;
1196 mlx5_flow_action_update_t action_update;
1197 mlx5_flow_action_query_t action_query;
1198 mlx5_flow_sync_domain_t sync_domain;
1203 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1205 struct flow_grp_info {
1206 uint64_t external:1;
1207 uint64_t transfer:1;
1208 uint64_t fdb_def_rule:1;
1209 /* force standard group translation */
1210 uint64_t std_tbl_fix:1;
1211 uint64_t skip_scale:2;
1215 tunnel_use_standard_attr_group_translate
1216 (struct rte_eth_dev *dev,
1217 const struct mlx5_flow_tunnel *tunnel,
1218 const struct rte_flow_attr *attr,
1219 const struct rte_flow_item items[],
1220 const struct rte_flow_action actions[])
1224 if (!is_tunnel_offload_active(dev))
1225 /* no tunnel offload API */
1229 * OvS will use jump to group 0 in tunnel steer rule.
1230 * If tunnel steer rule starts from group 0 (attr.group == 0)
1231 * that 0 group must be translated with standard method.
1232 * attr.group == 0 in tunnel match rule translated with tunnel
1235 verdict = !attr->group &&
1236 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1239 * non-tunnel group translation uses standard method for
1240 * root group only: attr.group == 0
1242 verdict = !attr->group;
1249 * Get DV flow aso meter by index.
1252 * Pointer to the Ethernet device structure.
1254 * mlx5 flow aso meter index in the container.
1256 * mlx5 flow aso meter pool in the container,
1259 * Pointer to the aso meter, NULL otherwise.
1261 static inline struct mlx5_aso_mtr *
1262 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1264 struct mlx5_aso_mtr_pool *pool;
1265 struct mlx5_aso_mtr_pools_mng *pools_mng =
1266 &priv->sh->mtrmng->pools_mng;
1268 /* Decrease to original index. */
1270 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1271 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1272 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1275 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1276 const struct mlx5_flow_tunnel *tunnel,
1277 uint32_t group, uint32_t *table,
1278 const struct flow_grp_info *flags,
1279 struct rte_flow_error *error);
1280 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1281 int tunnel, uint64_t layer_types,
1282 uint64_t hash_fields);
1283 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1284 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1285 uint32_t subpriority);
1286 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1287 const struct rte_flow_attr *attr);
1288 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1289 const struct rte_flow_attr *attr,
1290 uint32_t subpriority);
1291 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1292 enum mlx5_feature_name feature,
1294 struct rte_flow_error *error);
1295 const struct rte_flow_action *mlx5_flow_find_action
1296 (const struct rte_flow_action *actions,
1297 enum rte_flow_action_type action);
1298 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1299 const struct rte_flow_action *action,
1300 struct rte_flow_error *error);
1301 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1302 const struct rte_flow_attr *attr,
1303 struct rte_flow_error *error);
1304 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1305 const struct rte_flow_attr *attr,
1306 struct rte_flow_error *error);
1307 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1308 const struct rte_flow_attr *attr,
1309 struct rte_flow_error *error);
1310 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1311 uint64_t action_flags,
1312 const struct rte_flow_attr *attr,
1313 struct rte_flow_error *error);
1314 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1315 uint64_t action_flags,
1316 struct rte_eth_dev *dev,
1317 const struct rte_flow_attr *attr,
1318 struct rte_flow_error *error);
1319 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1320 uint64_t action_flags,
1321 struct rte_eth_dev *dev,
1322 const struct rte_flow_attr *attr,
1323 uint64_t item_flags,
1324 struct rte_flow_error *error);
1325 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1326 const struct rte_flow_attr *attr,
1327 struct rte_flow_error *error);
1328 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1329 const struct rte_flow_attr *attributes,
1330 struct rte_flow_error *error);
1331 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1332 const uint8_t *mask,
1333 const uint8_t *nic_mask,
1335 bool range_accepted,
1336 struct rte_flow_error *error);
1337 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1338 uint64_t item_flags, bool ext_vlan_sup,
1339 struct rte_flow_error *error);
1340 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1341 uint64_t item_flags,
1342 uint8_t target_protocol,
1343 struct rte_flow_error *error);
1344 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1345 uint64_t item_flags,
1346 const struct rte_flow_item *gre_item,
1347 struct rte_flow_error *error);
1348 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1349 uint64_t item_flags,
1351 uint16_t ether_type,
1352 const struct rte_flow_item_ipv4 *acc_mask,
1353 bool range_accepted,
1354 struct rte_flow_error *error);
1355 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1356 uint64_t item_flags,
1358 uint16_t ether_type,
1359 const struct rte_flow_item_ipv6 *acc_mask,
1360 struct rte_flow_error *error);
1361 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1362 const struct rte_flow_item *item,
1363 uint64_t item_flags,
1364 uint64_t prev_layer,
1365 struct rte_flow_error *error);
1366 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1367 uint64_t item_flags,
1368 uint8_t target_protocol,
1369 const struct rte_flow_item_tcp *flow_mask,
1370 struct rte_flow_error *error);
1371 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1372 uint64_t item_flags,
1373 uint8_t target_protocol,
1374 struct rte_flow_error *error);
1375 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1376 uint64_t item_flags,
1377 struct rte_eth_dev *dev,
1378 struct rte_flow_error *error);
1379 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1380 uint64_t item_flags,
1381 struct rte_flow_error *error);
1382 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1383 uint64_t item_flags,
1384 struct rte_eth_dev *dev,
1385 struct rte_flow_error *error);
1386 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1387 uint64_t item_flags,
1388 uint8_t target_protocol,
1389 struct rte_flow_error *error);
1390 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1391 uint64_t item_flags,
1392 uint8_t target_protocol,
1393 struct rte_flow_error *error);
1394 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1395 uint64_t item_flags,
1396 uint8_t target_protocol,
1397 struct rte_flow_error *error);
1398 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1399 uint64_t item_flags,
1400 struct rte_eth_dev *dev,
1401 struct rte_flow_error *error);
1402 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1404 const struct rte_flow_item *geneve_item,
1405 struct rte_eth_dev *dev,
1406 struct rte_flow_error *error);
1407 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1408 uint64_t item_flags,
1410 uint16_t ether_type,
1411 const struct rte_flow_item_ecpri *acc_mask,
1412 struct rte_flow_error *error);
1413 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1414 struct mlx5_flow_meter_info *fm,
1416 uint8_t domain_bitmap);
1417 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1418 struct mlx5_flow_meter_info *fm);
1419 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1420 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1421 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1422 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1423 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1425 /* Hash list callbacks for flow tables: */
1426 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1427 uint64_t key, void *entry_ctx);
1428 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1429 struct mlx5_hlist_entry *entry, uint64_t key,
1431 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1432 struct mlx5_hlist_entry *entry);
1433 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1434 uint32_t table_level, uint8_t egress, uint8_t transfer,
1435 bool external, const struct mlx5_flow_tunnel *tunnel,
1436 uint32_t group_id, uint8_t dummy,
1437 uint32_t table_id, struct rte_flow_error *error);
1439 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1440 uint64_t key, void *cb_ctx);
1441 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1442 struct mlx5_hlist_entry *entry, uint64_t key,
1444 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1445 struct mlx5_hlist_entry *entry);
1447 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1448 struct mlx5_hlist_entry *entry,
1449 uint64_t key, void *cb_ctx);
1450 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1451 uint64_t key, void *ctx);
1452 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1453 struct mlx5_hlist_entry *entry);
1455 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1456 uint64_t key, void *ctx);
1457 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1458 struct mlx5_hlist_entry *entry, uint64_t key,
1460 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1461 struct mlx5_hlist_entry *entry);
1463 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1464 struct mlx5_hlist_entry *entry,
1465 uint64_t key, void *cb_ctx);
1466 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1467 uint64_t key, void *cb_ctx);
1468 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1469 struct mlx5_hlist_entry *entry);
1471 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1472 struct mlx5_cache_entry *entry, void *ctx);
1473 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1474 struct mlx5_cache_entry *entry, void *ctx);
1475 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1476 struct mlx5_cache_entry *entry);
1478 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1479 struct mlx5_cache_entry *entry, void *cb_ctx);
1480 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1481 struct mlx5_cache_entry *entry, void *cb_ctx);
1482 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1483 struct mlx5_cache_entry *entry);
1485 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1486 struct mlx5_cache_entry *entry, void *cb_ctx);
1487 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1488 (struct mlx5_cache_list *list,
1489 struct mlx5_cache_entry *entry, void *cb_ctx);
1490 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1491 struct mlx5_cache_entry *entry);
1493 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1494 struct mlx5_cache_entry *entry, void *cb_ctx);
1495 struct mlx5_cache_entry *flow_dv_sample_create_cb
1496 (struct mlx5_cache_list *list,
1497 struct mlx5_cache_entry *entry, void *cb_ctx);
1498 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1499 struct mlx5_cache_entry *entry);
1501 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1502 struct mlx5_cache_entry *entry, void *cb_ctx);
1503 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1504 (struct mlx5_cache_list *list,
1505 struct mlx5_cache_entry *entry, void *cb_ctx);
1506 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1507 struct mlx5_cache_entry *entry);
1508 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1510 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1511 const struct rte_flow_item *item,
1512 struct rte_flow_error *error);
1513 void flow_release_workspace(void *data);
1514 int mlx5_flow_os_init_workspace_once(void);
1515 void *mlx5_flow_os_get_specific_workspace(void);
1516 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1517 void mlx5_flow_os_release_workspace(void);
1518 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1519 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1520 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1521 const struct rte_flow_action *actions[RTE_COLORS],
1522 struct rte_flow_attr *attr,
1524 uint8_t *domain_bitmap,
1525 bool *is_def_policy,
1526 struct rte_mtr_error *error);
1527 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1528 struct mlx5_flow_meter_policy *mtr_policy);
1529 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1530 struct mlx5_flow_meter_policy *mtr_policy,
1531 const struct rte_flow_action *actions[RTE_COLORS],
1532 struct rte_mtr_error *error);
1533 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1534 struct mlx5_flow_meter_policy *mtr_policy);
1535 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1536 struct mlx5_flow_meter_policy *mtr_policy);
1537 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1538 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1539 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1540 struct mlx5_flow_handle *dev_handle);
1541 #endif /* RTE_PMD_MLX5_FLOW_H_ */