1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* E-Switch Manager port, used for rte_flow_item_port_id. */
22 #define MLX5_PORT_ESW_MGR UINT32_MAX
24 /* Private rte flow items. */
25 enum mlx5_rte_flow_item_type {
26 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
28 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
29 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
30 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
33 /* Private (internal) rte flow actions. */
34 enum mlx5_rte_flow_action_type {
35 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
36 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
37 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
38 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
39 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
41 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
43 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
46 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
49 MLX5_INDIRECT_ACTION_TYPE_RSS,
50 MLX5_INDIRECT_ACTION_TYPE_AGE,
51 MLX5_INDIRECT_ACTION_TYPE_COUNT,
52 MLX5_INDIRECT_ACTION_TYPE_CT,
55 /* Now, the maximal ports will be supported is 256, action number is 4M. */
56 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100
58 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22
59 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)
61 /* 30-31: type, 22-29: owner port, 0-21: index. */
62 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \
63 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \
64 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \
65 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index))
67 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \
68 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \
69 MLX5_INDIRECT_ACT_CT_OWNER_MASK)
71 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \
72 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))
74 /* Matches on selected register. */
75 struct mlx5_rte_flow_item_tag {
80 /* Modify selected register. */
81 struct mlx5_rte_flow_action_set_tag {
88 struct mlx5_flow_action_copy_mreg {
93 /* Matches on source queue. */
94 struct mlx5_rte_flow_item_tx_queue {
98 /* Feature name to allocate metadata register. */
99 enum mlx5_feature_name {
114 /* Default queue number. */
115 #define MLX5_RSSQ_DEFAULT_NUM 16
117 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
118 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
119 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
120 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
121 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
122 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
124 /* Pattern inner Layer bits. */
125 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
126 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
127 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
128 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
129 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
130 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
132 /* Pattern tunnel Layer bits. */
133 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
134 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
135 #define MLX5_FLOW_LAYER_GRE (1u << 14)
136 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
137 /* List of tunnel Layer bits continued below. */
139 /* General pattern items bits. */
140 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
141 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
142 #define MLX5_FLOW_ITEM_TAG (1u << 18)
143 #define MLX5_FLOW_ITEM_MARK (1u << 19)
145 /* Pattern MISC bits. */
146 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
147 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
148 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
150 /* Pattern tunnel Layer bits (continued). */
151 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
152 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
153 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
154 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
157 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
159 /* Pattern tunnel Layer bits (continued). */
160 #define MLX5_FLOW_LAYER_GTP (1u << 28)
162 /* Pattern eCPRI Layer bit. */
163 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
165 /* IPv6 Fragment Extension Header bit. */
166 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
167 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
169 /* Pattern tunnel Layer bits (continued). */
170 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
171 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
173 /* INTEGRITY item bits */
174 #define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34)
175 #define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35)
177 /* Conntrack item. */
178 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36)
181 #define MLX5_FLOW_LAYER_OUTER_L3 \
182 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
183 #define MLX5_FLOW_LAYER_OUTER_L4 \
184 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
185 #define MLX5_FLOW_LAYER_OUTER \
186 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
187 MLX5_FLOW_LAYER_OUTER_L4)
190 #define MLX5_FLOW_LAYER_TUNNEL \
191 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
192 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
193 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
194 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
197 #define MLX5_FLOW_LAYER_INNER_L3 \
198 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
199 #define MLX5_FLOW_LAYER_INNER_L4 \
200 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
201 #define MLX5_FLOW_LAYER_INNER \
202 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
203 MLX5_FLOW_LAYER_INNER_L4)
206 #define MLX5_FLOW_LAYER_L2 \
207 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
208 #define MLX5_FLOW_LAYER_L3_IPV4 \
209 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
210 #define MLX5_FLOW_LAYER_L3_IPV6 \
211 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
212 #define MLX5_FLOW_LAYER_L3 \
213 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
214 #define MLX5_FLOW_LAYER_L4 \
215 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
218 #define MLX5_FLOW_ACTION_DROP (1u << 0)
219 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
220 #define MLX5_FLOW_ACTION_RSS (1u << 2)
221 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
222 #define MLX5_FLOW_ACTION_MARK (1u << 4)
223 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
224 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
225 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
226 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
227 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
228 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
229 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
230 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
231 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
232 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
233 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
234 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
235 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
236 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
237 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
238 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
239 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
240 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
241 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
242 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
243 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
244 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
245 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
246 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
247 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
248 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
249 #define MLX5_FLOW_ACTION_METER (1ull << 31)
250 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
251 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
252 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
253 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
254 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
255 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
256 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
257 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
258 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
259 #define MLX5_FLOW_ACTION_CT (1ull << 41)
261 #define MLX5_FLOW_FATE_ACTIONS \
262 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
263 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
264 MLX5_FLOW_ACTION_DEFAULT_MISS | \
265 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
267 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
268 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
269 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
271 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
272 MLX5_FLOW_ACTION_SET_IPV4_DST | \
273 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
274 MLX5_FLOW_ACTION_SET_IPV6_DST | \
275 MLX5_FLOW_ACTION_SET_TP_SRC | \
276 MLX5_FLOW_ACTION_SET_TP_DST | \
277 MLX5_FLOW_ACTION_SET_TTL | \
278 MLX5_FLOW_ACTION_DEC_TTL | \
279 MLX5_FLOW_ACTION_SET_MAC_SRC | \
280 MLX5_FLOW_ACTION_SET_MAC_DST | \
281 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
282 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
283 MLX5_FLOW_ACTION_INC_TCP_ACK | \
284 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
285 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
286 MLX5_FLOW_ACTION_SET_TAG | \
287 MLX5_FLOW_ACTION_MARK_EXT | \
288 MLX5_FLOW_ACTION_SET_META | \
289 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
290 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
291 MLX5_FLOW_ACTION_MODIFY_FIELD)
293 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
294 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
296 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
299 #define IPPROTO_MPLS 137
302 /* UDP port number for MPLS */
303 #define MLX5_UDP_PORT_MPLS 6635
305 /* UDP port numbers for VxLAN. */
306 #define MLX5_UDP_PORT_VXLAN 4789
307 #define MLX5_UDP_PORT_VXLAN_GPE 4790
309 /* UDP port numbers for GENEVE. */
310 #define MLX5_UDP_PORT_GENEVE 6081
312 /* Lowest priority indicator. */
313 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
316 * Max priority for ingress\egress flow groups
317 * greater than 0 and for any transfer flow group.
318 * From user configation: 0 - 21843.
320 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
323 * Number of sub priorities.
324 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
325 * matching on the NIC (firmware dependent) L4 most have the higher priority
326 * followed by L3 and ending with L2.
328 #define MLX5_PRIORITY_MAP_L2 2
329 #define MLX5_PRIORITY_MAP_L3 1
330 #define MLX5_PRIORITY_MAP_L4 0
331 #define MLX5_PRIORITY_MAP_MAX 3
333 /* Valid layer type for IPV4 RSS. */
334 #define MLX5_IPV4_LAYER_TYPES \
335 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \
336 RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
337 RTE_ETH_RSS_NONFRAG_IPV4_OTHER)
339 /* IBV hash source bits for IPV4. */
340 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
342 /* Valid layer type for IPV6 RSS. */
343 #define MLX5_IPV6_LAYER_TYPES \
344 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
345 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | \
346 RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER)
348 /* IBV hash source bits for IPV6. */
349 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
351 /* IBV hash bits for L3 SRC. */
352 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
354 /* IBV hash bits for L3 DST. */
355 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
357 /* IBV hash bits for TCP. */
358 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
359 IBV_RX_HASH_DST_PORT_TCP)
361 /* IBV hash bits for UDP. */
362 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
363 IBV_RX_HASH_DST_PORT_UDP)
365 /* IBV hash bits for L4 SRC. */
366 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
367 IBV_RX_HASH_SRC_PORT_UDP)
369 /* IBV hash bits for L4 DST. */
370 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
371 IBV_RX_HASH_DST_PORT_UDP)
373 /* Geneve header first 16Bit */
374 #define MLX5_GENEVE_VER_MASK 0x3
375 #define MLX5_GENEVE_VER_SHIFT 14
376 #define MLX5_GENEVE_VER_VAL(a) \
377 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
378 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
379 #define MLX5_GENEVE_OPTLEN_SHIFT 8
380 #define MLX5_GENEVE_OPTLEN_VAL(a) \
381 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
382 #define MLX5_GENEVE_OAMF_MASK 0x1
383 #define MLX5_GENEVE_OAMF_SHIFT 7
384 #define MLX5_GENEVE_OAMF_VAL(a) \
385 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
386 #define MLX5_GENEVE_CRITO_MASK 0x1
387 #define MLX5_GENEVE_CRITO_SHIFT 6
388 #define MLX5_GENEVE_CRITO_VAL(a) \
389 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
390 #define MLX5_GENEVE_RSVD_MASK 0x3F
391 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
393 * The length of the Geneve options fields, expressed in four byte multiples,
394 * not including the eight byte fixed tunnel.
396 #define MLX5_GENEVE_OPT_LEN_0 14
397 #define MLX5_GENEVE_OPT_LEN_1 63
399 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
400 sizeof(struct rte_ipv4_hdr))
401 /* GTP extension header flag. */
402 #define MLX5_GTP_EXT_HEADER_FLAG 4
404 /* GTP extension header PDU type shift. */
405 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
407 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
408 #define MLX5_IPV4_FRAG_OFFSET_MASK \
409 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
411 /* Specific item's fields can accept a range of values (using spec and last). */
412 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
413 #define MLX5_ITEM_RANGE_ACCEPTED true
415 /* Software header modify action numbers of a flow. */
416 #define MLX5_ACT_NUM_MDF_IPV4 1
417 #define MLX5_ACT_NUM_MDF_IPV6 4
418 #define MLX5_ACT_NUM_MDF_MAC 2
419 #define MLX5_ACT_NUM_MDF_VID 1
420 #define MLX5_ACT_NUM_MDF_PORT 2
421 #define MLX5_ACT_NUM_MDF_TTL 1
422 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
423 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
424 #define MLX5_ACT_NUM_MDF_TCPACK 1
425 #define MLX5_ACT_NUM_SET_REG 1
426 #define MLX5_ACT_NUM_SET_TAG 1
427 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
428 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
429 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
430 #define MLX5_ACT_NUM_SET_DSCP 1
432 /* Maximum number of fields to modify in MODIFY_FIELD */
433 #define MLX5_ACT_MAX_MOD_FIELDS 5
435 /* Syndrome bits definition for connection tracking. */
436 #define MLX5_CT_SYNDROME_VALID (0x0 << 6)
437 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6)
438 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6)
439 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1)
440 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0)
442 enum mlx5_flow_drv_type {
445 MLX5_FLOW_TYPE_VERBS,
449 /* Fate action type. */
450 enum mlx5_flow_fate_type {
451 MLX5_FLOW_FATE_NONE, /* Egress flow. */
452 MLX5_FLOW_FATE_QUEUE,
454 MLX5_FLOW_FATE_PORT_ID,
456 MLX5_FLOW_FATE_DEFAULT_MISS,
457 MLX5_FLOW_FATE_SHARED_RSS,
462 /* Matcher PRM representation */
463 struct mlx5_flow_dv_match_params {
465 /**< Size of match value. Do NOT split size and key! */
466 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
467 /**< Matcher value. This value is used as the mask or as a key. */
470 /* Matcher structure. */
471 struct mlx5_flow_dv_matcher {
472 struct mlx5_list_entry entry; /**< Pointer to the next element. */
473 struct mlx5_flow_tbl_resource *tbl;
474 /**< Pointer to the table(group) the matcher associated with. */
475 void *matcher_object; /**< Pointer to DV matcher */
476 uint16_t crc; /**< CRC of key. */
477 uint16_t priority; /**< Priority of matcher. */
478 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
481 #define MLX5_ENCAP_MAX_LEN 132
483 /* Encap/decap resource structure. */
484 struct mlx5_flow_dv_encap_decap_resource {
485 struct mlx5_list_entry entry;
486 /* Pointer to next element. */
487 uint32_t refcnt; /**< Reference counter. */
489 /**< Encap/decap action object. */
490 uint8_t buf[MLX5_ENCAP_MAX_LEN];
492 uint8_t reformat_type;
494 uint64_t flags; /**< Flags for RDMA API. */
495 uint32_t idx; /**< Index for the index memory pool. */
498 /* Tag resource structure. */
499 struct mlx5_flow_dv_tag_resource {
500 struct mlx5_list_entry entry;
501 /**< hash list entry for tag resource, tag value as the key. */
503 /**< Tag action object. */
504 uint32_t refcnt; /**< Reference counter. */
505 uint32_t idx; /**< Index for the index memory pool. */
506 uint32_t tag_id; /**< Tag ID. */
509 /* Modify resource structure */
510 struct mlx5_flow_dv_modify_hdr_resource {
511 struct mlx5_list_entry entry;
512 void *action; /**< Modify header action object. */
514 /* Key area for hash list matching: */
515 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
516 uint8_t actions_num; /**< Number of modification actions. */
517 bool root; /**< Whether action is in root table. */
518 struct mlx5_modification_cmd actions[];
519 /**< Modification actions. */
522 /* Modify resource key of the hash organization. */
523 union mlx5_flow_modify_hdr_key {
525 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
526 uint32_t actions_num:5; /**< Number of modification actions. */
527 uint32_t group:19; /**< Flow group id. */
528 uint32_t cksum; /**< Actions check sum. */
530 uint64_t v64; /**< full 64bits value of key */
533 /* Jump action resource structure. */
534 struct mlx5_flow_dv_jump_tbl_resource {
535 void *action; /**< Pointer to the rdma core action. */
538 /* Port ID resource structure. */
539 struct mlx5_flow_dv_port_id_action_resource {
540 struct mlx5_list_entry entry;
541 void *action; /**< Action object. */
542 uint32_t port_id; /**< Port ID value. */
543 uint32_t idx; /**< Indexed pool memory index. */
546 /* Push VLAN action resource structure */
547 struct mlx5_flow_dv_push_vlan_action_resource {
548 struct mlx5_list_entry entry; /* Cache entry. */
549 void *action; /**< Action object. */
550 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
551 rte_be32_t vlan_tag; /**< VLAN tag value. */
552 uint32_t idx; /**< Indexed pool memory index. */
555 /* Metadata register copy table entry. */
556 struct mlx5_flow_mreg_copy_resource {
558 * Hash list entry for copy table.
559 * - Key is 32/64-bit MARK action ID.
560 * - MUST be the first entry.
562 struct mlx5_list_entry hlist_ent;
563 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
564 /* List entry for device flows. */
566 uint32_t rix_flow; /* Built flow for copy. */
570 /* Table tunnel parameter. */
571 struct mlx5_flow_tbl_tunnel_prm {
572 const struct mlx5_flow_tunnel *tunnel;
577 /* Table data structure of the hash organization. */
578 struct mlx5_flow_tbl_data_entry {
579 struct mlx5_list_entry entry;
580 /**< hash list entry, 64-bits key inside. */
581 struct mlx5_flow_tbl_resource tbl;
582 /**< flow table resource. */
583 struct mlx5_list *matchers;
584 /**< matchers' header associated with the flow table. */
585 struct mlx5_flow_dv_jump_tbl_resource jump;
586 /**< jump resource, at most one for each table created. */
587 uint32_t idx; /**< index for the indexed mempool. */
588 /**< tunnel offload */
589 const struct mlx5_flow_tunnel *tunnel;
592 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
593 uint32_t is_egress:1; /**< Egress table. */
594 uint32_t is_transfer:1; /**< Transfer table. */
595 uint32_t dummy:1; /**< DR table. */
596 uint32_t id:22; /**< Table ID. */
597 uint32_t reserve:5; /**< Reserved to future using. */
598 uint32_t level; /**< Table level. */
601 /* Sub rdma-core actions list. */
602 struct mlx5_flow_sub_actions_list {
603 uint32_t actions_num; /**< Number of sample actions. */
604 uint64_t action_flags;
605 void *dr_queue_action;
608 void *dr_port_id_action;
609 void *dr_encap_action;
610 void *dr_jump_action;
613 /* Sample sub-actions resource list. */
614 struct mlx5_flow_sub_actions_idx {
615 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
616 uint32_t rix_tag; /**< Index to the tag action. */
617 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
618 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
619 uint32_t rix_jump; /**< Index to the jump action resource. */
622 /* Sample action resource structure. */
623 struct mlx5_flow_dv_sample_resource {
624 struct mlx5_list_entry entry; /**< Cache entry. */
626 void *verbs_action; /**< Verbs sample action object. */
627 void **sub_actions; /**< Sample sub-action array. */
629 struct rte_eth_dev *dev; /**< Device registers the action. */
630 uint32_t idx; /** Sample object index. */
631 uint8_t ft_type; /** Flow Table Type */
632 uint32_t ft_id; /** Flow Table Level */
633 uint32_t ratio; /** Sample Ratio */
634 uint64_t set_action; /** Restore reg_c0 value */
635 void *normal_path_tbl; /** Flow Table pointer */
636 struct mlx5_flow_sub_actions_idx sample_idx;
637 /**< Action index resources. */
638 struct mlx5_flow_sub_actions_list sample_act;
639 /**< Action resources. */
642 #define MLX5_MAX_DEST_NUM 2
644 /* Destination array action resource structure. */
645 struct mlx5_flow_dv_dest_array_resource {
646 struct mlx5_list_entry entry; /**< Cache entry. */
647 uint32_t idx; /** Destination array action object index. */
648 uint8_t ft_type; /** Flow Table Type */
649 uint8_t num_of_dest; /**< Number of destination actions. */
650 struct rte_eth_dev *dev; /**< Device registers the action. */
651 void *action; /**< Pointer to the rdma core action. */
652 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
653 /**< Action index resources. */
654 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
655 /**< Action resources. */
658 /* PMD flow priority for tunnel */
659 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
660 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
663 /** Device flow handle structure for DV mode only. */
664 struct mlx5_flow_handle_dv {
666 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
667 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
668 /**< Pointer to modify header resource in cache. */
669 uint32_t rix_encap_decap;
670 /**< Index to encap/decap resource in cache. */
671 uint32_t rix_push_vlan;
672 /**< Index to push VLAN action resource in cache. */
674 /**< Index to the tag action. */
676 /**< Index to sample action resource in cache. */
677 uint32_t rix_dest_array;
678 /**< Index to destination array resource in cache. */
681 /** Device flow handle structure: used both for creating & destroying. */
682 struct mlx5_flow_handle {
683 SILIST_ENTRY(uint32_t)next;
684 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
685 /**< Index to next device flow handle. */
687 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
688 void *drv_flow; /**< pointer to driver flow object. */
689 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
690 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
691 uint32_t mark:1; /**< Metadate rxq mark flag. */
692 uint32_t fate_action:3; /**< Fate action type. */
694 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
695 uint32_t rix_jump; /**< Index to the jump action resource. */
696 uint32_t rix_port_id_action;
697 /**< Index to port ID action resource. */
699 /**< Generic value indicates the fate action. */
700 uint32_t rix_default_fate;
701 /**< Indicates default miss fate action. */
703 /**< Indicates shared RSS fate action. */
705 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
706 struct mlx5_flow_handle_dv dvh;
711 * Size for Verbs device flow handle structure only. Do not use the DV only
712 * structure in Verbs. No DV flows attributes will be accessed.
713 * Macro offsetof() could also be used here.
715 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
716 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
717 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
719 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
722 /** Device flow structure only for DV flow creation. */
723 struct mlx5_flow_dv_workspace {
724 uint32_t group; /**< The group index. */
725 uint32_t table_id; /**< Flow table identifier. */
726 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
727 int actions_n; /**< number of actions. */
728 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
729 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
730 /**< Pointer to encap/decap resource in cache. */
731 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
732 /**< Pointer to push VLAN action resource in cache. */
733 struct mlx5_flow_dv_tag_resource *tag_resource;
734 /**< pointer to the tag action. */
735 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
736 /**< Pointer to port ID action resource. */
737 struct mlx5_flow_dv_jump_tbl_resource *jump;
738 /**< Pointer to the jump action resource. */
739 struct mlx5_flow_dv_match_params value;
740 /**< Holds the value that the packet is compared to. */
741 struct mlx5_flow_dv_sample_resource *sample_res;
742 /**< Pointer to the sample action resource. */
743 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
744 /**< Pointer to the destination array resource. */
747 #ifdef HAVE_INFINIBAND_VERBS_H
749 * Maximal Verbs flow specifications & actions size.
750 * Some elements are mutually exclusive, but enough space should be allocated.
751 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
752 * 2. One tunnel header (exception: GRE + MPLS),
753 * SPEC length: GRE == tunnel.
754 * Actions: 1. 1 Mark OR Flag.
755 * 2. 1 Drop (if any).
756 * 3. No limitation for counters, but it makes no sense to support too
757 * many counters in a single device flow.
759 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
760 #define MLX5_VERBS_MAX_SPEC_SIZE \
762 (2 * (sizeof(struct ibv_flow_spec_eth) + \
763 sizeof(struct ibv_flow_spec_ipv6) + \
764 sizeof(struct ibv_flow_spec_tcp_udp)) + \
765 sizeof(struct ibv_flow_spec_gre) + \
766 sizeof(struct ibv_flow_spec_mpls)) \
769 #define MLX5_VERBS_MAX_SPEC_SIZE \
771 (2 * (sizeof(struct ibv_flow_spec_eth) + \
772 sizeof(struct ibv_flow_spec_ipv6) + \
773 sizeof(struct ibv_flow_spec_tcp_udp)) + \
774 sizeof(struct ibv_flow_spec_tunnel)) \
778 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
779 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
780 #define MLX5_VERBS_MAX_ACT_SIZE \
782 sizeof(struct ibv_flow_spec_action_tag) + \
783 sizeof(struct ibv_flow_spec_action_drop) + \
784 sizeof(struct ibv_flow_spec_counter_action) * 4 \
787 #define MLX5_VERBS_MAX_ACT_SIZE \
789 sizeof(struct ibv_flow_spec_action_tag) + \
790 sizeof(struct ibv_flow_spec_action_drop) \
794 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
795 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
797 /** Device flow structure only for Verbs flow creation. */
798 struct mlx5_flow_verbs_workspace {
799 unsigned int size; /**< Size of the attribute. */
800 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
801 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
802 /**< Specifications & actions buffer of verbs flow. */
804 #endif /* HAVE_INFINIBAND_VERBS_H */
806 #define MLX5_SCALE_FLOW_GROUP_BIT 0
807 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
809 /** Maximal number of device sub-flows supported. */
810 #define MLX5_NUM_MAX_DEV_FLOWS 32
813 * tunnel offload rules type
815 enum mlx5_tof_rule_type {
816 MLX5_TUNNEL_OFFLOAD_NONE = 0,
817 MLX5_TUNNEL_OFFLOAD_SET_RULE,
818 MLX5_TUNNEL_OFFLOAD_MATCH_RULE,
819 MLX5_TUNNEL_OFFLOAD_MISS_RULE,
822 /** Device flow structure. */
825 struct rte_flow *flow; /**< Pointer to the main flow. */
826 uint32_t flow_idx; /**< The memory pool index to the main flow. */
827 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
829 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
830 bool external; /**< true if the flow is created external to PMD. */
831 uint8_t ingress:1; /**< 1 if the flow is ingress. */
832 uint8_t skip_scale:2;
834 * Each Bit be set to 1 if Skip the scale the flow group with factor.
835 * If bit0 be set to 1, then skip the scale the original flow group;
836 * If bit1 be set to 1, then skip the scale the jump flow group if
837 * having jump action.
838 * 00: Enable scale in a flow, default value.
839 * 01: Skip scale the flow group with factor, enable scale the group
841 * 10: Enable scale the group with factor, skip scale the group of
843 * 11: Skip scale the table with factor both for flow group and jump
847 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
848 struct mlx5_flow_dv_workspace dv;
850 #ifdef HAVE_INFINIBAND_VERBS_H
851 struct mlx5_flow_verbs_workspace verbs;
854 struct mlx5_flow_handle *handle;
855 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
856 const struct mlx5_flow_tunnel *tunnel;
857 enum mlx5_tof_rule_type tof_type;
860 /* Flow meter state. */
861 #define MLX5_FLOW_METER_DISABLE 0
862 #define MLX5_FLOW_METER_ENABLE 1
864 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
865 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
867 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
869 #define MLX5_MAN_WIDTH 8
870 /* Legacy Meter parameter structure. */
871 struct mlx5_legacy_flow_meter {
872 struct mlx5_flow_meter_info fm;
873 /* Must be the first in struct. */
874 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
875 /**< Pointer to the next flow meter structure. */
877 /* Index to meter object. */
880 #define MLX5_MAX_TUNNELS 256
881 #define MLX5_TNL_MISS_RULE_PRIORITY 3
882 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
885 * When tunnel offload is active, all JUMP group ids are converted
886 * using the same method. That conversion is applied both to tunnel and
887 * regular rule types.
888 * Group ids used in tunnel rules are relative to it's tunnel (!).
889 * Application can create number of steer rules, using the same
890 * tunnel, with different group id in each rule.
891 * Each tunnel stores its groups internally in PMD tunnel object.
892 * Groups used in regular rules do not belong to any tunnel and are stored
896 struct mlx5_flow_tunnel {
897 LIST_ENTRY(mlx5_flow_tunnel) chain;
898 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
899 uint32_t tunnel_id; /** unique tunnel ID */
901 struct rte_flow_action action;
902 struct rte_flow_item item;
903 struct mlx5_hlist *groups; /** tunnel groups */
906 /** PMD tunnel related context */
907 struct mlx5_flow_tunnel_hub {
909 * Access to the list MUST be MT protected
911 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
912 /* protect access to the tunnels list */
914 struct mlx5_hlist *groups; /** non tunnel groups */
917 /* convert jump group to flow table ID in tunnel rules */
918 struct tunnel_tbl_entry {
919 struct mlx5_list_entry hash;
925 static inline uint32_t
926 tunnel_id_to_flow_tbl(uint32_t id)
928 return id | (1u << 16);
931 static inline uint32_t
932 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
934 return flow_tbl & ~(1u << 16);
937 union tunnel_tbl_key {
945 static inline struct mlx5_flow_tunnel_hub *
946 mlx5_tunnel_hub(struct rte_eth_dev *dev)
948 struct mlx5_priv *priv = dev->data->dev_private;
949 return priv->sh->tunnel_hub;
953 is_tunnel_offload_active(const struct rte_eth_dev *dev)
955 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
956 const struct mlx5_priv *priv = dev->data->dev_private;
957 return !!priv->config.dv_miss_info;
965 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type)
967 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE;
971 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type)
973 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE;
976 static inline const struct mlx5_flow_tunnel *
977 flow_actions_to_tunnel(const struct rte_flow_action actions[])
979 return actions[0].conf;
982 static inline const struct mlx5_flow_tunnel *
983 flow_items_to_tunnel(const struct rte_flow_item items[])
985 return items[0].spec;
988 /* Flow structure. */
990 uint32_t dev_handles;
991 /**< Device flow handles that are part of the flow. */
993 uint32_t drv_type:2; /**< Driver type. */
995 uint32_t meter:24; /**< Holds flow meter id. */
996 uint32_t indirect_type:2; /**< Indirect action type. */
997 uint32_t rix_mreg_copy;
998 /**< Index to metadata register copy table resource. */
999 uint32_t counter; /**< Holds flow counter. */
1000 uint32_t tunnel_id; /**< Tunnel id */
1002 uint32_t age; /**< Holds ASO age bit index. */
1003 uint32_t ct; /**< Holds ASO CT index. */
1005 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1009 * Define list of valid combinations of RX Hash fields
1010 * (see enum ibv_rx_hash_fields).
1012 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1013 #define MLX5_RSS_HASH_IPV4_TCP \
1014 (MLX5_RSS_HASH_IPV4 | \
1015 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1016 #define MLX5_RSS_HASH_IPV4_UDP \
1017 (MLX5_RSS_HASH_IPV4 | \
1018 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1019 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1020 #define MLX5_RSS_HASH_IPV6_TCP \
1021 (MLX5_RSS_HASH_IPV6 | \
1022 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1023 #define MLX5_RSS_HASH_IPV6_UDP \
1024 (MLX5_RSS_HASH_IPV6 | \
1025 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1026 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1027 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1028 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1029 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1030 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1031 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1032 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1033 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1034 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1035 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1036 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1037 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1038 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1039 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1040 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1041 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1042 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1043 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1044 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1045 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1046 #define MLX5_RSS_HASH_NONE 0ULL
1049 /* extract next protocol type from Ethernet & VLAN headers */
1050 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1051 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1052 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1053 (_prt) = rte_be_to_cpu_16((_prt)); \
1056 /* array of valid combinations of RX Hash fields for RSS */
1057 static const uint64_t mlx5_rss_hash_fields[] = {
1059 MLX5_RSS_HASH_IPV4_TCP,
1060 MLX5_RSS_HASH_IPV4_UDP,
1062 MLX5_RSS_HASH_IPV6_TCP,
1063 MLX5_RSS_HASH_IPV6_UDP,
1067 /* Shared RSS action structure */
1068 struct mlx5_shared_action_rss {
1069 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1070 uint32_t refcnt; /**< Atomically accessed refcnt. */
1071 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1072 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1073 struct mlx5_ind_table_obj *ind_tbl;
1074 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1075 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1076 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1077 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1080 struct rte_flow_action_handle {
1084 /* Thread specific flow workspace intermediate data. */
1085 struct mlx5_flow_workspace {
1086 /* If creating another flow in same thread, push new as stack. */
1087 struct mlx5_flow_workspace *prev;
1088 struct mlx5_flow_workspace *next;
1089 uint32_t inuse; /* can't create new flow with current. */
1090 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1091 struct mlx5_flow_rss_desc rss_desc;
1092 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1093 uint32_t flow_idx; /* Intermediate device flow index. */
1094 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1095 struct mlx5_flow_meter_policy *policy;
1096 /* The meter policy used by meter in flow. */
1097 struct mlx5_flow_meter_policy *final_policy;
1098 /* The final policy when meter policy is hierarchy. */
1099 uint32_t skip_matcher_reg:1;
1100 /* Indicates if need to skip matcher register in translate. */
1103 struct mlx5_flow_split_info {
1105 /**< True if flow is created by request external to PMD. */
1106 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1107 uint32_t flow_idx; /**< This memory pool index to the flow. */
1108 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1109 uint64_t prefix_layers; /**< Prefix subflow layers. */
1110 uint32_t table_id; /**< Flow table identifier. */
1113 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1114 const struct rte_flow_attr *attr,
1115 const struct rte_flow_item items[],
1116 const struct rte_flow_action actions[],
1119 struct rte_flow_error *error);
1120 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1121 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1122 const struct rte_flow_item items[],
1123 const struct rte_flow_action actions[], struct rte_flow_error *error);
1124 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1125 struct mlx5_flow *dev_flow,
1126 const struct rte_flow_attr *attr,
1127 const struct rte_flow_item items[],
1128 const struct rte_flow_action actions[],
1129 struct rte_flow_error *error);
1130 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1131 struct rte_flow_error *error);
1132 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1133 struct rte_flow *flow);
1134 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1135 struct rte_flow *flow);
1136 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1137 struct rte_flow *flow,
1138 const struct rte_flow_action *actions,
1140 struct rte_flow_error *error);
1141 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1142 struct mlx5_flow_meter_info *fm,
1144 uint8_t domain_bitmap);
1145 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1146 struct mlx5_flow_meter_info *fm);
1147 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1148 typedef struct mlx5_flow_meter_sub_policy *
1149 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1150 (struct rte_eth_dev *dev,
1151 struct mlx5_flow_meter_policy *mtr_policy,
1152 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1153 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t)
1154 (struct rte_eth_dev *dev,
1155 struct mlx5_flow_meter_info *fm,
1157 const struct rte_flow_item *item,
1158 struct rte_flow_error *error);
1159 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t)
1160 (struct rte_eth_dev *dev,
1161 struct mlx5_flow_meter_policy *mtr_policy);
1162 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1163 (struct rte_eth_dev *dev);
1164 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1166 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1167 (struct rte_eth_dev *dev);
1168 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1170 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1172 bool clear, uint64_t *pkts,
1174 typedef int (*mlx5_flow_get_aged_flows_t)
1175 (struct rte_eth_dev *dev,
1177 uint32_t nb_contexts,
1178 struct rte_flow_error *error);
1179 typedef int (*mlx5_flow_action_validate_t)
1180 (struct rte_eth_dev *dev,
1181 const struct rte_flow_indir_action_conf *conf,
1182 const struct rte_flow_action *action,
1183 struct rte_flow_error *error);
1184 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1185 (struct rte_eth_dev *dev,
1186 const struct rte_flow_indir_action_conf *conf,
1187 const struct rte_flow_action *action,
1188 struct rte_flow_error *error);
1189 typedef int (*mlx5_flow_action_destroy_t)
1190 (struct rte_eth_dev *dev,
1191 struct rte_flow_action_handle *action,
1192 struct rte_flow_error *error);
1193 typedef int (*mlx5_flow_action_update_t)
1194 (struct rte_eth_dev *dev,
1195 struct rte_flow_action_handle *action,
1197 struct rte_flow_error *error);
1198 typedef int (*mlx5_flow_action_query_t)
1199 (struct rte_eth_dev *dev,
1200 const struct rte_flow_action_handle *action,
1202 struct rte_flow_error *error);
1203 typedef int (*mlx5_flow_sync_domain_t)
1204 (struct rte_eth_dev *dev,
1207 typedef int (*mlx5_flow_validate_mtr_acts_t)
1208 (struct rte_eth_dev *dev,
1209 const struct rte_flow_action *actions[RTE_COLORS],
1210 struct rte_flow_attr *attr,
1212 uint8_t *domain_bitmap,
1213 uint8_t *policy_mode,
1214 struct rte_mtr_error *error);
1215 typedef int (*mlx5_flow_create_mtr_acts_t)
1216 (struct rte_eth_dev *dev,
1217 struct mlx5_flow_meter_policy *mtr_policy,
1218 const struct rte_flow_action *actions[RTE_COLORS],
1219 struct rte_mtr_error *error);
1220 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1221 (struct rte_eth_dev *dev,
1222 struct mlx5_flow_meter_policy *mtr_policy);
1223 typedef int (*mlx5_flow_create_policy_rules_t)
1224 (struct rte_eth_dev *dev,
1225 struct mlx5_flow_meter_policy *mtr_policy);
1226 typedef void (*mlx5_flow_destroy_policy_rules_t)
1227 (struct rte_eth_dev *dev,
1228 struct mlx5_flow_meter_policy *mtr_policy);
1229 typedef int (*mlx5_flow_create_def_policy_t)
1230 (struct rte_eth_dev *dev);
1231 typedef void (*mlx5_flow_destroy_def_policy_t)
1232 (struct rte_eth_dev *dev);
1234 struct mlx5_flow_driver_ops {
1235 mlx5_flow_validate_t validate;
1236 mlx5_flow_prepare_t prepare;
1237 mlx5_flow_translate_t translate;
1238 mlx5_flow_apply_t apply;
1239 mlx5_flow_remove_t remove;
1240 mlx5_flow_destroy_t destroy;
1241 mlx5_flow_query_t query;
1242 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1243 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1244 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1245 mlx5_flow_mtr_alloc_t create_meter;
1246 mlx5_flow_mtr_free_t free_meter;
1247 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1248 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1249 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1250 mlx5_flow_create_policy_rules_t create_policy_rules;
1251 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1252 mlx5_flow_create_def_policy_t create_def_policy;
1253 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1254 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1255 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create;
1256 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq;
1257 mlx5_flow_counter_alloc_t counter_alloc;
1258 mlx5_flow_counter_free_t counter_free;
1259 mlx5_flow_counter_query_t counter_query;
1260 mlx5_flow_get_aged_flows_t get_aged_flows;
1261 mlx5_flow_action_validate_t action_validate;
1262 mlx5_flow_action_create_t action_create;
1263 mlx5_flow_action_destroy_t action_destroy;
1264 mlx5_flow_action_update_t action_update;
1265 mlx5_flow_action_query_t action_query;
1266 mlx5_flow_sync_domain_t sync_domain;
1271 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1273 struct flow_grp_info {
1274 uint64_t external:1;
1275 uint64_t transfer:1;
1276 uint64_t fdb_def_rule:1;
1277 /* force standard group translation */
1278 uint64_t std_tbl_fix:1;
1279 uint64_t skip_scale:2;
1283 tunnel_use_standard_attr_group_translate
1284 (const struct rte_eth_dev *dev,
1285 const struct rte_flow_attr *attr,
1286 const struct mlx5_flow_tunnel *tunnel,
1287 enum mlx5_tof_rule_type tof_rule_type)
1291 if (!is_tunnel_offload_active(dev))
1292 /* no tunnel offload API */
1296 * OvS will use jump to group 0 in tunnel steer rule.
1297 * If tunnel steer rule starts from group 0 (attr.group == 0)
1298 * that 0 group must be translated with standard method.
1299 * attr.group == 0 in tunnel match rule translated with tunnel
1302 verdict = !attr->group &&
1303 is_flow_tunnel_steer_rule(tof_rule_type);
1306 * non-tunnel group translation uses standard method for
1307 * root group only: attr.group == 0
1309 verdict = !attr->group;
1316 * Get DV flow aso meter by index.
1319 * Pointer to the Ethernet device structure.
1321 * mlx5 flow aso meter index in the container.
1323 * mlx5 flow aso meter pool in the container,
1326 * Pointer to the aso meter, NULL otherwise.
1328 static inline struct mlx5_aso_mtr *
1329 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1331 struct mlx5_aso_mtr_pool *pool;
1332 struct mlx5_aso_mtr_pools_mng *pools_mng =
1333 &priv->sh->mtrmng->pools_mng;
1335 /* Decrease to original index. */
1337 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1338 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1339 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1342 static __rte_always_inline const struct rte_flow_item *
1343 mlx5_find_end_item(const struct rte_flow_item *item)
1345 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1349 static __rte_always_inline bool
1350 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1352 struct rte_flow_item_integrity test = *item;
1355 test.ipv4_csum_ok = 0;
1356 test.l4_csum_ok = 0;
1357 return (test.value == 0);
1361 * Get ASO CT action by device and index.
1364 * Pointer to the Ethernet device structure.
1366 * Index to the ASO CT action.
1369 * The specified ASO CT action pointer.
1371 static inline struct mlx5_aso_ct_action *
1372 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx)
1374 struct mlx5_priv *priv = dev->data->dev_private;
1375 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
1376 struct mlx5_aso_ct_pool *pool;
1379 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n);
1380 /* Bit operation AND could be used. */
1381 rte_rwlock_read_lock(&mng->resize_rwl);
1382 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL];
1383 rte_rwlock_read_unlock(&mng->resize_rwl);
1384 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];
1388 * Get ASO CT action by owner & index.
1391 * Pointer to the Ethernet device structure.
1393 * Index to the ASO CT action and owner port combination.
1396 * The specified ASO CT action pointer.
1398 static inline struct mlx5_aso_ct_action *
1399 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx)
1401 struct mlx5_priv *priv = dev->data->dev_private;
1402 struct mlx5_aso_ct_action *ct;
1403 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
1404 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
1406 if (owner == PORT_ID(priv)) {
1407 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
1409 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
1411 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
1412 if (dev->data->dev_started != 1)
1414 ct = flow_aso_ct_get_by_dev_idx(owndev, idx);
1415 if (ct->peer != PORT_ID(priv))
1421 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1422 const struct mlx5_flow_tunnel *tunnel,
1423 uint32_t group, uint32_t *table,
1424 const struct flow_grp_info *flags,
1425 struct rte_flow_error *error);
1426 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1427 int tunnel, uint64_t layer_types,
1428 uint64_t hash_fields);
1429 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1430 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1431 uint32_t subpriority);
1432 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1433 const struct rte_flow_attr *attr);
1434 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1435 const struct rte_flow_attr *attr,
1436 uint32_t subpriority, bool external);
1437 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1438 enum mlx5_feature_name feature,
1440 struct rte_flow_error *error);
1441 const struct rte_flow_action *mlx5_flow_find_action
1442 (const struct rte_flow_action *actions,
1443 enum rte_flow_action_type action);
1444 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1445 const struct rte_flow_action *action,
1446 struct rte_flow_error *error);
1447 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1448 const struct rte_flow_attr *attr,
1449 struct rte_flow_error *error);
1450 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1451 const struct rte_flow_attr *attr,
1452 struct rte_flow_error *error);
1453 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1454 const struct rte_flow_attr *attr,
1455 struct rte_flow_error *error);
1456 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1457 uint64_t action_flags,
1458 const struct rte_flow_attr *attr,
1459 struct rte_flow_error *error);
1460 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1461 uint64_t action_flags,
1462 struct rte_eth_dev *dev,
1463 const struct rte_flow_attr *attr,
1464 struct rte_flow_error *error);
1465 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1466 uint64_t action_flags,
1467 struct rte_eth_dev *dev,
1468 const struct rte_flow_attr *attr,
1469 uint64_t item_flags,
1470 struct rte_flow_error *error);
1471 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1472 const struct rte_flow_attr *attr,
1473 struct rte_flow_error *error);
1474 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1475 const struct rte_flow_attr *attributes,
1476 struct rte_flow_error *error);
1477 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1478 const uint8_t *mask,
1479 const uint8_t *nic_mask,
1481 bool range_accepted,
1482 struct rte_flow_error *error);
1483 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1484 uint64_t item_flags, bool ext_vlan_sup,
1485 struct rte_flow_error *error);
1486 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1487 uint64_t item_flags,
1488 uint8_t target_protocol,
1489 struct rte_flow_error *error);
1490 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1491 uint64_t item_flags,
1492 const struct rte_flow_item *gre_item,
1493 struct rte_flow_error *error);
1494 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1495 uint64_t item_flags,
1497 uint16_t ether_type,
1498 const struct rte_flow_item_ipv4 *acc_mask,
1499 bool range_accepted,
1500 struct rte_flow_error *error);
1501 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1502 uint64_t item_flags,
1504 uint16_t ether_type,
1505 const struct rte_flow_item_ipv6 *acc_mask,
1506 struct rte_flow_error *error);
1507 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1508 const struct rte_flow_item *item,
1509 uint64_t item_flags,
1510 uint64_t prev_layer,
1511 struct rte_flow_error *error);
1512 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1513 uint64_t item_flags,
1514 uint8_t target_protocol,
1515 const struct rte_flow_item_tcp *flow_mask,
1516 struct rte_flow_error *error);
1517 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1518 uint64_t item_flags,
1519 uint8_t target_protocol,
1520 struct rte_flow_error *error);
1521 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1522 uint64_t item_flags,
1523 struct rte_eth_dev *dev,
1524 struct rte_flow_error *error);
1525 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev,
1527 const struct rte_flow_item *item,
1528 uint64_t item_flags,
1529 const struct rte_flow_attr *attr,
1530 struct rte_flow_error *error);
1531 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1532 uint64_t item_flags,
1533 struct rte_eth_dev *dev,
1534 struct rte_flow_error *error);
1535 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1536 uint64_t item_flags,
1537 uint8_t target_protocol,
1538 struct rte_flow_error *error);
1539 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1540 uint64_t item_flags,
1541 uint8_t target_protocol,
1542 struct rte_flow_error *error);
1543 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1544 uint64_t item_flags,
1545 uint8_t target_protocol,
1546 struct rte_flow_error *error);
1547 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1548 uint64_t item_flags,
1549 struct rte_eth_dev *dev,
1550 struct rte_flow_error *error);
1551 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1553 const struct rte_flow_item *geneve_item,
1554 struct rte_eth_dev *dev,
1555 struct rte_flow_error *error);
1556 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1557 uint64_t item_flags,
1559 uint16_t ether_type,
1560 const struct rte_flow_item_ecpri *acc_mask,
1561 struct rte_flow_error *error);
1562 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1563 struct mlx5_flow_meter_info *fm,
1565 uint8_t domain_bitmap);
1566 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1567 struct mlx5_flow_meter_info *fm);
1568 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1569 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1570 (struct rte_eth_dev *dev,
1571 struct mlx5_flow_meter_policy *mtr_policy,
1572 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1573 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
1574 struct mlx5_flow_meter_policy *mtr_policy);
1575 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1576 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev);
1577 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1578 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1579 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1581 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx);
1582 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1584 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1585 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx,
1586 struct mlx5_list_entry *oentry,
1588 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1589 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1590 uint32_t table_level, uint8_t egress, uint8_t transfer,
1591 bool external, const struct mlx5_flow_tunnel *tunnel,
1592 uint32_t group_id, uint8_t dummy,
1593 uint32_t table_id, struct rte_flow_error *error);
1595 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx);
1596 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1598 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1599 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx,
1600 struct mlx5_list_entry *oentry,
1602 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1604 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1606 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx);
1607 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1608 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx,
1609 struct mlx5_list_entry *oentry,
1611 void flow_dv_modify_clone_free_cb(void *tool_ctx,
1612 struct mlx5_list_entry *entry);
1614 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx);
1615 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1617 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1618 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx,
1619 struct mlx5_list_entry *entry,
1621 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1623 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1625 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx,
1627 void flow_dv_encap_decap_remove_cb(void *tool_ctx,
1628 struct mlx5_list_entry *entry);
1629 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx,
1630 struct mlx5_list_entry *entry,
1632 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx,
1633 struct mlx5_list_entry *entry);
1635 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1637 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx);
1638 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1640 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1642 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx);
1643 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1644 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx,
1645 struct mlx5_list_entry *entry, void *cb_ctx);
1646 void flow_dv_port_id_clone_free_cb(void *tool_ctx,
1647 struct mlx5_list_entry *entry);
1649 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1651 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx,
1653 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1654 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx,
1655 struct mlx5_list_entry *entry, void *cb_ctx);
1656 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx,
1657 struct mlx5_list_entry *entry);
1659 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1661 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx);
1662 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1663 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx,
1664 struct mlx5_list_entry *entry, void *cb_ctx);
1665 void flow_dv_sample_clone_free_cb(void *tool_ctx,
1666 struct mlx5_list_entry *entry);
1668 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1670 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx,
1672 void flow_dv_dest_array_remove_cb(void *tool_ctx,
1673 struct mlx5_list_entry *entry);
1674 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx,
1675 struct mlx5_list_entry *entry, void *cb_ctx);
1676 void flow_dv_dest_array_clone_free_cb(void *tool_ctx,
1677 struct mlx5_list_entry *entry);
1678 int flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
1679 void **action, struct rte_flow_error *error);
1681 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
1682 struct rte_flow_error *error);
1684 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1686 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1687 const struct rte_flow_item *item,
1688 struct rte_flow_error *error);
1689 void flow_release_workspace(void *data);
1690 int mlx5_flow_os_init_workspace_once(void);
1691 void *mlx5_flow_os_get_specific_workspace(void);
1692 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1693 void mlx5_flow_os_release_workspace(void);
1694 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1695 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1696 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1697 const struct rte_flow_action *actions[RTE_COLORS],
1698 struct rte_flow_attr *attr,
1700 uint8_t *domain_bitmap,
1701 uint8_t *policy_mode,
1702 struct rte_mtr_error *error);
1703 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1704 struct mlx5_flow_meter_policy *mtr_policy);
1705 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1706 struct mlx5_flow_meter_policy *mtr_policy,
1707 const struct rte_flow_action *actions[RTE_COLORS],
1708 struct rte_mtr_error *error);
1709 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1710 struct mlx5_flow_meter_policy *mtr_policy);
1711 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1712 struct mlx5_flow_meter_policy *mtr_policy);
1713 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1714 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1715 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1716 struct mlx5_flow_handle *dev_handle);
1717 const struct mlx5_flow_tunnel *
1718 mlx5_get_tof(const struct rte_flow_item *items,
1719 const struct rte_flow_action *actions,
1720 enum mlx5_tof_rule_type *rule_type);
1723 #endif /* RTE_PMD_MLX5_FLOW_H_ */