1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* E-Switch Manager port, used for rte_flow_item_port_id. */
22 #define MLX5_PORT_ESW_MGR UINT32_MAX
24 /* Private rte flow items. */
25 enum mlx5_rte_flow_item_type {
26 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
28 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
29 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
30 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
33 /* Private (internal) rte flow actions. */
34 enum mlx5_rte_flow_action_type {
35 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
36 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
37 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
38 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
39 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
41 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
43 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
46 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
49 MLX5_INDIRECT_ACTION_TYPE_RSS,
50 MLX5_INDIRECT_ACTION_TYPE_AGE,
51 MLX5_INDIRECT_ACTION_TYPE_COUNT,
52 MLX5_INDIRECT_ACTION_TYPE_CT,
55 /* Now, the maximal ports will be supported is 256, action number is 4M. */
56 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100
58 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22
59 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)
61 /* 30-31: type, 22-29: owner port, 0-21: index. */
62 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \
63 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \
64 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \
65 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index))
67 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \
68 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \
69 MLX5_INDIRECT_ACT_CT_OWNER_MASK)
71 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \
72 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))
74 /* Matches on selected register. */
75 struct mlx5_rte_flow_item_tag {
80 /* Modify selected register. */
81 struct mlx5_rte_flow_action_set_tag {
88 struct mlx5_flow_action_copy_mreg {
93 /* Matches on source queue. */
94 struct mlx5_rte_flow_item_tx_queue {
98 /* Feature name to allocate metadata register. */
99 enum mlx5_feature_name {
115 /* Default queue number. */
116 #define MLX5_RSSQ_DEFAULT_NUM 16
118 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
119 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
120 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
121 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
122 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
123 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
125 /* Pattern inner Layer bits. */
126 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
127 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
128 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
129 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
130 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
131 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
133 /* Pattern tunnel Layer bits. */
134 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
135 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
136 #define MLX5_FLOW_LAYER_GRE (1u << 14)
137 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
138 /* List of tunnel Layer bits continued below. */
140 /* General pattern items bits. */
141 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
142 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
143 #define MLX5_FLOW_ITEM_TAG (1u << 18)
144 #define MLX5_FLOW_ITEM_MARK (1u << 19)
146 /* Pattern MISC bits. */
147 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
148 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
149 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
151 /* Pattern tunnel Layer bits (continued). */
152 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
153 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
154 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
155 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
158 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
160 /* Pattern tunnel Layer bits (continued). */
161 #define MLX5_FLOW_LAYER_GTP (1u << 28)
163 /* Pattern eCPRI Layer bit. */
164 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
166 /* IPv6 Fragment Extension Header bit. */
167 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
168 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
170 /* Pattern tunnel Layer bits (continued). */
171 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
172 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
174 /* INTEGRITY item bits */
175 #define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34)
176 #define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35)
177 #define MLX5_FLOW_ITEM_INTEGRITY \
178 (MLX5_FLOW_ITEM_OUTER_INTEGRITY | MLX5_FLOW_ITEM_INNER_INTEGRITY)
180 /* Conntrack item. */
181 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36)
184 #define MLX5_FLOW_ITEM_OUTER_FLEX (UINT64_C(1) << 37)
185 #define MLX5_FLOW_ITEM_INNER_FLEX (UINT64_C(1) << 38)
186 #define MLX5_FLOW_ITEM_FLEX_TUNNEL (UINT64_C(1) << 39)
189 #define MLX5_FLOW_LAYER_OUTER_L3 \
190 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
191 #define MLX5_FLOW_LAYER_OUTER_L4 \
192 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
193 #define MLX5_FLOW_LAYER_OUTER \
194 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
195 MLX5_FLOW_LAYER_OUTER_L4)
198 #define MLX5_FLOW_LAYER_TUNNEL \
199 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
200 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
201 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
202 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP | \
203 MLX5_FLOW_ITEM_FLEX_TUNNEL)
206 #define MLX5_FLOW_LAYER_INNER_L3 \
207 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
208 #define MLX5_FLOW_LAYER_INNER_L4 \
209 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
210 #define MLX5_FLOW_LAYER_INNER \
211 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
212 MLX5_FLOW_LAYER_INNER_L4)
215 #define MLX5_FLOW_LAYER_L2 \
216 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
217 #define MLX5_FLOW_LAYER_L3_IPV4 \
218 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
219 #define MLX5_FLOW_LAYER_L3_IPV6 \
220 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
221 #define MLX5_FLOW_LAYER_L3 \
222 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
223 #define MLX5_FLOW_LAYER_L4 \
224 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
227 #define MLX5_FLOW_ACTION_DROP (1u << 0)
228 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
229 #define MLX5_FLOW_ACTION_RSS (1u << 2)
230 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
231 #define MLX5_FLOW_ACTION_MARK (1u << 4)
232 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
233 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
234 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
235 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
236 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
237 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
238 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
239 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
240 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
241 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
242 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
243 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
244 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
245 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
246 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
247 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
248 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
249 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
250 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
251 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
252 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
253 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
254 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
255 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
256 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
257 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
258 #define MLX5_FLOW_ACTION_METER (1ull << 31)
259 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
260 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
261 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
262 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
263 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
264 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
265 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
266 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
267 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
268 #define MLX5_FLOW_ACTION_CT (1ull << 41)
270 #define MLX5_FLOW_FATE_ACTIONS \
271 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
272 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
273 MLX5_FLOW_ACTION_DEFAULT_MISS | \
274 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
276 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
277 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
278 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
280 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
281 MLX5_FLOW_ACTION_SET_IPV4_DST | \
282 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
283 MLX5_FLOW_ACTION_SET_IPV6_DST | \
284 MLX5_FLOW_ACTION_SET_TP_SRC | \
285 MLX5_FLOW_ACTION_SET_TP_DST | \
286 MLX5_FLOW_ACTION_SET_TTL | \
287 MLX5_FLOW_ACTION_DEC_TTL | \
288 MLX5_FLOW_ACTION_SET_MAC_SRC | \
289 MLX5_FLOW_ACTION_SET_MAC_DST | \
290 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
291 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
292 MLX5_FLOW_ACTION_INC_TCP_ACK | \
293 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
294 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
295 MLX5_FLOW_ACTION_SET_TAG | \
296 MLX5_FLOW_ACTION_MARK_EXT | \
297 MLX5_FLOW_ACTION_SET_META | \
298 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
299 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
300 MLX5_FLOW_ACTION_MODIFY_FIELD)
302 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
303 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
305 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
308 #define IPPROTO_MPLS 137
311 /* UDP port number for MPLS */
312 #define MLX5_UDP_PORT_MPLS 6635
314 /* UDP port numbers for VxLAN. */
315 #define MLX5_UDP_PORT_VXLAN 4789
316 #define MLX5_UDP_PORT_VXLAN_GPE 4790
318 /* UDP port numbers for GENEVE. */
319 #define MLX5_UDP_PORT_GENEVE 6081
321 /* Lowest priority indicator. */
322 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
325 * Max priority for ingress\egress flow groups
326 * greater than 0 and for any transfer flow group.
327 * From user configation: 0 - 21843.
329 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
332 * Number of sub priorities.
333 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
334 * matching on the NIC (firmware dependent) L4 most have the higher priority
335 * followed by L3 and ending with L2.
337 #define MLX5_PRIORITY_MAP_L2 2
338 #define MLX5_PRIORITY_MAP_L3 1
339 #define MLX5_PRIORITY_MAP_L4 0
340 #define MLX5_PRIORITY_MAP_MAX 3
342 /* Valid layer type for IPV4 RSS. */
343 #define MLX5_IPV4_LAYER_TYPES \
344 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \
345 RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
346 RTE_ETH_RSS_NONFRAG_IPV4_OTHER)
348 /* IBV hash source bits for IPV4. */
349 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
351 /* Valid layer type for IPV6 RSS. */
352 #define MLX5_IPV6_LAYER_TYPES \
353 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
354 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | \
355 RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER)
357 /* IBV hash source bits for IPV6. */
358 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
360 /* IBV hash bits for L3 SRC. */
361 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
363 /* IBV hash bits for L3 DST. */
364 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
366 /* IBV hash bits for TCP. */
367 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
368 IBV_RX_HASH_DST_PORT_TCP)
370 /* IBV hash bits for UDP. */
371 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
372 IBV_RX_HASH_DST_PORT_UDP)
374 /* IBV hash bits for L4 SRC. */
375 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
376 IBV_RX_HASH_SRC_PORT_UDP)
378 /* IBV hash bits for L4 DST. */
379 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
380 IBV_RX_HASH_DST_PORT_UDP)
382 /* Geneve header first 16Bit */
383 #define MLX5_GENEVE_VER_MASK 0x3
384 #define MLX5_GENEVE_VER_SHIFT 14
385 #define MLX5_GENEVE_VER_VAL(a) \
386 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
387 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
388 #define MLX5_GENEVE_OPTLEN_SHIFT 8
389 #define MLX5_GENEVE_OPTLEN_VAL(a) \
390 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
391 #define MLX5_GENEVE_OAMF_MASK 0x1
392 #define MLX5_GENEVE_OAMF_SHIFT 7
393 #define MLX5_GENEVE_OAMF_VAL(a) \
394 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
395 #define MLX5_GENEVE_CRITO_MASK 0x1
396 #define MLX5_GENEVE_CRITO_SHIFT 6
397 #define MLX5_GENEVE_CRITO_VAL(a) \
398 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
399 #define MLX5_GENEVE_RSVD_MASK 0x3F
400 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
402 * The length of the Geneve options fields, expressed in four byte multiples,
403 * not including the eight byte fixed tunnel.
405 #define MLX5_GENEVE_OPT_LEN_0 14
406 #define MLX5_GENEVE_OPT_LEN_1 63
408 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
409 sizeof(struct rte_ipv4_hdr))
410 /* GTP extension header flag. */
411 #define MLX5_GTP_EXT_HEADER_FLAG 4
413 /* GTP extension header PDU type shift. */
414 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
416 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
417 #define MLX5_IPV4_FRAG_OFFSET_MASK \
418 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
420 /* Specific item's fields can accept a range of values (using spec and last). */
421 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
422 #define MLX5_ITEM_RANGE_ACCEPTED true
424 /* Software header modify action numbers of a flow. */
425 #define MLX5_ACT_NUM_MDF_IPV4 1
426 #define MLX5_ACT_NUM_MDF_IPV6 4
427 #define MLX5_ACT_NUM_MDF_MAC 2
428 #define MLX5_ACT_NUM_MDF_VID 1
429 #define MLX5_ACT_NUM_MDF_PORT 2
430 #define MLX5_ACT_NUM_MDF_TTL 1
431 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
432 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
433 #define MLX5_ACT_NUM_MDF_TCPACK 1
434 #define MLX5_ACT_NUM_SET_REG 1
435 #define MLX5_ACT_NUM_SET_TAG 1
436 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
437 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
438 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
439 #define MLX5_ACT_NUM_SET_DSCP 1
441 /* Maximum number of fields to modify in MODIFY_FIELD */
442 #define MLX5_ACT_MAX_MOD_FIELDS 5
444 /* Syndrome bits definition for connection tracking. */
445 #define MLX5_CT_SYNDROME_VALID (0x0 << 6)
446 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6)
447 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6)
448 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1)
449 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0)
451 enum mlx5_flow_drv_type {
454 MLX5_FLOW_TYPE_VERBS,
459 /* Fate action type. */
460 enum mlx5_flow_fate_type {
461 MLX5_FLOW_FATE_NONE, /* Egress flow. */
462 MLX5_FLOW_FATE_QUEUE,
464 MLX5_FLOW_FATE_PORT_ID,
466 MLX5_FLOW_FATE_DEFAULT_MISS,
467 MLX5_FLOW_FATE_SHARED_RSS,
472 /* Matcher PRM representation */
473 struct mlx5_flow_dv_match_params {
475 /**< Size of match value. Do NOT split size and key! */
476 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
477 /**< Matcher value. This value is used as the mask or as a key. */
480 /* Matcher structure. */
481 struct mlx5_flow_dv_matcher {
482 struct mlx5_list_entry entry; /**< Pointer to the next element. */
483 struct mlx5_flow_tbl_resource *tbl;
484 /**< Pointer to the table(group) the matcher associated with. */
485 void *matcher_object; /**< Pointer to DV matcher */
486 uint16_t crc; /**< CRC of key. */
487 uint16_t priority; /**< Priority of matcher. */
488 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
491 #define MLX5_ENCAP_MAX_LEN 132
493 /* Encap/decap resource structure. */
494 struct mlx5_flow_dv_encap_decap_resource {
495 struct mlx5_list_entry entry;
496 /* Pointer to next element. */
497 uint32_t refcnt; /**< Reference counter. */
499 /**< Encap/decap action object. */
500 uint8_t buf[MLX5_ENCAP_MAX_LEN];
502 uint8_t reformat_type;
504 uint64_t flags; /**< Flags for RDMA API. */
505 uint32_t idx; /**< Index for the index memory pool. */
508 /* Tag resource structure. */
509 struct mlx5_flow_dv_tag_resource {
510 struct mlx5_list_entry entry;
511 /**< hash list entry for tag resource, tag value as the key. */
513 /**< Tag action object. */
514 uint32_t refcnt; /**< Reference counter. */
515 uint32_t idx; /**< Index for the index memory pool. */
516 uint32_t tag_id; /**< Tag ID. */
519 /* Modify resource structure */
520 struct mlx5_flow_dv_modify_hdr_resource {
521 struct mlx5_list_entry entry;
522 void *action; /**< Modify header action object. */
524 /* Key area for hash list matching: */
525 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
526 uint8_t actions_num; /**< Number of modification actions. */
527 bool root; /**< Whether action is in root table. */
528 struct mlx5_modification_cmd actions[];
529 /**< Modification actions. */
532 /* Modify resource key of the hash organization. */
533 union mlx5_flow_modify_hdr_key {
535 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
536 uint32_t actions_num:5; /**< Number of modification actions. */
537 uint32_t group:19; /**< Flow group id. */
538 uint32_t cksum; /**< Actions check sum. */
540 uint64_t v64; /**< full 64bits value of key */
543 /* Jump action resource structure. */
544 struct mlx5_flow_dv_jump_tbl_resource {
545 void *action; /**< Pointer to the rdma core action. */
548 /* Port ID resource structure. */
549 struct mlx5_flow_dv_port_id_action_resource {
550 struct mlx5_list_entry entry;
551 void *action; /**< Action object. */
552 uint32_t port_id; /**< Port ID value. */
553 uint32_t idx; /**< Indexed pool memory index. */
556 /* Push VLAN action resource structure */
557 struct mlx5_flow_dv_push_vlan_action_resource {
558 struct mlx5_list_entry entry; /* Cache entry. */
559 void *action; /**< Action object. */
560 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
561 rte_be32_t vlan_tag; /**< VLAN tag value. */
562 uint32_t idx; /**< Indexed pool memory index. */
565 /* Metadata register copy table entry. */
566 struct mlx5_flow_mreg_copy_resource {
568 * Hash list entry for copy table.
569 * - Key is 32/64-bit MARK action ID.
570 * - MUST be the first entry.
572 struct mlx5_list_entry hlist_ent;
573 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
574 /* List entry for device flows. */
576 uint32_t rix_flow; /* Built flow for copy. */
580 /* Table tunnel parameter. */
581 struct mlx5_flow_tbl_tunnel_prm {
582 const struct mlx5_flow_tunnel *tunnel;
587 /* Table data structure of the hash organization. */
588 struct mlx5_flow_tbl_data_entry {
589 struct mlx5_list_entry entry;
590 /**< hash list entry, 64-bits key inside. */
591 struct mlx5_flow_tbl_resource tbl;
592 /**< flow table resource. */
593 struct mlx5_list *matchers;
594 /**< matchers' header associated with the flow table. */
595 struct mlx5_flow_dv_jump_tbl_resource jump;
596 /**< jump resource, at most one for each table created. */
597 uint32_t idx; /**< index for the indexed mempool. */
598 /**< tunnel offload */
599 const struct mlx5_flow_tunnel *tunnel;
602 uint32_t tunnel_offload:1; /* Tunnel offload table or not. */
603 uint32_t is_egress:1; /**< Egress table. */
604 uint32_t is_transfer:1; /**< Transfer table. */
605 uint32_t dummy:1; /**< DR table. */
606 uint32_t id:22; /**< Table ID. */
607 uint32_t reserve:5; /**< Reserved to future using. */
608 uint32_t level; /**< Table level. */
611 /* Sub rdma-core actions list. */
612 struct mlx5_flow_sub_actions_list {
613 uint32_t actions_num; /**< Number of sample actions. */
614 uint64_t action_flags;
615 void *dr_queue_action;
618 void *dr_port_id_action;
619 void *dr_encap_action;
620 void *dr_jump_action;
623 /* Sample sub-actions resource list. */
624 struct mlx5_flow_sub_actions_idx {
625 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
626 uint32_t rix_tag; /**< Index to the tag action. */
627 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
628 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
629 uint32_t rix_jump; /**< Index to the jump action resource. */
632 /* Sample action resource structure. */
633 struct mlx5_flow_dv_sample_resource {
634 struct mlx5_list_entry entry; /**< Cache entry. */
636 void *verbs_action; /**< Verbs sample action object. */
637 void **sub_actions; /**< Sample sub-action array. */
639 struct rte_eth_dev *dev; /**< Device registers the action. */
640 uint32_t idx; /** Sample object index. */
641 uint8_t ft_type; /** Flow Table Type */
642 uint32_t ft_id; /** Flow Table Level */
643 uint32_t ratio; /** Sample Ratio */
644 uint64_t set_action; /** Restore reg_c0 value */
645 void *normal_path_tbl; /** Flow Table pointer */
646 struct mlx5_flow_sub_actions_idx sample_idx;
647 /**< Action index resources. */
648 struct mlx5_flow_sub_actions_list sample_act;
649 /**< Action resources. */
652 #define MLX5_MAX_DEST_NUM 2
654 /* Destination array action resource structure. */
655 struct mlx5_flow_dv_dest_array_resource {
656 struct mlx5_list_entry entry; /**< Cache entry. */
657 uint32_t idx; /** Destination array action object index. */
658 uint8_t ft_type; /** Flow Table Type */
659 uint8_t num_of_dest; /**< Number of destination actions. */
660 struct rte_eth_dev *dev; /**< Device registers the action. */
661 void *action; /**< Pointer to the rdma core action. */
662 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
663 /**< Action index resources. */
664 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
665 /**< Action resources. */
668 /* PMD flow priority for tunnel */
669 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
670 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
673 /** Device flow handle structure for DV mode only. */
674 struct mlx5_flow_handle_dv {
676 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
677 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
678 /**< Pointer to modify header resource in cache. */
679 uint32_t rix_encap_decap;
680 /**< Index to encap/decap resource in cache. */
681 uint32_t rix_push_vlan;
682 /**< Index to push VLAN action resource in cache. */
684 /**< Index to the tag action. */
686 /**< Index to sample action resource in cache. */
687 uint32_t rix_dest_array;
688 /**< Index to destination array resource in cache. */
691 /** Device flow handle structure: used both for creating & destroying. */
692 struct mlx5_flow_handle {
693 SILIST_ENTRY(uint32_t)next;
694 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
695 /**< Index to next device flow handle. */
697 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
698 void *drv_flow; /**< pointer to driver flow object. */
699 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
700 uint32_t is_meter_flow_id:1; /**< Indicate if flow_id is for meter. */
701 uint32_t fate_action:3; /**< Fate action type. */
702 uint32_t flex_item; /**< referenced Flex Item bitmask. */
704 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
705 uint32_t rix_jump; /**< Index to the jump action resource. */
706 uint32_t rix_port_id_action;
707 /**< Index to port ID action resource. */
709 /**< Generic value indicates the fate action. */
710 uint32_t rix_default_fate;
711 /**< Indicates default miss fate action. */
713 /**< Indicates shared RSS fate action. */
715 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
716 struct mlx5_flow_handle_dv dvh;
721 * Size for Verbs device flow handle structure only. Do not use the DV only
722 * structure in Verbs. No DV flows attributes will be accessed.
723 * Macro offsetof() could also be used here.
725 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
726 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
727 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
729 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
732 /** Device flow structure only for DV flow creation. */
733 struct mlx5_flow_dv_workspace {
734 uint32_t group; /**< The group index. */
735 uint32_t table_id; /**< Flow table identifier. */
736 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
737 int actions_n; /**< number of actions. */
738 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
739 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
740 /**< Pointer to encap/decap resource in cache. */
741 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
742 /**< Pointer to push VLAN action resource in cache. */
743 struct mlx5_flow_dv_tag_resource *tag_resource;
744 /**< pointer to the tag action. */
745 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
746 /**< Pointer to port ID action resource. */
747 struct mlx5_flow_dv_jump_tbl_resource *jump;
748 /**< Pointer to the jump action resource. */
749 struct mlx5_flow_dv_match_params value;
750 /**< Holds the value that the packet is compared to. */
751 struct mlx5_flow_dv_sample_resource *sample_res;
752 /**< Pointer to the sample action resource. */
753 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
754 /**< Pointer to the destination array resource. */
757 #ifdef HAVE_INFINIBAND_VERBS_H
759 * Maximal Verbs flow specifications & actions size.
760 * Some elements are mutually exclusive, but enough space should be allocated.
761 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
762 * 2. One tunnel header (exception: GRE + MPLS),
763 * SPEC length: GRE == tunnel.
764 * Actions: 1. 1 Mark OR Flag.
765 * 2. 1 Drop (if any).
766 * 3. No limitation for counters, but it makes no sense to support too
767 * many counters in a single device flow.
769 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
770 #define MLX5_VERBS_MAX_SPEC_SIZE \
772 (2 * (sizeof(struct ibv_flow_spec_eth) + \
773 sizeof(struct ibv_flow_spec_ipv6) + \
774 sizeof(struct ibv_flow_spec_tcp_udp)) + \
775 sizeof(struct ibv_flow_spec_gre) + \
776 sizeof(struct ibv_flow_spec_mpls)) \
779 #define MLX5_VERBS_MAX_SPEC_SIZE \
781 (2 * (sizeof(struct ibv_flow_spec_eth) + \
782 sizeof(struct ibv_flow_spec_ipv6) + \
783 sizeof(struct ibv_flow_spec_tcp_udp)) + \
784 sizeof(struct ibv_flow_spec_tunnel)) \
788 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
789 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
790 #define MLX5_VERBS_MAX_ACT_SIZE \
792 sizeof(struct ibv_flow_spec_action_tag) + \
793 sizeof(struct ibv_flow_spec_action_drop) + \
794 sizeof(struct ibv_flow_spec_counter_action) * 4 \
797 #define MLX5_VERBS_MAX_ACT_SIZE \
799 sizeof(struct ibv_flow_spec_action_tag) + \
800 sizeof(struct ibv_flow_spec_action_drop) \
804 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
805 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
807 /** Device flow structure only for Verbs flow creation. */
808 struct mlx5_flow_verbs_workspace {
809 unsigned int size; /**< Size of the attribute. */
810 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
811 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
812 /**< Specifications & actions buffer of verbs flow. */
814 #endif /* HAVE_INFINIBAND_VERBS_H */
816 #define MLX5_SCALE_FLOW_GROUP_BIT 0
817 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
819 /** Maximal number of device sub-flows supported. */
820 #define MLX5_NUM_MAX_DEV_FLOWS 32
823 * tunnel offload rules type
825 enum mlx5_tof_rule_type {
826 MLX5_TUNNEL_OFFLOAD_NONE = 0,
827 MLX5_TUNNEL_OFFLOAD_SET_RULE,
828 MLX5_TUNNEL_OFFLOAD_MATCH_RULE,
829 MLX5_TUNNEL_OFFLOAD_MISS_RULE,
832 /** Device flow structure. */
835 struct rte_flow *flow; /**< Pointer to the main flow. */
836 uint32_t flow_idx; /**< The memory pool index to the main flow. */
837 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
839 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
840 bool external; /**< true if the flow is created external to PMD. */
841 uint8_t ingress:1; /**< 1 if the flow is ingress. */
842 uint8_t skip_scale:2;
844 * Each Bit be set to 1 if Skip the scale the flow group with factor.
845 * If bit0 be set to 1, then skip the scale the original flow group;
846 * If bit1 be set to 1, then skip the scale the jump flow group if
847 * having jump action.
848 * 00: Enable scale in a flow, default value.
849 * 01: Skip scale the flow group with factor, enable scale the group
851 * 10: Enable scale the group with factor, skip scale the group of
853 * 11: Skip scale the table with factor both for flow group and jump
857 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
858 struct mlx5_flow_dv_workspace dv;
860 #ifdef HAVE_INFINIBAND_VERBS_H
861 struct mlx5_flow_verbs_workspace verbs;
864 struct mlx5_flow_handle *handle;
865 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
866 const struct mlx5_flow_tunnel *tunnel;
867 enum mlx5_tof_rule_type tof_type;
870 /* Flow meter state. */
871 #define MLX5_FLOW_METER_DISABLE 0
872 #define MLX5_FLOW_METER_ENABLE 1
874 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
875 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
877 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
879 #define MLX5_MAN_WIDTH 8
880 /* Legacy Meter parameter structure. */
881 struct mlx5_legacy_flow_meter {
882 struct mlx5_flow_meter_info fm;
883 /* Must be the first in struct. */
884 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
885 /**< Pointer to the next flow meter structure. */
887 /* Index to meter object. */
890 #define MLX5_MAX_TUNNELS 256
891 #define MLX5_TNL_MISS_RULE_PRIORITY 3
892 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
895 * When tunnel offload is active, all JUMP group ids are converted
896 * using the same method. That conversion is applied both to tunnel and
897 * regular rule types.
898 * Group ids used in tunnel rules are relative to it's tunnel (!).
899 * Application can create number of steer rules, using the same
900 * tunnel, with different group id in each rule.
901 * Each tunnel stores its groups internally in PMD tunnel object.
902 * Groups used in regular rules do not belong to any tunnel and are stored
906 struct mlx5_flow_tunnel {
907 LIST_ENTRY(mlx5_flow_tunnel) chain;
908 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
909 uint32_t tunnel_id; /** unique tunnel ID */
911 struct rte_flow_action action;
912 struct rte_flow_item item;
913 struct mlx5_hlist *groups; /** tunnel groups */
916 /** PMD tunnel related context */
917 struct mlx5_flow_tunnel_hub {
919 * Access to the list MUST be MT protected
921 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
922 /* protect access to the tunnels list */
924 struct mlx5_hlist *groups; /** non tunnel groups */
927 /* convert jump group to flow table ID in tunnel rules */
928 struct tunnel_tbl_entry {
929 struct mlx5_list_entry hash;
935 static inline uint32_t
936 tunnel_id_to_flow_tbl(uint32_t id)
938 return id | (1u << 16);
941 static inline uint32_t
942 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
944 return flow_tbl & ~(1u << 16);
947 union tunnel_tbl_key {
955 static inline struct mlx5_flow_tunnel_hub *
956 mlx5_tunnel_hub(struct rte_eth_dev *dev)
958 struct mlx5_priv *priv = dev->data->dev_private;
959 return priv->sh->tunnel_hub;
963 is_tunnel_offload_active(const struct rte_eth_dev *dev)
965 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
966 const struct mlx5_priv *priv = dev->data->dev_private;
967 return !!priv->sh->config.dv_miss_info;
975 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type)
977 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE;
981 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type)
983 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE;
986 static inline const struct mlx5_flow_tunnel *
987 flow_actions_to_tunnel(const struct rte_flow_action actions[])
989 return actions[0].conf;
992 static inline const struct mlx5_flow_tunnel *
993 flow_items_to_tunnel(const struct rte_flow_item items[])
995 return items[0].spec;
998 /* Flow structure. */
1000 uint32_t dev_handles;
1001 /**< Device flow handles that are part of the flow. */
1003 uint32_t drv_type:2; /**< Driver type. */
1005 uint32_t meter:24; /**< Holds flow meter id. */
1006 uint32_t indirect_type:2; /**< Indirect action type. */
1007 uint32_t rix_mreg_copy;
1008 /**< Index to metadata register copy table resource. */
1009 uint32_t counter; /**< Holds flow counter. */
1010 uint32_t tunnel_id; /**< Tunnel id */
1012 uint32_t age; /**< Holds ASO age bit index. */
1013 uint32_t ct; /**< Holds ASO CT index. */
1015 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1019 * Define list of valid combinations of RX Hash fields
1020 * (see enum ibv_rx_hash_fields).
1022 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1023 #define MLX5_RSS_HASH_IPV4_TCP \
1024 (MLX5_RSS_HASH_IPV4 | \
1025 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1026 #define MLX5_RSS_HASH_IPV4_UDP \
1027 (MLX5_RSS_HASH_IPV4 | \
1028 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1029 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1030 #define MLX5_RSS_HASH_IPV6_TCP \
1031 (MLX5_RSS_HASH_IPV6 | \
1032 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1033 #define MLX5_RSS_HASH_IPV6_UDP \
1034 (MLX5_RSS_HASH_IPV6 | \
1035 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1036 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1037 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1038 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1039 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1040 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1041 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1042 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1043 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1044 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1045 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1046 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1047 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1048 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1049 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1050 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1051 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1052 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1053 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1054 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1055 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1056 #define MLX5_RSS_HASH_NONE 0ULL
1059 /* extract next protocol type from Ethernet & VLAN headers */
1060 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1061 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1062 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1063 (_prt) = rte_be_to_cpu_16((_prt)); \
1066 /* array of valid combinations of RX Hash fields for RSS */
1067 static const uint64_t mlx5_rss_hash_fields[] = {
1069 MLX5_RSS_HASH_IPV4_TCP,
1070 MLX5_RSS_HASH_IPV4_UDP,
1072 MLX5_RSS_HASH_IPV6_TCP,
1073 MLX5_RSS_HASH_IPV6_UDP,
1077 /* Shared RSS action structure */
1078 struct mlx5_shared_action_rss {
1079 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1080 uint32_t refcnt; /**< Atomically accessed refcnt. */
1081 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1082 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1083 struct mlx5_ind_table_obj *ind_tbl;
1084 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1085 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1086 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1087 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1090 struct rte_flow_action_handle {
1094 /* Thread specific flow workspace intermediate data. */
1095 struct mlx5_flow_workspace {
1096 /* If creating another flow in same thread, push new as stack. */
1097 struct mlx5_flow_workspace *prev;
1098 struct mlx5_flow_workspace *next;
1099 uint32_t inuse; /* can't create new flow with current. */
1100 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1101 struct mlx5_flow_rss_desc rss_desc;
1102 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1103 uint32_t flow_idx; /* Intermediate device flow index. */
1104 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1105 struct mlx5_flow_meter_policy *policy;
1106 /* The meter policy used by meter in flow. */
1107 struct mlx5_flow_meter_policy *final_policy;
1108 /* The final policy when meter policy is hierarchy. */
1109 uint32_t skip_matcher_reg:1;
1110 /* Indicates if need to skip matcher register in translate. */
1111 uint32_t mark:1; /* Indicates if flow contains mark action. */
1114 struct mlx5_flow_split_info {
1115 uint32_t external:1;
1116 /**< True if flow is created by request external to PMD. */
1117 uint32_t prefix_mark:1; /**< Prefix subflow mark flag. */
1118 uint32_t skip_scale:8; /**< Skip the scale the table with factor. */
1119 uint32_t flow_idx; /**< This memory pool index to the flow. */
1120 uint32_t table_id; /**< Flow table identifier. */
1121 uint64_t prefix_layers; /**< Prefix subflow layers. */
1124 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1125 const struct rte_flow_attr *attr,
1126 const struct rte_flow_item items[],
1127 const struct rte_flow_action actions[],
1130 struct rte_flow_error *error);
1131 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1132 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1133 const struct rte_flow_item items[],
1134 const struct rte_flow_action actions[], struct rte_flow_error *error);
1135 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1136 struct mlx5_flow *dev_flow,
1137 const struct rte_flow_attr *attr,
1138 const struct rte_flow_item items[],
1139 const struct rte_flow_action actions[],
1140 struct rte_flow_error *error);
1141 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1142 struct rte_flow_error *error);
1143 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1144 struct rte_flow *flow);
1145 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1146 struct rte_flow *flow);
1147 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1148 struct rte_flow *flow,
1149 const struct rte_flow_action *actions,
1151 struct rte_flow_error *error);
1152 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1153 struct mlx5_flow_meter_info *fm,
1155 uint8_t domain_bitmap);
1156 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1157 struct mlx5_flow_meter_info *fm);
1158 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1159 typedef struct mlx5_flow_meter_sub_policy *
1160 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1161 (struct rte_eth_dev *dev,
1162 struct mlx5_flow_meter_policy *mtr_policy,
1163 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1164 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t)
1165 (struct rte_eth_dev *dev,
1166 struct mlx5_flow_meter_info *fm,
1168 const struct rte_flow_item *item,
1169 struct rte_flow_error *error);
1170 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t)
1171 (struct rte_eth_dev *dev,
1172 struct mlx5_flow_meter_policy *mtr_policy);
1173 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1174 (struct rte_eth_dev *dev);
1175 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1177 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1178 (struct rte_eth_dev *dev);
1179 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1181 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1183 bool clear, uint64_t *pkts,
1184 uint64_t *bytes, void **action);
1185 typedef int (*mlx5_flow_get_aged_flows_t)
1186 (struct rte_eth_dev *dev,
1188 uint32_t nb_contexts,
1189 struct rte_flow_error *error);
1190 typedef int (*mlx5_flow_action_validate_t)
1191 (struct rte_eth_dev *dev,
1192 const struct rte_flow_indir_action_conf *conf,
1193 const struct rte_flow_action *action,
1194 struct rte_flow_error *error);
1195 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1196 (struct rte_eth_dev *dev,
1197 const struct rte_flow_indir_action_conf *conf,
1198 const struct rte_flow_action *action,
1199 struct rte_flow_error *error);
1200 typedef int (*mlx5_flow_action_destroy_t)
1201 (struct rte_eth_dev *dev,
1202 struct rte_flow_action_handle *action,
1203 struct rte_flow_error *error);
1204 typedef int (*mlx5_flow_action_update_t)
1205 (struct rte_eth_dev *dev,
1206 struct rte_flow_action_handle *action,
1208 struct rte_flow_error *error);
1209 typedef int (*mlx5_flow_action_query_t)
1210 (struct rte_eth_dev *dev,
1211 const struct rte_flow_action_handle *action,
1213 struct rte_flow_error *error);
1214 typedef int (*mlx5_flow_sync_domain_t)
1215 (struct rte_eth_dev *dev,
1218 typedef int (*mlx5_flow_validate_mtr_acts_t)
1219 (struct rte_eth_dev *dev,
1220 const struct rte_flow_action *actions[RTE_COLORS],
1221 struct rte_flow_attr *attr,
1223 uint8_t *domain_bitmap,
1224 uint8_t *policy_mode,
1225 struct rte_mtr_error *error);
1226 typedef int (*mlx5_flow_create_mtr_acts_t)
1227 (struct rte_eth_dev *dev,
1228 struct mlx5_flow_meter_policy *mtr_policy,
1229 const struct rte_flow_action *actions[RTE_COLORS],
1230 struct rte_mtr_error *error);
1231 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1232 (struct rte_eth_dev *dev,
1233 struct mlx5_flow_meter_policy *mtr_policy);
1234 typedef int (*mlx5_flow_create_policy_rules_t)
1235 (struct rte_eth_dev *dev,
1236 struct mlx5_flow_meter_policy *mtr_policy);
1237 typedef void (*mlx5_flow_destroy_policy_rules_t)
1238 (struct rte_eth_dev *dev,
1239 struct mlx5_flow_meter_policy *mtr_policy);
1240 typedef int (*mlx5_flow_create_def_policy_t)
1241 (struct rte_eth_dev *dev);
1242 typedef void (*mlx5_flow_destroy_def_policy_t)
1243 (struct rte_eth_dev *dev);
1244 typedef int (*mlx5_flow_discover_priorities_t)
1245 (struct rte_eth_dev *dev,
1246 const uint16_t *vprio, int vprio_n);
1247 typedef struct rte_flow_item_flex_handle *(*mlx5_flow_item_create_t)
1248 (struct rte_eth_dev *dev,
1249 const struct rte_flow_item_flex_conf *conf,
1250 struct rte_flow_error *error);
1251 typedef int (*mlx5_flow_item_release_t)
1252 (struct rte_eth_dev *dev,
1253 const struct rte_flow_item_flex_handle *handle,
1254 struct rte_flow_error *error);
1255 typedef int (*mlx5_flow_item_update_t)
1256 (struct rte_eth_dev *dev,
1257 const struct rte_flow_item_flex_handle *handle,
1258 const struct rte_flow_item_flex_conf *conf,
1259 struct rte_flow_error *error);
1260 typedef int (*mlx5_flow_info_get_t)
1261 (struct rte_eth_dev *dev,
1262 struct rte_flow_port_info *port_info,
1263 struct rte_flow_queue_info *queue_info,
1264 struct rte_flow_error *error);
1265 typedef int (*mlx5_flow_port_configure_t)
1266 (struct rte_eth_dev *dev,
1267 const struct rte_flow_port_attr *port_attr,
1269 const struct rte_flow_queue_attr *queue_attr[],
1270 struct rte_flow_error *err);
1272 struct mlx5_flow_driver_ops {
1273 mlx5_flow_validate_t validate;
1274 mlx5_flow_prepare_t prepare;
1275 mlx5_flow_translate_t translate;
1276 mlx5_flow_apply_t apply;
1277 mlx5_flow_remove_t remove;
1278 mlx5_flow_destroy_t destroy;
1279 mlx5_flow_query_t query;
1280 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1281 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1282 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1283 mlx5_flow_mtr_alloc_t create_meter;
1284 mlx5_flow_mtr_free_t free_meter;
1285 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1286 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1287 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1288 mlx5_flow_create_policy_rules_t create_policy_rules;
1289 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1290 mlx5_flow_create_def_policy_t create_def_policy;
1291 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1292 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1293 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create;
1294 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq;
1295 mlx5_flow_counter_alloc_t counter_alloc;
1296 mlx5_flow_counter_free_t counter_free;
1297 mlx5_flow_counter_query_t counter_query;
1298 mlx5_flow_get_aged_flows_t get_aged_flows;
1299 mlx5_flow_action_validate_t action_validate;
1300 mlx5_flow_action_create_t action_create;
1301 mlx5_flow_action_destroy_t action_destroy;
1302 mlx5_flow_action_update_t action_update;
1303 mlx5_flow_action_query_t action_query;
1304 mlx5_flow_sync_domain_t sync_domain;
1305 mlx5_flow_discover_priorities_t discover_priorities;
1306 mlx5_flow_item_create_t item_create;
1307 mlx5_flow_item_release_t item_release;
1308 mlx5_flow_item_update_t item_update;
1309 mlx5_flow_info_get_t info_get;
1310 mlx5_flow_port_configure_t configure;
1315 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1317 struct flow_grp_info {
1318 uint64_t external:1;
1319 uint64_t transfer:1;
1320 uint64_t fdb_def_rule:1;
1321 /* force standard group translation */
1322 uint64_t std_tbl_fix:1;
1323 uint64_t skip_scale:2;
1327 tunnel_use_standard_attr_group_translate
1328 (const struct rte_eth_dev *dev,
1329 const struct rte_flow_attr *attr,
1330 const struct mlx5_flow_tunnel *tunnel,
1331 enum mlx5_tof_rule_type tof_rule_type)
1335 if (!is_tunnel_offload_active(dev))
1336 /* no tunnel offload API */
1340 * OvS will use jump to group 0 in tunnel steer rule.
1341 * If tunnel steer rule starts from group 0 (attr.group == 0)
1342 * that 0 group must be translated with standard method.
1343 * attr.group == 0 in tunnel match rule translated with tunnel
1346 verdict = !attr->group &&
1347 is_flow_tunnel_steer_rule(tof_rule_type);
1350 * non-tunnel group translation uses standard method for
1351 * root group only: attr.group == 0
1353 verdict = !attr->group;
1360 * Get DV flow aso meter by index.
1363 * Pointer to the Ethernet device structure.
1365 * mlx5 flow aso meter index in the container.
1367 * mlx5 flow aso meter pool in the container,
1370 * Pointer to the aso meter, NULL otherwise.
1372 static inline struct mlx5_aso_mtr *
1373 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1375 struct mlx5_aso_mtr_pool *pool;
1376 struct mlx5_aso_mtr_pools_mng *pools_mng =
1377 &priv->sh->mtrmng->pools_mng;
1379 /* Decrease to original index. */
1381 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1382 rte_rwlock_read_lock(&pools_mng->resize_mtrwl);
1383 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1384 rte_rwlock_read_unlock(&pools_mng->resize_mtrwl);
1385 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1388 static __rte_always_inline const struct rte_flow_item *
1389 mlx5_find_end_item(const struct rte_flow_item *item)
1391 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1395 static __rte_always_inline bool
1396 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1398 struct rte_flow_item_integrity test = *item;
1401 test.ipv4_csum_ok = 0;
1402 test.l4_csum_ok = 0;
1403 return (test.value == 0);
1407 * Get ASO CT action by device and index.
1410 * Pointer to the Ethernet device structure.
1412 * Index to the ASO CT action.
1415 * The specified ASO CT action pointer.
1417 static inline struct mlx5_aso_ct_action *
1418 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx)
1420 struct mlx5_priv *priv = dev->data->dev_private;
1421 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
1422 struct mlx5_aso_ct_pool *pool;
1425 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n);
1426 /* Bit operation AND could be used. */
1427 rte_rwlock_read_lock(&mng->resize_rwl);
1428 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL];
1429 rte_rwlock_read_unlock(&mng->resize_rwl);
1430 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];
1434 * Get ASO CT action by owner & index.
1437 * Pointer to the Ethernet device structure.
1439 * Index to the ASO CT action and owner port combination.
1442 * The specified ASO CT action pointer.
1444 static inline struct mlx5_aso_ct_action *
1445 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx)
1447 struct mlx5_priv *priv = dev->data->dev_private;
1448 struct mlx5_aso_ct_action *ct;
1449 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
1450 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
1452 if (owner == PORT_ID(priv)) {
1453 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
1455 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
1457 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
1458 if (dev->data->dev_started != 1)
1460 ct = flow_aso_ct_get_by_dev_idx(owndev, idx);
1461 if (ct->peer != PORT_ID(priv))
1467 static inline uint16_t
1468 mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
1470 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
1471 return RTE_ETHER_TYPE_TEB;
1472 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
1473 return RTE_ETHER_TYPE_IPV4;
1474 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
1475 return RTE_ETHER_TYPE_IPV6;
1476 else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
1477 return RTE_ETHER_TYPE_MPLS;
1481 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1482 const struct mlx5_flow_tunnel *tunnel,
1483 uint32_t group, uint32_t *table,
1484 const struct flow_grp_info *flags,
1485 struct rte_flow_error *error);
1486 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1487 int tunnel, uint64_t layer_types,
1488 uint64_t hash_fields);
1489 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1490 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1491 uint32_t subpriority);
1492 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1493 const struct rte_flow_attr *attr);
1494 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1495 const struct rte_flow_attr *attr,
1496 uint32_t subpriority, bool external);
1497 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1498 enum mlx5_feature_name feature,
1500 struct rte_flow_error *error);
1501 const struct rte_flow_action *mlx5_flow_find_action
1502 (const struct rte_flow_action *actions,
1503 enum rte_flow_action_type action);
1504 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1505 const struct rte_flow_action *action,
1506 struct rte_flow_error *error);
1507 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1508 const struct rte_flow_attr *attr,
1509 struct rte_flow_error *error);
1510 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1511 const struct rte_flow_attr *attr,
1512 struct rte_flow_error *error);
1513 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1514 const struct rte_flow_attr *attr,
1515 struct rte_flow_error *error);
1516 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1517 uint64_t action_flags,
1518 const struct rte_flow_attr *attr,
1519 struct rte_flow_error *error);
1520 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1521 uint64_t action_flags,
1522 struct rte_eth_dev *dev,
1523 const struct rte_flow_attr *attr,
1524 struct rte_flow_error *error);
1525 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1526 uint64_t action_flags,
1527 struct rte_eth_dev *dev,
1528 const struct rte_flow_attr *attr,
1529 uint64_t item_flags,
1530 struct rte_flow_error *error);
1531 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1532 const struct rte_flow_attr *attr,
1533 struct rte_flow_error *error);
1534 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1535 const struct rte_flow_attr *attributes,
1536 struct rte_flow_error *error);
1537 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1538 const uint8_t *mask,
1539 const uint8_t *nic_mask,
1541 bool range_accepted,
1542 struct rte_flow_error *error);
1543 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1544 uint64_t item_flags, bool ext_vlan_sup,
1545 struct rte_flow_error *error);
1546 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1547 uint64_t item_flags,
1548 uint8_t target_protocol,
1549 struct rte_flow_error *error);
1550 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1551 uint64_t item_flags,
1552 const struct rte_flow_item *gre_item,
1553 struct rte_flow_error *error);
1554 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1555 uint64_t item_flags,
1557 uint16_t ether_type,
1558 const struct rte_flow_item_ipv4 *acc_mask,
1559 bool range_accepted,
1560 struct rte_flow_error *error);
1561 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1562 uint64_t item_flags,
1564 uint16_t ether_type,
1565 const struct rte_flow_item_ipv6 *acc_mask,
1566 struct rte_flow_error *error);
1567 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1568 const struct rte_flow_item *item,
1569 uint64_t item_flags,
1570 uint64_t prev_layer,
1571 struct rte_flow_error *error);
1572 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1573 uint64_t item_flags,
1574 uint8_t target_protocol,
1575 const struct rte_flow_item_tcp *flow_mask,
1576 struct rte_flow_error *error);
1577 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1578 uint64_t item_flags,
1579 uint8_t target_protocol,
1580 struct rte_flow_error *error);
1581 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1582 uint64_t item_flags,
1583 struct rte_eth_dev *dev,
1584 struct rte_flow_error *error);
1585 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev,
1587 const struct rte_flow_item *item,
1588 uint64_t item_flags,
1589 const struct rte_flow_attr *attr,
1590 struct rte_flow_error *error);
1591 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1592 uint64_t item_flags,
1593 struct rte_eth_dev *dev,
1594 struct rte_flow_error *error);
1595 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1596 uint64_t item_flags,
1597 uint8_t target_protocol,
1598 struct rte_flow_error *error);
1599 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1600 uint64_t item_flags,
1601 uint8_t target_protocol,
1602 struct rte_flow_error *error);
1603 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1604 uint64_t item_flags,
1605 uint8_t target_protocol,
1606 struct rte_flow_error *error);
1607 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1608 uint64_t item_flags,
1609 struct rte_eth_dev *dev,
1610 struct rte_flow_error *error);
1611 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1613 const struct rte_flow_item *geneve_item,
1614 struct rte_eth_dev *dev,
1615 struct rte_flow_error *error);
1616 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1617 uint64_t item_flags,
1619 uint16_t ether_type,
1620 const struct rte_flow_item_ecpri *acc_mask,
1621 struct rte_flow_error *error);
1622 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1623 struct mlx5_flow_meter_info *fm,
1625 uint8_t domain_bitmap);
1626 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1627 struct mlx5_flow_meter_info *fm);
1628 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1629 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1630 (struct rte_eth_dev *dev,
1631 struct mlx5_flow_meter_policy *mtr_policy,
1632 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1633 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
1634 struct mlx5_flow_meter_policy *mtr_policy);
1635 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1636 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev);
1637 int mlx5_action_handle_attach(struct rte_eth_dev *dev);
1638 int mlx5_action_handle_detach(struct rte_eth_dev *dev);
1639 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1640 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1641 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1643 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx);
1644 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1646 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1647 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx,
1648 struct mlx5_list_entry *oentry,
1650 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1651 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1652 uint32_t table_level, uint8_t egress, uint8_t transfer,
1653 bool external, const struct mlx5_flow_tunnel *tunnel,
1654 uint32_t group_id, uint8_t dummy,
1655 uint32_t table_id, struct rte_flow_error *error);
1657 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx);
1658 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1660 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1661 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx,
1662 struct mlx5_list_entry *oentry,
1664 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1666 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1668 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx);
1669 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1670 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx,
1671 struct mlx5_list_entry *oentry,
1673 void flow_dv_modify_clone_free_cb(void *tool_ctx,
1674 struct mlx5_list_entry *entry);
1676 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx);
1677 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1679 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1680 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx,
1681 struct mlx5_list_entry *entry,
1683 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1685 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1687 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx,
1689 void flow_dv_encap_decap_remove_cb(void *tool_ctx,
1690 struct mlx5_list_entry *entry);
1691 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx,
1692 struct mlx5_list_entry *entry,
1694 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx,
1695 struct mlx5_list_entry *entry);
1697 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1699 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx);
1700 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1702 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1704 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx);
1705 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1706 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx,
1707 struct mlx5_list_entry *entry, void *cb_ctx);
1708 void flow_dv_port_id_clone_free_cb(void *tool_ctx,
1709 struct mlx5_list_entry *entry);
1711 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1713 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx,
1715 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1716 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx,
1717 struct mlx5_list_entry *entry, void *cb_ctx);
1718 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx,
1719 struct mlx5_list_entry *entry);
1721 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1723 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx);
1724 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1725 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx,
1726 struct mlx5_list_entry *entry, void *cb_ctx);
1727 void flow_dv_sample_clone_free_cb(void *tool_ctx,
1728 struct mlx5_list_entry *entry);
1730 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1732 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx,
1734 void flow_dv_dest_array_remove_cb(void *tool_ctx,
1735 struct mlx5_list_entry *entry);
1736 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx,
1737 struct mlx5_list_entry *entry, void *cb_ctx);
1738 void flow_dv_dest_array_clone_free_cb(void *tool_ctx,
1739 struct mlx5_list_entry *entry);
1741 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1743 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1744 const struct rte_flow_item *item,
1745 struct rte_flow_error *error);
1746 void flow_release_workspace(void *data);
1747 int mlx5_flow_os_init_workspace_once(void);
1748 void *mlx5_flow_os_get_specific_workspace(void);
1749 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1750 void mlx5_flow_os_release_workspace(void);
1751 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1752 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1753 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1754 const struct rte_flow_action *actions[RTE_COLORS],
1755 struct rte_flow_attr *attr,
1757 uint8_t *domain_bitmap,
1758 uint8_t *policy_mode,
1759 struct rte_mtr_error *error);
1760 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1761 struct mlx5_flow_meter_policy *mtr_policy);
1762 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1763 struct mlx5_flow_meter_policy *mtr_policy,
1764 const struct rte_flow_action *actions[RTE_COLORS],
1765 struct rte_mtr_error *error);
1766 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1767 struct mlx5_flow_meter_policy *mtr_policy);
1768 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1769 struct mlx5_flow_meter_policy *mtr_policy);
1770 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1771 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1772 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1773 struct mlx5_flow_handle *dev_handle);
1774 const struct mlx5_flow_tunnel *
1775 mlx5_get_tof(const struct rte_flow_item *items,
1776 const struct rte_flow_action *actions,
1777 enum mlx5_tof_rule_type *rule_type);
1779 flow_hw_resource_release(struct rte_eth_dev *dev);
1780 #endif /* RTE_PMD_MLX5_FLOW_H_ */