1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
31 /* Private rte flow items. */
32 enum mlx5_rte_flow_item_type {
33 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
35 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
38 /* Private (internal) rte flow actions. */
39 enum mlx5_rte_flow_action_type {
40 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
41 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
42 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
43 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
46 /* Matches on selected register. */
47 struct mlx5_rte_flow_item_tag {
52 /* Modify selected register. */
53 struct mlx5_rte_flow_action_set_tag {
58 struct mlx5_flow_action_copy_mreg {
63 /* Matches on source queue. */
64 struct mlx5_rte_flow_item_tx_queue {
68 /* Feature name to allocate metadata register. */
69 enum mlx5_feature_name {
82 /* Pattern outer Layer bits. */
83 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
84 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
85 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
86 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
87 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
88 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
90 /* Pattern inner Layer bits. */
91 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
92 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
93 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
94 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
95 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
96 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
98 /* Pattern tunnel Layer bits. */
99 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
100 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
101 #define MLX5_FLOW_LAYER_GRE (1u << 14)
102 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
103 /* List of tunnel Layer bits continued below. */
105 /* General pattern items bits. */
106 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
107 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
108 #define MLX5_FLOW_ITEM_TAG (1u << 18)
109 #define MLX5_FLOW_ITEM_MARK (1u << 19)
111 /* Pattern MISC bits. */
112 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
113 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
114 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
116 /* Pattern tunnel Layer bits (continued). */
117 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
118 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
119 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
120 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
123 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
125 /* Pattern tunnel Layer bits (continued). */
126 #define MLX5_FLOW_LAYER_GTP (1u << 28)
129 #define MLX5_FLOW_LAYER_OUTER_L3 \
130 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
131 #define MLX5_FLOW_LAYER_OUTER_L4 \
132 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
133 #define MLX5_FLOW_LAYER_OUTER \
134 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
135 MLX5_FLOW_LAYER_OUTER_L4)
138 #define MLX5_FLOW_LAYER_TUNNEL \
139 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
140 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
141 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
142 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
145 #define MLX5_FLOW_LAYER_INNER_L3 \
146 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
147 #define MLX5_FLOW_LAYER_INNER_L4 \
148 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
149 #define MLX5_FLOW_LAYER_INNER \
150 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
151 MLX5_FLOW_LAYER_INNER_L4)
154 #define MLX5_FLOW_LAYER_L2 \
155 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
156 #define MLX5_FLOW_LAYER_L3_IPV4 \
157 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
158 #define MLX5_FLOW_LAYER_L3_IPV6 \
159 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
160 #define MLX5_FLOW_LAYER_L3 \
161 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
162 #define MLX5_FLOW_LAYER_L4 \
163 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
166 #define MLX5_FLOW_ACTION_DROP (1u << 0)
167 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
168 #define MLX5_FLOW_ACTION_RSS (1u << 2)
169 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
170 #define MLX5_FLOW_ACTION_MARK (1u << 4)
171 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
172 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
173 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
174 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
175 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
176 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
177 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
178 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
179 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
180 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
181 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
182 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
183 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
184 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
185 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
186 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
187 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
188 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
189 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
190 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
191 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
192 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
193 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
194 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
195 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
196 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
197 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
198 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
199 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33)
200 #define MLX5_FLOW_ACTION_SET_META (1ull << 34)
201 #define MLX5_FLOW_ACTION_METER (1ull << 35)
202 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 36)
203 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 37)
205 #define MLX5_FLOW_FATE_ACTIONS \
206 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
207 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
209 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
210 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
211 MLX5_FLOW_ACTION_JUMP)
213 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
214 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
215 MLX5_FLOW_ACTION_RAW_ENCAP | \
216 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
218 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
219 MLX5_FLOW_ACTION_NVGRE_DECAP | \
220 MLX5_FLOW_ACTION_RAW_DECAP | \
221 MLX5_FLOW_ACTION_OF_POP_VLAN)
223 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
224 MLX5_FLOW_ACTION_SET_IPV4_DST | \
225 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
226 MLX5_FLOW_ACTION_SET_IPV6_DST | \
227 MLX5_FLOW_ACTION_SET_TP_SRC | \
228 MLX5_FLOW_ACTION_SET_TP_DST | \
229 MLX5_FLOW_ACTION_SET_TTL | \
230 MLX5_FLOW_ACTION_DEC_TTL | \
231 MLX5_FLOW_ACTION_SET_MAC_SRC | \
232 MLX5_FLOW_ACTION_SET_MAC_DST | \
233 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
234 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
235 MLX5_FLOW_ACTION_INC_TCP_ACK | \
236 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
237 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
238 MLX5_FLOW_ACTION_SET_TAG | \
239 MLX5_FLOW_ACTION_MARK_EXT | \
240 MLX5_FLOW_ACTION_SET_META | \
241 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
242 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
244 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
245 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
247 #define IPPROTO_MPLS 137
250 /* UDP port number for MPLS */
251 #define MLX5_UDP_PORT_MPLS 6635
253 /* UDP port numbers for VxLAN. */
254 #define MLX5_UDP_PORT_VXLAN 4789
255 #define MLX5_UDP_PORT_VXLAN_GPE 4790
257 /* UDP port numbers for GENEVE. */
258 #define MLX5_UDP_PORT_GENEVE 6081
260 /* Priority reserved for default flows. */
261 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
264 * Number of sub priorities.
265 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
266 * matching on the NIC (firmware dependent) L4 most have the higher priority
267 * followed by L3 and ending with L2.
269 #define MLX5_PRIORITY_MAP_L2 2
270 #define MLX5_PRIORITY_MAP_L3 1
271 #define MLX5_PRIORITY_MAP_L4 0
272 #define MLX5_PRIORITY_MAP_MAX 3
274 /* Valid layer type for IPV4 RSS. */
275 #define MLX5_IPV4_LAYER_TYPES \
276 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
277 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
278 ETH_RSS_NONFRAG_IPV4_OTHER)
280 /* IBV hash source bits for IPV4. */
281 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
283 /* Valid layer type for IPV6 RSS. */
284 #define MLX5_IPV6_LAYER_TYPES \
285 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
286 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
287 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
289 /* IBV hash source bits for IPV6. */
290 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
292 /* IBV hash bits for L3 SRC. */
293 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
295 /* IBV hash bits for L3 DST. */
296 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
298 /* IBV hash bits for TCP. */
299 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
300 IBV_RX_HASH_DST_PORT_TCP)
302 /* IBV hash bits for UDP. */
303 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
304 IBV_RX_HASH_DST_PORT_UDP)
306 /* IBV hash bits for L4 SRC. */
307 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
308 IBV_RX_HASH_SRC_PORT_UDP)
310 /* IBV hash bits for L4 DST. */
311 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
312 IBV_RX_HASH_DST_PORT_UDP)
314 /* Geneve header first 16Bit */
315 #define MLX5_GENEVE_VER_MASK 0x3
316 #define MLX5_GENEVE_VER_SHIFT 14
317 #define MLX5_GENEVE_VER_VAL(a) \
318 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
319 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
320 #define MLX5_GENEVE_OPTLEN_SHIFT 7
321 #define MLX5_GENEVE_OPTLEN_VAL(a) \
322 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
323 #define MLX5_GENEVE_OAMF_MASK 0x1
324 #define MLX5_GENEVE_OAMF_SHIFT 7
325 #define MLX5_GENEVE_OAMF_VAL(a) \
326 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
327 #define MLX5_GENEVE_CRITO_MASK 0x1
328 #define MLX5_GENEVE_CRITO_SHIFT 6
329 #define MLX5_GENEVE_CRITO_VAL(a) \
330 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
331 #define MLX5_GENEVE_RSVD_MASK 0x3F
332 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
334 * The length of the Geneve options fields, expressed in four byte multiples,
335 * not including the eight byte fixed tunnel.
337 #define MLX5_GENEVE_OPT_LEN_0 14
338 #define MLX5_GENEVE_OPT_LEN_1 63
340 enum mlx5_flow_drv_type {
343 MLX5_FLOW_TYPE_VERBS,
347 /* Matcher PRM representation */
348 struct mlx5_flow_dv_match_params {
350 /**< Size of match value. Do NOT split size and key! */
351 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
352 /**< Matcher value. This value is used as the mask or as a key. */
355 /* Matcher structure. */
356 struct mlx5_flow_dv_matcher {
357 LIST_ENTRY(mlx5_flow_dv_matcher) next;
358 /**< Pointer to the next element. */
359 struct mlx5_flow_tbl_resource *tbl;
360 /**< Pointer to the table(group) the matcher associated with. */
361 rte_atomic32_t refcnt; /**< Reference counter. */
362 void *matcher_object; /**< Pointer to DV matcher */
363 uint16_t crc; /**< CRC of key. */
364 uint16_t priority; /**< Priority of matcher. */
365 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
368 #define MLX5_ENCAP_MAX_LEN 132
370 /* Encap/decap resource structure. */
371 struct mlx5_flow_dv_encap_decap_resource {
372 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
373 /* Pointer to next element. */
374 rte_atomic32_t refcnt; /**< Reference counter. */
376 /**< Verbs encap/decap action object. */
377 uint8_t buf[MLX5_ENCAP_MAX_LEN];
379 uint8_t reformat_type;
381 uint64_t flags; /**< Flags for RDMA API. */
384 /* Tag resource structure. */
385 struct mlx5_flow_dv_tag_resource {
386 struct mlx5_hlist_entry entry;
387 /**< hash list entry for tag resource, tag value as the key. */
389 /**< Verbs tag action object. */
390 rte_atomic32_t refcnt; /**< Reference counter. */
394 * Number of modification commands.
395 * If extensive metadata registers are supported
396 * the maximal actions amount is 16 and 8 otherwise.
398 #define MLX5_MODIFY_NUM 16
399 #define MLX5_MODIFY_NUM_NO_MREG 8
401 /* Modify resource structure */
402 struct mlx5_flow_dv_modify_hdr_resource {
403 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
404 /* Pointer to next element. */
405 rte_atomic32_t refcnt; /**< Reference counter. */
406 struct ibv_flow_action *verbs_action;
407 /**< Verbs modify header action object. */
408 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
409 uint32_t actions_num; /**< Number of modification actions. */
410 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
411 /**< Modification actions. */
412 uint64_t flags; /**< Flags for RDMA API. */
415 /* Jump action resource structure. */
416 struct mlx5_flow_dv_jump_tbl_resource {
417 rte_atomic32_t refcnt; /**< Reference counter. */
418 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
419 void *action; /**< Pointer to the rdma core action. */
422 /* Port ID resource structure. */
423 struct mlx5_flow_dv_port_id_action_resource {
424 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
425 /* Pointer to next element. */
426 rte_atomic32_t refcnt; /**< Reference counter. */
428 /**< Verbs tag action object. */
429 uint32_t port_id; /**< Port ID value. */
432 /* Push VLAN action resource structure */
433 struct mlx5_flow_dv_push_vlan_action_resource {
434 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
435 /* Pointer to next element. */
436 rte_atomic32_t refcnt; /**< Reference counter. */
437 void *action; /**< Direct verbs action object. */
438 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
439 rte_be32_t vlan_tag; /**< VLAN tag value. */
442 /* Metadata register copy table entry. */
443 struct mlx5_flow_mreg_copy_resource {
445 * Hash list entry for copy table.
446 * - Key is 32/64-bit MARK action ID.
447 * - MUST be the first entry.
449 struct mlx5_hlist_entry hlist_ent;
450 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
451 /* List entry for device flows. */
452 uint32_t refcnt; /* Reference counter. */
453 uint32_t appcnt; /* Apply/Remove counter. */
454 struct rte_flow *flow; /* Built flow for copy. */
457 /* Table data structure of the hash organization. */
458 struct mlx5_flow_tbl_data_entry {
459 struct mlx5_hlist_entry entry;
460 /**< hash list entry, 64-bits key inside. */
461 struct mlx5_flow_tbl_resource tbl;
462 /**< flow table resource. */
463 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
464 /**< matchers' header associated with the flow table. */
465 struct mlx5_flow_dv_jump_tbl_resource jump;
466 /**< jump resource, at most one for each table created. */
470 * Max number of actions per DV flow.
471 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
472 * In rdma-core file providers/mlx5/verbs.c
474 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
476 /* DV flows structure. */
477 struct mlx5_flow_dv {
478 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
480 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
481 struct mlx5_flow_dv_match_params value;
482 /**< Holds the value that the packet is compared to. */
483 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
484 /**< Pointer to encap/decap resource in cache. */
485 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
486 /**< Pointer to modify header resource in cache. */
487 struct ibv_flow *flow; /**< Installed flow. */
488 struct mlx5_flow_dv_jump_tbl_resource *jump;
489 /**< Pointer to the jump action resource. */
490 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
491 /**< Pointer to port ID action resource. */
492 struct mlx5_vf_vlan vf_vlan;
493 /**< Structure for VF VLAN workaround. */
494 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
495 /**< Pointer to push VLAN action resource in cache. */
496 struct mlx5_flow_dv_tag_resource *tag_resource;
497 /**< pointer to the tag action. */
498 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
499 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
502 int actions_n; /**< number of actions. */
505 /* Verbs specification header. */
506 struct ibv_spec_header {
507 enum ibv_flow_spec_type type;
511 /** Handles information leading to a drop fate. */
512 struct mlx5_flow_verbs {
513 LIST_ENTRY(mlx5_flow_verbs) next;
514 unsigned int size; /**< Size of the attribute. */
516 struct ibv_flow_attr *attr;
517 /**< Pointer to the Specification buffer. */
518 uint8_t *specs; /**< Pointer to the specifications. */
520 struct ibv_flow *flow; /**< Verbs flow pointer. */
521 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
522 struct mlx5_vf_vlan vf_vlan;
523 /**< Structure for VF VLAN workaround. */
526 struct mlx5_flow_rss {
528 uint32_t queue_num; /**< Number of entries in @p queue. */
529 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
530 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
531 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
534 /** Device flow structure. */
536 LIST_ENTRY(mlx5_flow) next;
537 struct rte_flow *flow; /**< Pointer to the main flow. */
539 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
541 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
542 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
543 uint8_t ingress; /**< 1 if the flow is ingress. */
544 uint32_t group; /**< The group index. */
545 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
547 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
548 struct mlx5_flow_dv dv;
550 struct mlx5_flow_verbs verbs;
553 uint32_t qrss_id; /**< Uniqie Q/RSS suffix subflow tag. */
554 uint32_t mtr_flow_id; /**< Unique meter match flow id. */
556 bool external; /**< true if the flow is created external to PMD. */
559 /* Flow meter state. */
560 #define MLX5_FLOW_METER_DISABLE 0
561 #define MLX5_FLOW_METER_ENABLE 1
563 #define MLX5_MAN_WIDTH 8
564 /* Modify this value if enum rte_mtr_color changes. */
565 #define RTE_MTR_DROPPED RTE_COLORS
567 /* Meter policer statistics */
568 struct mlx5_flow_policer_stats {
569 struct mlx5_flow_counter *cnt[RTE_COLORS + 1];
570 /**< Color counter, extra for drop. */
572 /**< Statistics mask for the colors. */
575 /* Meter table structure. */
576 struct mlx5_meter_domain_info {
577 struct mlx5_flow_tbl_resource *tbl;
580 /**< Meter color not match default criteria. */
582 /**< Meter color match criteria. */
584 /**< Meter match action. */
585 void *policer_rules[RTE_MTR_DROPPED + 1];
586 /**< Meter policer for the match. */
589 /* Meter table set for TX RX FDB. */
590 struct mlx5_meter_domains_infos {
592 /**< Table user count. */
593 struct mlx5_meter_domain_info egress;
594 /**< TX meter table. */
595 struct mlx5_meter_domain_info ingress;
596 /**< RX meter table. */
597 struct mlx5_meter_domain_info transfer;
598 /**< FDB meter table. */
600 /**< Drop action as not matched. */
601 void *count_actns[RTE_MTR_DROPPED + 1];
602 /**< Counters for match and unmatched statistics. */
603 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
604 /**< Flow meter parameter. */
606 /**< Flow meter parameter size. */
608 /**< Flow meter action. */
611 /* Meter parameter structure. */
612 struct mlx5_flow_meter {
613 TAILQ_ENTRY(mlx5_flow_meter) next;
614 /**< Pointer to the next flow meter structure. */
617 struct rte_mtr_params params;
618 /**< Meter rule parameters. */
619 struct mlx5_flow_meter_profile *profile;
620 /**< Meter profile parameters. */
621 struct rte_flow_attr attr;
622 /**< Flow attributes. */
623 struct mlx5_meter_domains_infos *mfts;
624 /**< Flow table created for this meter. */
625 struct mlx5_flow_policer_stats policer_stats;
626 /**< Meter policer statistics. */
629 uint32_t active_state:1;
632 /**< Meter shared or not. */
635 /* RFC2697 parameter structure. */
636 struct mlx5_flow_meter_srtcm_rfc2697_prm {
637 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
638 uint32_t cbs_exponent:5;
639 uint32_t cbs_mantissa:8;
640 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
641 uint32_t cir_exponent:5;
642 uint32_t cir_mantissa:8;
643 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
644 uint32_t ebs_exponent:5;
645 uint32_t ebs_mantissa:8;
648 /* Flow meter profile structure. */
649 struct mlx5_flow_meter_profile {
650 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
651 /**< Pointer to the next flow meter structure. */
652 uint32_t meter_profile_id; /**< Profile id. */
653 struct rte_mtr_meter_profile profile; /**< Profile detail. */
655 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
656 /**< srtcm_rfc2697 struct. */
658 uint32_t ref_cnt; /**< Use count. */
661 /* Flow structure. */
663 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
664 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
665 struct mlx5_flow_rss rss; /**< RSS context. */
666 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
667 struct mlx5_flow_mreg_copy_resource *mreg_copy;
668 /**< pointer to metadata register copy table resource. */
669 struct mlx5_flow_meter *meter; /**< Holds flow meter. */
670 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
671 /**< Device flows that are part of the flow. */
672 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
673 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
674 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
677 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
678 const struct rte_flow_attr *attr,
679 const struct rte_flow_item items[],
680 const struct rte_flow_action actions[],
682 struct rte_flow_error *error);
683 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
684 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
685 const struct rte_flow_action actions[], struct rte_flow_error *error);
686 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
687 struct mlx5_flow *dev_flow,
688 const struct rte_flow_attr *attr,
689 const struct rte_flow_item items[],
690 const struct rte_flow_action actions[],
691 struct rte_flow_error *error);
692 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
693 struct rte_flow_error *error);
694 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
695 struct rte_flow *flow);
696 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
697 struct rte_flow *flow);
698 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
699 struct rte_flow *flow,
700 const struct rte_flow_action *actions,
702 struct rte_flow_error *error);
703 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
704 (struct rte_eth_dev *dev,
705 const struct mlx5_flow_meter *fm);
706 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
707 struct mlx5_meter_domains_infos *tbls);
708 typedef int (*mlx5_flow_create_policer_rules_t)
709 (struct rte_eth_dev *dev,
710 struct mlx5_flow_meter *fm,
711 const struct rte_flow_attr *attr);
712 typedef int (*mlx5_flow_destroy_policer_rules_t)
713 (struct rte_eth_dev *dev,
714 const struct mlx5_flow_meter *fm,
715 const struct rte_flow_attr *attr);
716 typedef struct mlx5_flow_counter * (*mlx5_flow_counter_alloc_t)
717 (struct rte_eth_dev *dev);
718 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
719 struct mlx5_flow_counter *cnt);
720 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
721 struct mlx5_flow_counter *cnt,
722 bool clear, uint64_t *pkts,
724 struct mlx5_flow_driver_ops {
725 mlx5_flow_validate_t validate;
726 mlx5_flow_prepare_t prepare;
727 mlx5_flow_translate_t translate;
728 mlx5_flow_apply_t apply;
729 mlx5_flow_remove_t remove;
730 mlx5_flow_destroy_t destroy;
731 mlx5_flow_query_t query;
732 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
733 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
734 mlx5_flow_create_policer_rules_t create_policer_rules;
735 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
736 mlx5_flow_counter_alloc_t counter_alloc;
737 mlx5_flow_counter_free_t counter_free;
738 mlx5_flow_counter_query_t counter_query;
742 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
743 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
744 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
745 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
749 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
750 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
751 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
752 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
754 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
755 bool external, uint32_t group, uint32_t *table,
756 struct rte_flow_error *error);
757 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
758 uint64_t layer_types,
759 uint64_t hash_fields);
760 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
761 uint32_t subpriority);
762 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
763 enum mlx5_feature_name feature,
765 struct rte_flow_error *error);
766 const struct rte_flow_action *mlx5_flow_find_action
767 (const struct rte_flow_action *actions,
768 enum rte_flow_action_type action);
769 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
770 const struct rte_flow_attr *attr,
771 struct rte_flow_error *error);
772 int mlx5_flow_validate_action_drop(uint64_t action_flags,
773 const struct rte_flow_attr *attr,
774 struct rte_flow_error *error);
775 int mlx5_flow_validate_action_flag(uint64_t action_flags,
776 const struct rte_flow_attr *attr,
777 struct rte_flow_error *error);
778 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
779 uint64_t action_flags,
780 const struct rte_flow_attr *attr,
781 struct rte_flow_error *error);
782 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
783 uint64_t action_flags,
784 struct rte_eth_dev *dev,
785 const struct rte_flow_attr *attr,
786 struct rte_flow_error *error);
787 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
788 uint64_t action_flags,
789 struct rte_eth_dev *dev,
790 const struct rte_flow_attr *attr,
792 struct rte_flow_error *error);
793 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
794 const struct rte_flow_attr *attributes,
795 struct rte_flow_error *error);
796 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
798 const uint8_t *nic_mask,
800 struct rte_flow_error *error);
801 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
803 struct rte_flow_error *error);
804 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
806 uint8_t target_protocol,
807 struct rte_flow_error *error);
808 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
810 const struct rte_flow_item *gre_item,
811 struct rte_flow_error *error);
812 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
816 const struct rte_flow_item_ipv4 *acc_mask,
817 struct rte_flow_error *error);
818 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
822 const struct rte_flow_item_ipv6 *acc_mask,
823 struct rte_flow_error *error);
824 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
825 const struct rte_flow_item *item,
828 struct rte_flow_error *error);
829 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
831 uint8_t target_protocol,
832 const struct rte_flow_item_tcp *flow_mask,
833 struct rte_flow_error *error);
834 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
836 uint8_t target_protocol,
837 struct rte_flow_error *error);
838 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
840 struct rte_eth_dev *dev,
841 struct rte_flow_error *error);
842 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
844 struct rte_flow_error *error);
845 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
847 struct rte_eth_dev *dev,
848 struct rte_flow_error *error);
849 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
851 uint8_t target_protocol,
852 struct rte_flow_error *error);
853 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
855 uint8_t target_protocol,
856 struct rte_flow_error *error);
857 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
859 uint8_t target_protocol,
860 struct rte_flow_error *error);
861 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
863 struct rte_eth_dev *dev,
864 struct rte_flow_error *error);
865 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
866 (struct rte_eth_dev *dev,
867 const struct mlx5_flow_meter *fm);
868 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
869 struct mlx5_meter_domains_infos *tbl);
870 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
871 struct mlx5_flow_meter *fm,
872 const struct rte_flow_attr *attr);
873 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
874 struct mlx5_flow_meter *fm,
875 const struct rte_flow_attr *attr);
876 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
877 struct rte_mtr_error *error);
878 #endif /* RTE_PMD_MLX5_FLOW_H_ */