1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Private rte flow items. */
31 enum mlx5_rte_flow_item_type {
32 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
34 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
37 /* Private (internal) rte flow actions. */
38 enum mlx5_rte_flow_action_type {
39 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
40 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
41 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
44 /* Matches on selected register. */
45 struct mlx5_rte_flow_item_tag {
50 /* Modify selected register. */
51 struct mlx5_rte_flow_action_set_tag {
56 struct mlx5_flow_action_copy_mreg {
61 /* Matches on source queue. */
62 struct mlx5_rte_flow_item_tx_queue {
66 /* Pattern outer Layer bits. */
67 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
68 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
69 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
70 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
71 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
72 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
74 /* Pattern inner Layer bits. */
75 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
76 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
77 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
78 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
79 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
80 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
82 /* Pattern tunnel Layer bits. */
83 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
84 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
85 #define MLX5_FLOW_LAYER_GRE (1u << 14)
86 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
87 /* List of tunnel Layer bits continued below. */
89 /* General pattern items bits. */
90 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
91 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
92 #define MLX5_FLOW_ITEM_TAG (1u << 18)
94 /* Pattern MISC bits. */
95 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
96 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
97 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
99 /* Pattern tunnel Layer bits (continued). */
100 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
101 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
102 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
103 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
106 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
109 #define MLX5_FLOW_LAYER_OUTER_L3 \
110 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
111 #define MLX5_FLOW_LAYER_OUTER_L4 \
112 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
113 #define MLX5_FLOW_LAYER_OUTER \
114 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
115 MLX5_FLOW_LAYER_OUTER_L4)
117 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
118 #define MLX5_FLOW_LAYER_IPV4_LRO \
119 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
120 #define MLX5_FLOW_LAYER_IPV6_LRO \
121 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
124 #define MLX5_FLOW_LAYER_TUNNEL \
125 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
126 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
127 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
128 MLX5_FLOW_LAYER_GENEVE)
131 #define MLX5_FLOW_LAYER_INNER_L3 \
132 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
133 #define MLX5_FLOW_LAYER_INNER_L4 \
134 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
135 #define MLX5_FLOW_LAYER_INNER \
136 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
137 MLX5_FLOW_LAYER_INNER_L4)
140 #define MLX5_FLOW_LAYER_L2 \
141 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
142 #define MLX5_FLOW_LAYER_L3_IPV4 \
143 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
144 #define MLX5_FLOW_LAYER_L3_IPV6 \
145 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
146 #define MLX5_FLOW_LAYER_L3 \
147 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
148 #define MLX5_FLOW_LAYER_L4 \
149 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
152 #define MLX5_FLOW_ACTION_DROP (1u << 0)
153 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
154 #define MLX5_FLOW_ACTION_RSS (1u << 2)
155 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
156 #define MLX5_FLOW_ACTION_MARK (1u << 4)
157 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
158 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
159 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
160 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
161 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
162 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
163 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
164 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
165 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
166 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
167 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
168 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
169 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
170 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
171 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
172 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
173 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
174 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
175 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
176 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
177 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
178 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
179 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
180 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
181 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
182 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
183 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
184 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
186 #define MLX5_FLOW_FATE_ACTIONS \
187 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
188 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
190 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
191 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
192 MLX5_FLOW_ACTION_JUMP)
194 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
195 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
196 MLX5_FLOW_ACTION_RAW_ENCAP | \
197 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
199 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
200 MLX5_FLOW_ACTION_NVGRE_DECAP | \
201 MLX5_FLOW_ACTION_RAW_DECAP | \
202 MLX5_FLOW_ACTION_OF_POP_VLAN)
204 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
205 MLX5_FLOW_ACTION_SET_IPV4_DST | \
206 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
207 MLX5_FLOW_ACTION_SET_IPV6_DST | \
208 MLX5_FLOW_ACTION_SET_TP_SRC | \
209 MLX5_FLOW_ACTION_SET_TP_DST | \
210 MLX5_FLOW_ACTION_SET_TTL | \
211 MLX5_FLOW_ACTION_DEC_TTL | \
212 MLX5_FLOW_ACTION_SET_MAC_SRC | \
213 MLX5_FLOW_ACTION_SET_MAC_DST | \
214 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
215 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
216 MLX5_FLOW_ACTION_INC_TCP_ACK | \
217 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
218 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
219 MLX5_FLOW_ACTION_SET_TAG)
221 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
222 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
224 #define IPPROTO_MPLS 137
227 /* UDP port number for MPLS */
228 #define MLX5_UDP_PORT_MPLS 6635
230 /* UDP port numbers for VxLAN. */
231 #define MLX5_UDP_PORT_VXLAN 4789
232 #define MLX5_UDP_PORT_VXLAN_GPE 4790
234 /* UDP port numbers for GENEVE. */
235 #define MLX5_UDP_PORT_GENEVE 6081
237 /* Priority reserved for default flows. */
238 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
241 * Number of sub priorities.
242 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
243 * matching on the NIC (firmware dependent) L4 most have the higher priority
244 * followed by L3 and ending with L2.
246 #define MLX5_PRIORITY_MAP_L2 2
247 #define MLX5_PRIORITY_MAP_L3 1
248 #define MLX5_PRIORITY_MAP_L4 0
249 #define MLX5_PRIORITY_MAP_MAX 3
251 /* Valid layer type for IPV4 RSS. */
252 #define MLX5_IPV4_LAYER_TYPES \
253 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
254 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
255 ETH_RSS_NONFRAG_IPV4_OTHER)
257 /* IBV hash source bits for IPV4. */
258 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
260 /* Valid layer type for IPV6 RSS. */
261 #define MLX5_IPV6_LAYER_TYPES \
262 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
263 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
264 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
266 /* IBV hash source bits for IPV6. */
267 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
270 /* Geneve header first 16Bit */
271 #define MLX5_GENEVE_VER_MASK 0x3
272 #define MLX5_GENEVE_VER_SHIFT 14
273 #define MLX5_GENEVE_VER_VAL(a) \
274 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
275 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
276 #define MLX5_GENEVE_OPTLEN_SHIFT 7
277 #define MLX5_GENEVE_OPTLEN_VAL(a) \
278 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
279 #define MLX5_GENEVE_OAMF_MASK 0x1
280 #define MLX5_GENEVE_OAMF_SHIFT 7
281 #define MLX5_GENEVE_OAMF_VAL(a) \
282 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
283 #define MLX5_GENEVE_CRITO_MASK 0x1
284 #define MLX5_GENEVE_CRITO_SHIFT 6
285 #define MLX5_GENEVE_CRITO_VAL(a) \
286 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
287 #define MLX5_GENEVE_RSVD_MASK 0x3F
288 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
290 * The length of the Geneve options fields, expressed in four byte multiples,
291 * not including the eight byte fixed tunnel.
293 #define MLX5_GENEVE_OPT_LEN_0 14
294 #define MLX5_GENEVE_OPT_LEN_1 63
296 enum mlx5_flow_drv_type {
299 MLX5_FLOW_TYPE_VERBS,
303 /* Matcher PRM representation */
304 struct mlx5_flow_dv_match_params {
306 /**< Size of match value. Do NOT split size and key! */
307 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
308 /**< Matcher value. This value is used as the mask or as a key. */
311 /* Matcher structure. */
312 struct mlx5_flow_dv_matcher {
313 LIST_ENTRY(mlx5_flow_dv_matcher) next;
314 /* Pointer to the next element. */
315 rte_atomic32_t refcnt; /**< Reference counter. */
316 void *matcher_object; /**< Pointer to DV matcher */
317 uint16_t crc; /**< CRC of key. */
318 uint16_t priority; /**< Priority of matcher. */
319 uint8_t egress; /**< Egress matcher. */
320 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
321 uint32_t group; /**< The matcher group. */
322 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
325 #define MLX5_ENCAP_MAX_LEN 132
327 /* Encap/decap resource structure. */
328 struct mlx5_flow_dv_encap_decap_resource {
329 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
330 /* Pointer to next element. */
331 rte_atomic32_t refcnt; /**< Reference counter. */
333 /**< Verbs encap/decap action object. */
334 uint8_t buf[MLX5_ENCAP_MAX_LEN];
336 uint8_t reformat_type;
338 uint64_t flags; /**< Flags for RDMA API. */
341 /* Tag resource structure. */
342 struct mlx5_flow_dv_tag_resource {
343 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
344 /* Pointer to next element. */
345 rte_atomic32_t refcnt; /**< Reference counter. */
347 /**< Verbs tag action object. */
348 uint32_t tag; /**< the tag value. */
352 * Number of modification commands.
353 * If extensive metadata registers are supported
354 * the maximal actions amount is 16 and 8 otherwise.
356 #define MLX5_MODIFY_NUM 16
357 #define MLX5_MODIFY_NUM_NO_MREG 8
359 /* Modify resource structure */
360 struct mlx5_flow_dv_modify_hdr_resource {
361 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
362 /* Pointer to next element. */
363 rte_atomic32_t refcnt; /**< Reference counter. */
364 struct ibv_flow_action *verbs_action;
365 /**< Verbs modify header action object. */
366 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
367 uint32_t actions_num; /**< Number of modification actions. */
368 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
369 /**< Modification actions. */
370 uint64_t flags; /**< Flags for RDMA API. */
373 /* Jump action resource structure. */
374 struct mlx5_flow_dv_jump_tbl_resource {
375 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
376 /* Pointer to next element. */
377 rte_atomic32_t refcnt; /**< Reference counter. */
378 void *action; /**< Pointer to the rdma core action. */
379 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
380 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
383 /* Port ID resource structure. */
384 struct mlx5_flow_dv_port_id_action_resource {
385 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
386 /* Pointer to next element. */
387 rte_atomic32_t refcnt; /**< Reference counter. */
389 /**< Verbs tag action object. */
390 uint32_t port_id; /**< Port ID value. */
393 /* Push VLAN action resource structure */
394 struct mlx5_flow_dv_push_vlan_action_resource {
395 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
396 /* Pointer to next element. */
397 rte_atomic32_t refcnt; /**< Reference counter. */
398 void *action; /**< Direct verbs action object. */
399 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
400 rte_be32_t vlan_tag; /**< VLAN tag value. */
404 * Max number of actions per DV flow.
405 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
406 * In rdma-core file providers/mlx5/verbs.c
408 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
410 /* DV flows structure. */
411 struct mlx5_flow_dv {
412 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
414 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
415 struct mlx5_flow_dv_match_params value;
416 /**< Holds the value that the packet is compared to. */
417 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
418 /**< Pointer to encap/decap resource in cache. */
419 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
420 /**< Pointer to modify header resource in cache. */
421 struct ibv_flow *flow; /**< Installed flow. */
422 struct mlx5_flow_dv_jump_tbl_resource *jump;
423 /**< Pointer to the jump action resource. */
424 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
425 /**< Pointer to port ID action resource. */
426 struct mlx5_vf_vlan vf_vlan;
427 /**< Structure for VF VLAN workaround. */
428 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
429 /**< Pointer to push VLAN action resource in cache. */
430 struct mlx5_flow_dv_tag_resource *tag_resource;
431 /**< pointer to the tag action. */
432 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
433 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
436 int actions_n; /**< number of actions. */
439 /* Verbs specification header. */
440 struct ibv_spec_header {
441 enum ibv_flow_spec_type type;
445 /** Handles information leading to a drop fate. */
446 struct mlx5_flow_verbs {
447 LIST_ENTRY(mlx5_flow_verbs) next;
448 unsigned int size; /**< Size of the attribute. */
450 struct ibv_flow_attr *attr;
451 /**< Pointer to the Specification buffer. */
452 uint8_t *specs; /**< Pointer to the specifications. */
454 struct ibv_flow *flow; /**< Verbs flow pointer. */
455 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
456 struct mlx5_vf_vlan vf_vlan;
457 /**< Structure for VF VLAN workaround. */
460 struct mlx5_flow_rss {
462 uint32_t queue_num; /**< Number of entries in @p queue. */
463 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
464 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
465 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
468 /** Device flow structure. */
470 LIST_ENTRY(mlx5_flow) next;
471 struct rte_flow *flow; /**< Pointer to the main flow. */
473 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
475 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
476 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
477 uint8_t ingress; /**< 1 if the flow is ingress. */
478 uint32_t group; /**< The group index. */
479 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
481 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
482 struct mlx5_flow_dv dv;
484 struct mlx5_flow_verbs verbs;
486 bool external; /**< true if the flow is created external to PMD. */
489 /* Flow structure. */
491 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
492 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
493 struct mlx5_flow_rss rss; /**< RSS context. */
494 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
495 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
496 /**< Device flows that are part of the flow. */
497 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
498 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
501 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
502 const struct rte_flow_attr *attr,
503 const struct rte_flow_item items[],
504 const struct rte_flow_action actions[],
506 struct rte_flow_error *error);
507 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
508 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
509 const struct rte_flow_action actions[], struct rte_flow_error *error);
510 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
511 struct mlx5_flow *dev_flow,
512 const struct rte_flow_attr *attr,
513 const struct rte_flow_item items[],
514 const struct rte_flow_action actions[],
515 struct rte_flow_error *error);
516 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
517 struct rte_flow_error *error);
518 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
519 struct rte_flow *flow);
520 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
521 struct rte_flow *flow);
522 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
523 struct rte_flow *flow,
524 const struct rte_flow_action *actions,
526 struct rte_flow_error *error);
527 struct mlx5_flow_driver_ops {
528 mlx5_flow_validate_t validate;
529 mlx5_flow_prepare_t prepare;
530 mlx5_flow_translate_t translate;
531 mlx5_flow_apply_t apply;
532 mlx5_flow_remove_t remove;
533 mlx5_flow_destroy_t destroy;
534 mlx5_flow_query_t query;
537 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
538 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
539 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
540 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
544 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
545 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
546 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
547 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
549 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
550 bool external, uint32_t group, uint32_t *table,
551 struct rte_flow_error *error);
552 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
553 uint64_t layer_types,
554 uint64_t hash_fields);
555 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
556 uint32_t subpriority);
557 const struct rte_flow_action *mlx5_flow_find_action
558 (const struct rte_flow_action *actions,
559 enum rte_flow_action_type action);
560 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
561 const struct rte_flow_attr *attr,
562 struct rte_flow_error *error);
563 int mlx5_flow_validate_action_drop(uint64_t action_flags,
564 const struct rte_flow_attr *attr,
565 struct rte_flow_error *error);
566 int mlx5_flow_validate_action_flag(uint64_t action_flags,
567 const struct rte_flow_attr *attr,
568 struct rte_flow_error *error);
569 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
570 uint64_t action_flags,
571 const struct rte_flow_attr *attr,
572 struct rte_flow_error *error);
573 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
574 uint64_t action_flags,
575 struct rte_eth_dev *dev,
576 const struct rte_flow_attr *attr,
577 struct rte_flow_error *error);
578 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
579 uint64_t action_flags,
580 struct rte_eth_dev *dev,
581 const struct rte_flow_attr *attr,
583 struct rte_flow_error *error);
584 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
585 const struct rte_flow_attr *attributes,
586 struct rte_flow_error *error);
587 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
589 const uint8_t *nic_mask,
591 struct rte_flow_error *error);
592 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
594 struct rte_flow_error *error);
595 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
597 uint8_t target_protocol,
598 struct rte_flow_error *error);
599 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
601 const struct rte_flow_item *gre_item,
602 struct rte_flow_error *error);
603 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
607 const struct rte_flow_item_ipv4 *acc_mask,
608 struct rte_flow_error *error);
609 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
613 const struct rte_flow_item_ipv6 *acc_mask,
614 struct rte_flow_error *error);
615 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
616 const struct rte_flow_item *item,
619 struct rte_flow_error *error);
620 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
622 uint8_t target_protocol,
623 const struct rte_flow_item_tcp *flow_mask,
624 struct rte_flow_error *error);
625 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
627 uint8_t target_protocol,
628 struct rte_flow_error *error);
629 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
631 struct rte_eth_dev *dev,
632 struct rte_flow_error *error);
633 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
635 struct rte_flow_error *error);
636 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
638 struct rte_eth_dev *dev,
639 struct rte_flow_error *error);
640 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
642 uint8_t target_protocol,
643 struct rte_flow_error *error);
644 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
646 uint8_t target_protocol,
647 struct rte_flow_error *error);
648 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
650 uint8_t target_protocol,
651 struct rte_flow_error *error);
652 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
654 struct rte_eth_dev *dev,
655 struct rte_flow_error *error);
656 #endif /* RTE_PMD_MLX5_FLOW_H_ */