1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Private rte flow items. */
31 enum mlx5_rte_flow_item_type {
32 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
34 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
37 /* Private (internal) rte flow actions. */
38 enum mlx5_rte_flow_action_type {
39 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
40 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
41 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
42 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
45 /* Matches on selected register. */
46 struct mlx5_rte_flow_item_tag {
51 /* Modify selected register. */
52 struct mlx5_rte_flow_action_set_tag {
57 struct mlx5_flow_action_copy_mreg {
62 /* Matches on source queue. */
63 struct mlx5_rte_flow_item_tx_queue {
67 /* Feature name to allocate metadata register. */
68 enum mlx5_feature_name {
81 /* Pattern outer Layer bits. */
82 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
83 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
84 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
85 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
86 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
87 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
89 /* Pattern inner Layer bits. */
90 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
91 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
92 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
93 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
94 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
95 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
97 /* Pattern tunnel Layer bits. */
98 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
99 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
100 #define MLX5_FLOW_LAYER_GRE (1u << 14)
101 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
102 /* List of tunnel Layer bits continued below. */
104 /* General pattern items bits. */
105 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
106 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
107 #define MLX5_FLOW_ITEM_TAG (1u << 18)
108 #define MLX5_FLOW_ITEM_MARK (1u << 19)
110 /* Pattern MISC bits. */
111 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
112 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
113 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
115 /* Pattern tunnel Layer bits (continued). */
116 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
117 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
118 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
119 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
122 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
125 #define MLX5_FLOW_LAYER_OUTER_L3 \
126 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
127 #define MLX5_FLOW_LAYER_OUTER_L4 \
128 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
129 #define MLX5_FLOW_LAYER_OUTER \
130 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
131 MLX5_FLOW_LAYER_OUTER_L4)
133 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
134 #define MLX5_FLOW_LAYER_IPV4_LRO \
135 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
136 #define MLX5_FLOW_LAYER_IPV6_LRO \
137 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
140 #define MLX5_FLOW_LAYER_TUNNEL \
141 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
142 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
143 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
144 MLX5_FLOW_LAYER_GENEVE)
147 #define MLX5_FLOW_LAYER_INNER_L3 \
148 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
149 #define MLX5_FLOW_LAYER_INNER_L4 \
150 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
151 #define MLX5_FLOW_LAYER_INNER \
152 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
153 MLX5_FLOW_LAYER_INNER_L4)
156 #define MLX5_FLOW_LAYER_L2 \
157 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
158 #define MLX5_FLOW_LAYER_L3_IPV4 \
159 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
160 #define MLX5_FLOW_LAYER_L3_IPV6 \
161 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
162 #define MLX5_FLOW_LAYER_L3 \
163 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
164 #define MLX5_FLOW_LAYER_L4 \
165 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
168 #define MLX5_FLOW_ACTION_DROP (1u << 0)
169 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
170 #define MLX5_FLOW_ACTION_RSS (1u << 2)
171 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
172 #define MLX5_FLOW_ACTION_MARK (1u << 4)
173 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
174 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
175 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
176 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
177 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
178 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
179 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
180 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
181 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
182 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
183 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
184 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
185 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
186 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
187 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
188 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
189 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
190 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
191 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
192 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
193 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
194 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
195 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
196 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
197 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
198 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
199 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
200 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
201 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33)
202 #define MLX5_FLOW_ACTION_SET_META (1ull << 34)
204 #define MLX5_FLOW_FATE_ACTIONS \
205 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
206 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
208 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
209 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
210 MLX5_FLOW_ACTION_JUMP)
212 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
213 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
214 MLX5_FLOW_ACTION_RAW_ENCAP | \
215 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
217 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
218 MLX5_FLOW_ACTION_NVGRE_DECAP | \
219 MLX5_FLOW_ACTION_RAW_DECAP | \
220 MLX5_FLOW_ACTION_OF_POP_VLAN)
222 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
223 MLX5_FLOW_ACTION_SET_IPV4_DST | \
224 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
225 MLX5_FLOW_ACTION_SET_IPV6_DST | \
226 MLX5_FLOW_ACTION_SET_TP_SRC | \
227 MLX5_FLOW_ACTION_SET_TP_DST | \
228 MLX5_FLOW_ACTION_SET_TTL | \
229 MLX5_FLOW_ACTION_DEC_TTL | \
230 MLX5_FLOW_ACTION_SET_MAC_SRC | \
231 MLX5_FLOW_ACTION_SET_MAC_DST | \
232 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
233 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
234 MLX5_FLOW_ACTION_INC_TCP_ACK | \
235 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
236 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
237 MLX5_FLOW_ACTION_SET_TAG | \
238 MLX5_FLOW_ACTION_MARK_EXT | \
239 MLX5_FLOW_ACTION_SET_META)
241 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
242 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
244 #define IPPROTO_MPLS 137
247 /* UDP port number for MPLS */
248 #define MLX5_UDP_PORT_MPLS 6635
250 /* UDP port numbers for VxLAN. */
251 #define MLX5_UDP_PORT_VXLAN 4789
252 #define MLX5_UDP_PORT_VXLAN_GPE 4790
254 /* UDP port numbers for GENEVE. */
255 #define MLX5_UDP_PORT_GENEVE 6081
257 /* Priority reserved for default flows. */
258 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
261 * Number of sub priorities.
262 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
263 * matching on the NIC (firmware dependent) L4 most have the higher priority
264 * followed by L3 and ending with L2.
266 #define MLX5_PRIORITY_MAP_L2 2
267 #define MLX5_PRIORITY_MAP_L3 1
268 #define MLX5_PRIORITY_MAP_L4 0
269 #define MLX5_PRIORITY_MAP_MAX 3
271 /* Valid layer type for IPV4 RSS. */
272 #define MLX5_IPV4_LAYER_TYPES \
273 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
274 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
275 ETH_RSS_NONFRAG_IPV4_OTHER)
277 /* IBV hash source bits for IPV4. */
278 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
280 /* Valid layer type for IPV6 RSS. */
281 #define MLX5_IPV6_LAYER_TYPES \
282 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
283 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
284 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
286 /* IBV hash source bits for IPV6. */
287 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
290 /* Geneve header first 16Bit */
291 #define MLX5_GENEVE_VER_MASK 0x3
292 #define MLX5_GENEVE_VER_SHIFT 14
293 #define MLX5_GENEVE_VER_VAL(a) \
294 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
295 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
296 #define MLX5_GENEVE_OPTLEN_SHIFT 7
297 #define MLX5_GENEVE_OPTLEN_VAL(a) \
298 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
299 #define MLX5_GENEVE_OAMF_MASK 0x1
300 #define MLX5_GENEVE_OAMF_SHIFT 7
301 #define MLX5_GENEVE_OAMF_VAL(a) \
302 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
303 #define MLX5_GENEVE_CRITO_MASK 0x1
304 #define MLX5_GENEVE_CRITO_SHIFT 6
305 #define MLX5_GENEVE_CRITO_VAL(a) \
306 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
307 #define MLX5_GENEVE_RSVD_MASK 0x3F
308 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
310 * The length of the Geneve options fields, expressed in four byte multiples,
311 * not including the eight byte fixed tunnel.
313 #define MLX5_GENEVE_OPT_LEN_0 14
314 #define MLX5_GENEVE_OPT_LEN_1 63
316 enum mlx5_flow_drv_type {
319 MLX5_FLOW_TYPE_VERBS,
323 /* Matcher PRM representation */
324 struct mlx5_flow_dv_match_params {
326 /**< Size of match value. Do NOT split size and key! */
327 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
328 /**< Matcher value. This value is used as the mask or as a key. */
331 /* Matcher structure. */
332 struct mlx5_flow_dv_matcher {
333 LIST_ENTRY(mlx5_flow_dv_matcher) next;
334 /* Pointer to the next element. */
335 rte_atomic32_t refcnt; /**< Reference counter. */
336 void *matcher_object; /**< Pointer to DV matcher */
337 uint16_t crc; /**< CRC of key. */
338 uint16_t priority; /**< Priority of matcher. */
339 uint8_t egress; /**< Egress matcher. */
340 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
341 uint32_t group; /**< The matcher group. */
342 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
345 #define MLX5_ENCAP_MAX_LEN 132
347 /* Encap/decap resource structure. */
348 struct mlx5_flow_dv_encap_decap_resource {
349 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
350 /* Pointer to next element. */
351 rte_atomic32_t refcnt; /**< Reference counter. */
353 /**< Verbs encap/decap action object. */
354 uint8_t buf[MLX5_ENCAP_MAX_LEN];
356 uint8_t reformat_type;
358 uint64_t flags; /**< Flags for RDMA API. */
361 /* Tag resource structure. */
362 struct mlx5_flow_dv_tag_resource {
363 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
364 /* Pointer to next element. */
365 rte_atomic32_t refcnt; /**< Reference counter. */
367 /**< Verbs tag action object. */
368 uint32_t tag; /**< the tag value. */
372 * Number of modification commands.
373 * If extensive metadata registers are supported
374 * the maximal actions amount is 16 and 8 otherwise.
376 #define MLX5_MODIFY_NUM 16
377 #define MLX5_MODIFY_NUM_NO_MREG 8
379 /* Modify resource structure */
380 struct mlx5_flow_dv_modify_hdr_resource {
381 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
382 /* Pointer to next element. */
383 rte_atomic32_t refcnt; /**< Reference counter. */
384 struct ibv_flow_action *verbs_action;
385 /**< Verbs modify header action object. */
386 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
387 uint32_t actions_num; /**< Number of modification actions. */
388 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
389 /**< Modification actions. */
390 uint64_t flags; /**< Flags for RDMA API. */
393 /* Jump action resource structure. */
394 struct mlx5_flow_dv_jump_tbl_resource {
395 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
396 /* Pointer to next element. */
397 rte_atomic32_t refcnt; /**< Reference counter. */
398 void *action; /**< Pointer to the rdma core action. */
399 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
400 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
403 /* Port ID resource structure. */
404 struct mlx5_flow_dv_port_id_action_resource {
405 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
406 /* Pointer to next element. */
407 rte_atomic32_t refcnt; /**< Reference counter. */
409 /**< Verbs tag action object. */
410 uint32_t port_id; /**< Port ID value. */
413 /* Push VLAN action resource structure */
414 struct mlx5_flow_dv_push_vlan_action_resource {
415 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
416 /* Pointer to next element. */
417 rte_atomic32_t refcnt; /**< Reference counter. */
418 void *action; /**< Direct verbs action object. */
419 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
420 rte_be32_t vlan_tag; /**< VLAN tag value. */
423 /* Metadata register copy table entry. */
424 struct mlx5_flow_mreg_copy_resource {
426 * Hash list entry for copy table.
427 * - Key is 32/64-bit MARK action ID.
428 * - MUST be the first entry.
430 struct mlx5_hlist_entry hlist_ent;
431 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
432 /* List entry for device flows. */
433 uint32_t refcnt; /* Reference counter. */
434 uint32_t appcnt; /* Apply/Remove counter. */
435 struct rte_flow *flow; /* Built flow for copy. */
439 * Max number of actions per DV flow.
440 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
441 * In rdma-core file providers/mlx5/verbs.c
443 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
445 /* DV flows structure. */
446 struct mlx5_flow_dv {
447 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
449 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
450 struct mlx5_flow_dv_match_params value;
451 /**< Holds the value that the packet is compared to. */
452 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
453 /**< Pointer to encap/decap resource in cache. */
454 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
455 /**< Pointer to modify header resource in cache. */
456 struct ibv_flow *flow; /**< Installed flow. */
457 struct mlx5_flow_dv_jump_tbl_resource *jump;
458 /**< Pointer to the jump action resource. */
459 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
460 /**< Pointer to port ID action resource. */
461 struct mlx5_vf_vlan vf_vlan;
462 /**< Structure for VF VLAN workaround. */
463 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
464 /**< Pointer to push VLAN action resource in cache. */
465 struct mlx5_flow_dv_tag_resource *tag_resource;
466 /**< pointer to the tag action. */
467 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
468 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
471 int actions_n; /**< number of actions. */
474 /* Verbs specification header. */
475 struct ibv_spec_header {
476 enum ibv_flow_spec_type type;
480 /** Handles information leading to a drop fate. */
481 struct mlx5_flow_verbs {
482 LIST_ENTRY(mlx5_flow_verbs) next;
483 unsigned int size; /**< Size of the attribute. */
485 struct ibv_flow_attr *attr;
486 /**< Pointer to the Specification buffer. */
487 uint8_t *specs; /**< Pointer to the specifications. */
489 struct ibv_flow *flow; /**< Verbs flow pointer. */
490 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
491 struct mlx5_vf_vlan vf_vlan;
492 /**< Structure for VF VLAN workaround. */
495 struct mlx5_flow_rss {
497 uint32_t queue_num; /**< Number of entries in @p queue. */
498 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
499 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
500 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
503 /** Device flow structure. */
505 LIST_ENTRY(mlx5_flow) next;
506 struct rte_flow *flow; /**< Pointer to the main flow. */
508 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
510 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
511 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
512 uint8_t ingress; /**< 1 if the flow is ingress. */
513 uint32_t group; /**< The group index. */
514 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
516 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
517 struct mlx5_flow_dv dv;
519 struct mlx5_flow_verbs verbs;
521 uint32_t qrss_id; /**< Uniqie Q/RSS suffix subflow tag. */
522 bool external; /**< true if the flow is created external to PMD. */
525 /* Flow structure. */
527 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
528 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
529 struct mlx5_flow_rss rss; /**< RSS context. */
530 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
531 struct mlx5_flow_mreg_copy_resource *mreg_copy;
532 /**< pointer to metadata register copy table resource. */
533 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
534 /**< Device flows that are part of the flow. */
535 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
536 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
537 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
540 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
541 const struct rte_flow_attr *attr,
542 const struct rte_flow_item items[],
543 const struct rte_flow_action actions[],
545 struct rte_flow_error *error);
546 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
547 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
548 const struct rte_flow_action actions[], struct rte_flow_error *error);
549 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
550 struct mlx5_flow *dev_flow,
551 const struct rte_flow_attr *attr,
552 const struct rte_flow_item items[],
553 const struct rte_flow_action actions[],
554 struct rte_flow_error *error);
555 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
556 struct rte_flow_error *error);
557 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
558 struct rte_flow *flow);
559 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
560 struct rte_flow *flow);
561 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
562 struct rte_flow *flow,
563 const struct rte_flow_action *actions,
565 struct rte_flow_error *error);
566 struct mlx5_flow_driver_ops {
567 mlx5_flow_validate_t validate;
568 mlx5_flow_prepare_t prepare;
569 mlx5_flow_translate_t translate;
570 mlx5_flow_apply_t apply;
571 mlx5_flow_remove_t remove;
572 mlx5_flow_destroy_t destroy;
573 mlx5_flow_query_t query;
577 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
578 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
579 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
580 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
584 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
585 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
586 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
587 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
589 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
590 bool external, uint32_t group, uint32_t *table,
591 struct rte_flow_error *error);
592 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
593 uint64_t layer_types,
594 uint64_t hash_fields);
595 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
596 uint32_t subpriority);
597 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
598 enum mlx5_feature_name feature,
600 struct rte_flow_error *error);
601 const struct rte_flow_action *mlx5_flow_find_action
602 (const struct rte_flow_action *actions,
603 enum rte_flow_action_type action);
604 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
605 const struct rte_flow_attr *attr,
606 struct rte_flow_error *error);
607 int mlx5_flow_validate_action_drop(uint64_t action_flags,
608 const struct rte_flow_attr *attr,
609 struct rte_flow_error *error);
610 int mlx5_flow_validate_action_flag(uint64_t action_flags,
611 const struct rte_flow_attr *attr,
612 struct rte_flow_error *error);
613 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
614 uint64_t action_flags,
615 const struct rte_flow_attr *attr,
616 struct rte_flow_error *error);
617 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
618 uint64_t action_flags,
619 struct rte_eth_dev *dev,
620 const struct rte_flow_attr *attr,
621 struct rte_flow_error *error);
622 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
623 uint64_t action_flags,
624 struct rte_eth_dev *dev,
625 const struct rte_flow_attr *attr,
627 struct rte_flow_error *error);
628 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
629 const struct rte_flow_attr *attributes,
630 struct rte_flow_error *error);
631 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
633 const uint8_t *nic_mask,
635 struct rte_flow_error *error);
636 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
638 struct rte_flow_error *error);
639 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
641 uint8_t target_protocol,
642 struct rte_flow_error *error);
643 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
645 const struct rte_flow_item *gre_item,
646 struct rte_flow_error *error);
647 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
651 const struct rte_flow_item_ipv4 *acc_mask,
652 struct rte_flow_error *error);
653 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
657 const struct rte_flow_item_ipv6 *acc_mask,
658 struct rte_flow_error *error);
659 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
660 const struct rte_flow_item *item,
663 struct rte_flow_error *error);
664 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
666 uint8_t target_protocol,
667 const struct rte_flow_item_tcp *flow_mask,
668 struct rte_flow_error *error);
669 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
671 uint8_t target_protocol,
672 struct rte_flow_error *error);
673 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
675 struct rte_eth_dev *dev,
676 struct rte_flow_error *error);
677 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
679 struct rte_flow_error *error);
680 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
682 struct rte_eth_dev *dev,
683 struct rte_flow_error *error);
684 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
686 uint8_t target_protocol,
687 struct rte_flow_error *error);
688 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
690 uint8_t target_protocol,
691 struct rte_flow_error *error);
692 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
694 uint8_t target_protocol,
695 struct rte_flow_error *error);
696 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
698 struct rte_eth_dev *dev,
699 struct rte_flow_error *error);
700 #endif /* RTE_PMD_MLX5_FLOW_H_ */