1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
27 /* Pattern outer Layer bits. */
28 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
29 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
30 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
31 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
32 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
33 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
35 /* Pattern inner Layer bits. */
36 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
37 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
38 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
39 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
40 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
41 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
43 /* Pattern tunnel Layer bits. */
44 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
45 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
46 #define MLX5_FLOW_LAYER_GRE (1u << 14)
47 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
49 /* General pattern items bits. */
50 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
51 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
53 /* Pattern MISC bits. */
54 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
55 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
56 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)
58 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
59 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
62 #define MLX5_FLOW_LAYER_OUTER_L3 \
63 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
64 #define MLX5_FLOW_LAYER_OUTER_L4 \
65 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
66 #define MLX5_FLOW_LAYER_OUTER \
67 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
68 MLX5_FLOW_LAYER_OUTER_L4)
71 #define MLX5_FLOW_LAYER_TUNNEL \
72 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
73 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS | \
74 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP)
77 #define MLX5_FLOW_LAYER_INNER_L3 \
78 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
79 #define MLX5_FLOW_LAYER_INNER_L4 \
80 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
81 #define MLX5_FLOW_LAYER_INNER \
82 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
83 MLX5_FLOW_LAYER_INNER_L4)
86 #define MLX5_FLOW_LAYER_L2 \
87 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
88 #define MLX5_FLOW_LAYER_L3_IPV4 \
89 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
90 #define MLX5_FLOW_LAYER_L3_IPV6 \
91 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
92 #define MLX5_FLOW_LAYER_L3 \
93 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
94 #define MLX5_FLOW_LAYER_L4 \
95 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
98 #define MLX5_FLOW_ACTION_DROP (1u << 0)
99 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
100 #define MLX5_FLOW_ACTION_RSS (1u << 2)
101 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
102 #define MLX5_FLOW_ACTION_MARK (1u << 4)
103 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
104 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
105 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
106 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
107 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
108 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
109 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
110 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
111 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
112 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
113 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
114 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
115 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
116 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
117 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
118 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
119 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
120 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
121 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
122 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
123 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
124 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
125 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
126 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
127 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
128 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
129 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
131 #define MLX5_FLOW_FATE_ACTIONS \
132 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
133 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
135 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
136 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
137 MLX5_FLOW_ACTION_JUMP)
139 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
140 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
141 MLX5_FLOW_ACTION_RAW_ENCAP)
143 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
144 MLX5_FLOW_ACTION_NVGRE_DECAP | \
145 MLX5_FLOW_ACTION_RAW_DECAP)
147 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
148 MLX5_FLOW_ACTION_SET_IPV4_DST | \
149 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
150 MLX5_FLOW_ACTION_SET_IPV6_DST | \
151 MLX5_FLOW_ACTION_SET_TP_SRC | \
152 MLX5_FLOW_ACTION_SET_TP_DST | \
153 MLX5_FLOW_ACTION_SET_TTL | \
154 MLX5_FLOW_ACTION_DEC_TTL | \
155 MLX5_FLOW_ACTION_SET_MAC_SRC | \
156 MLX5_FLOW_ACTION_SET_MAC_DST | \
157 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
158 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
159 MLX5_FLOW_ACTION_INC_TCP_ACK | \
160 MLX5_FLOW_ACTION_DEC_TCP_ACK)
163 #define IPPROTO_MPLS 137
166 /* UDP port number for MPLS */
167 #define MLX5_UDP_PORT_MPLS 6635
169 /* UDP port numbers for VxLAN. */
170 #define MLX5_UDP_PORT_VXLAN 4789
171 #define MLX5_UDP_PORT_VXLAN_GPE 4790
173 /* Priority reserved for default flows. */
174 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
177 * Number of sub priorities.
178 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
179 * matching on the NIC (firmware dependent) L4 most have the higher priority
180 * followed by L3 and ending with L2.
182 #define MLX5_PRIORITY_MAP_L2 2
183 #define MLX5_PRIORITY_MAP_L3 1
184 #define MLX5_PRIORITY_MAP_L4 0
185 #define MLX5_PRIORITY_MAP_MAX 3
187 /* Valid layer type for IPV4 RSS. */
188 #define MLX5_IPV4_LAYER_TYPES \
189 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
190 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
191 ETH_RSS_NONFRAG_IPV4_OTHER)
193 /* IBV hash source bits for IPV4. */
194 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
196 /* Valid layer type for IPV6 RSS. */
197 #define MLX5_IPV6_LAYER_TYPES \
198 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
199 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
200 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
202 /* IBV hash source bits for IPV6. */
203 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
205 enum mlx5_flow_drv_type {
208 MLX5_FLOW_TYPE_VERBS,
212 /* Matcher PRM representation */
213 struct mlx5_flow_dv_match_params {
215 /**< Size of match value. Do NOT split size and key! */
216 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
217 /**< Matcher value. This value is used as the mask or as a key. */
220 /* Matcher structure. */
221 struct mlx5_flow_dv_matcher {
222 LIST_ENTRY(mlx5_flow_dv_matcher) next;
223 /* Pointer to the next element. */
224 rte_atomic32_t refcnt; /**< Reference counter. */
225 void *matcher_object; /**< Pointer to DV matcher */
226 uint16_t crc; /**< CRC of key. */
227 uint16_t priority; /**< Priority of matcher. */
228 uint8_t egress; /**< Egress matcher. */
229 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
230 uint32_t group; /**< The matcher group. */
231 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
234 #define MLX5_ENCAP_MAX_LEN 132
236 /* Encap/decap resource structure. */
237 struct mlx5_flow_dv_encap_decap_resource {
238 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
239 /* Pointer to next element. */
240 rte_atomic32_t refcnt; /**< Reference counter. */
242 /**< Verbs encap/decap action object. */
243 uint8_t buf[MLX5_ENCAP_MAX_LEN];
245 uint8_t reformat_type;
247 uint64_t flags; /**< Flags for RDMA API. */
250 /* Tag resource structure. */
251 struct mlx5_flow_dv_tag_resource {
252 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
253 /* Pointer to next element. */
254 rte_atomic32_t refcnt; /**< Reference counter. */
256 /**< Verbs tag action object. */
257 uint32_t tag; /**< the tag value. */
260 /* Number of modification commands. */
261 #define MLX5_MODIFY_NUM 8
263 /* Modify resource structure */
264 struct mlx5_flow_dv_modify_hdr_resource {
265 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
266 /* Pointer to next element. */
267 rte_atomic32_t refcnt; /**< Reference counter. */
268 struct ibv_flow_action *verbs_action;
269 /**< Verbs modify header action object. */
270 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
271 uint32_t actions_num; /**< Number of modification actions. */
272 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
273 /**< Modification actions. */
274 uint64_t flags; /**< Flags for RDMA API. */
277 /* Jump action resource structure. */
278 struct mlx5_flow_dv_jump_tbl_resource {
279 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
280 /* Pointer to next element. */
281 rte_atomic32_t refcnt; /**< Reference counter. */
282 void *action; /**< Pointer to the rdma core action. */
283 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
284 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
287 /* Port ID resource structure. */
288 struct mlx5_flow_dv_port_id_action_resource {
289 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
290 /* Pointer to next element. */
291 rte_atomic32_t refcnt; /**< Reference counter. */
293 /**< Verbs tag action object. */
294 uint32_t port_id; /**< Port ID value. */
298 * Max number of actions per DV flow.
299 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
300 * In rdma-core file providers/mlx5/verbs.c
302 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
304 /* DV flows structure. */
305 struct mlx5_flow_dv {
306 uint64_t hash_fields; /**< Fields that participate in the hash. */
307 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
309 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
310 struct mlx5_flow_dv_match_params value;
311 /**< Holds the value that the packet is compared to. */
312 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
313 /**< Pointer to encap/decap resource in cache. */
314 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
315 /**< Pointer to modify header resource in cache. */
316 struct ibv_flow *flow; /**< Installed flow. */
317 struct mlx5_flow_dv_jump_tbl_resource *jump;
318 /**< Pointer to the jump action resource. */
319 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
320 /**< Pointer to port ID action resource. */
321 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
322 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
325 int actions_n; /**< number of actions. */
328 /* Verbs specification header. */
329 struct ibv_spec_header {
330 enum ibv_flow_spec_type type;
334 /** Handles information leading to a drop fate. */
335 struct mlx5_flow_verbs {
336 LIST_ENTRY(mlx5_flow_verbs) next;
337 unsigned int size; /**< Size of the attribute. */
339 struct ibv_flow_attr *attr;
340 /**< Pointer to the Specification buffer. */
341 uint8_t *specs; /**< Pointer to the specifications. */
343 struct ibv_flow *flow; /**< Verbs flow pointer. */
344 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
345 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
348 /** Device flow structure. */
350 LIST_ENTRY(mlx5_flow) next;
351 struct rte_flow *flow; /**< Pointer to the main flow. */
353 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
355 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
356 struct mlx5_flow_dv dv;
358 struct mlx5_flow_verbs verbs;
362 /* Counters information. */
363 struct mlx5_flow_counter {
364 LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */
365 uint32_t shared:1; /**< Share counter ID with other flow rules. */
366 uint32_t ref_cnt:31; /**< Reference counter. */
367 uint32_t id; /**< Counter ID. */
368 union { /**< Holds the counters for the rule. */
369 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
370 struct ibv_counter_set *cs;
371 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
372 struct ibv_counters *cs;
374 struct mlx5_devx_counter_set *dcs;
376 uint64_t hits; /**< Number of packets matched by the rule. */
377 uint64_t bytes; /**< Number of bytes matched by the rule. */
378 void *action; /**< Pointer to the dv action. */
381 /* Flow structure. */
383 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
384 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
385 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
386 struct mlx5_flow_dv_tag_resource *tag_resource;
387 /**< pointer to the tag action. */
388 struct rte_flow_action_rss rss;/**< RSS context. */
389 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
390 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
391 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
392 /**< Device flows that are part of the flow. */
394 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
395 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
396 uint8_t ingress; /**< 1 if the flow is ingress. */
397 uint32_t group; /**< The group index. */
398 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
401 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
402 const struct rte_flow_attr *attr,
403 const struct rte_flow_item items[],
404 const struct rte_flow_action actions[],
405 struct rte_flow_error *error);
406 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
407 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
408 const struct rte_flow_action actions[], struct rte_flow_error *error);
409 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
410 struct mlx5_flow *dev_flow,
411 const struct rte_flow_attr *attr,
412 const struct rte_flow_item items[],
413 const struct rte_flow_action actions[],
414 struct rte_flow_error *error);
415 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
416 struct rte_flow_error *error);
417 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
418 struct rte_flow *flow);
419 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
420 struct rte_flow *flow);
421 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
422 struct rte_flow *flow,
423 const struct rte_flow_action *actions,
425 struct rte_flow_error *error);
426 struct mlx5_flow_driver_ops {
427 mlx5_flow_validate_t validate;
428 mlx5_flow_prepare_t prepare;
429 mlx5_flow_translate_t translate;
430 mlx5_flow_apply_t apply;
431 mlx5_flow_remove_t remove;
432 mlx5_flow_destroy_t destroy;
433 mlx5_flow_query_t query;
438 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
439 uint64_t layer_types,
440 uint64_t hash_fields);
441 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
442 uint32_t subpriority);
443 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
444 const struct rte_flow_attr *attr,
445 struct rte_flow_error *error);
446 int mlx5_flow_validate_action_drop(uint64_t action_flags,
447 const struct rte_flow_attr *attr,
448 struct rte_flow_error *error);
449 int mlx5_flow_validate_action_flag(uint64_t action_flags,
450 const struct rte_flow_attr *attr,
451 struct rte_flow_error *error);
452 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
453 uint64_t action_flags,
454 const struct rte_flow_attr *attr,
455 struct rte_flow_error *error);
456 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
457 uint64_t action_flags,
458 struct rte_eth_dev *dev,
459 const struct rte_flow_attr *attr,
460 struct rte_flow_error *error);
461 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
462 uint64_t action_flags,
463 struct rte_eth_dev *dev,
464 const struct rte_flow_attr *attr,
466 struct rte_flow_error *error);
467 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
468 const struct rte_flow_attr *attributes,
469 struct rte_flow_error *error);
470 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
472 const uint8_t *nic_mask,
474 struct rte_flow_error *error);
475 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
477 struct rte_flow_error *error);
478 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
480 uint8_t target_protocol,
481 struct rte_flow_error *error);
482 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
484 const struct rte_flow_item *gre_item,
485 struct rte_flow_error *error);
486 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
488 const struct rte_flow_item_ipv4 *acc_mask,
489 struct rte_flow_error *error);
490 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
492 const struct rte_flow_item_ipv6 *acc_mask,
493 struct rte_flow_error *error);
494 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
495 const struct rte_flow_item *item,
498 struct rte_flow_error *error);
499 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
501 uint8_t target_protocol,
502 const struct rte_flow_item_tcp *flow_mask,
503 struct rte_flow_error *error);
504 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
506 uint8_t target_protocol,
507 struct rte_flow_error *error);
508 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
510 struct rte_flow_error *error);
511 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
513 struct rte_flow_error *error);
514 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
516 struct rte_eth_dev *dev,
517 struct rte_flow_error *error);
518 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
520 uint8_t target_protocol,
521 struct rte_flow_error *error);
522 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
524 uint8_t target_protocol,
525 struct rte_flow_error *error);
527 #endif /* RTE_PMD_MLX5_FLOW_H_ */