1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Private rte flow items. */
31 enum mlx5_rte_flow_item_type {
32 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
34 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
37 /* Private (internal) rte flow actions. */
38 enum mlx5_rte_flow_action_type {
39 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
40 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
41 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
44 /* Matches on selected register. */
45 struct mlx5_rte_flow_item_tag {
50 /* Modify selected register. */
51 struct mlx5_rte_flow_action_set_tag {
56 struct mlx5_flow_action_copy_mreg {
61 /* Matches on source queue. */
62 struct mlx5_rte_flow_item_tx_queue {
66 /* Feature name to allocate metadata register. */
67 enum mlx5_feature_name {
78 /* Pattern outer Layer bits. */
79 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
80 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
81 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
82 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
83 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
84 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
86 /* Pattern inner Layer bits. */
87 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
88 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
89 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
90 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
91 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
92 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
94 /* Pattern tunnel Layer bits. */
95 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
96 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
97 #define MLX5_FLOW_LAYER_GRE (1u << 14)
98 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
99 /* List of tunnel Layer bits continued below. */
101 /* General pattern items bits. */
102 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
103 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
104 #define MLX5_FLOW_ITEM_TAG (1u << 18)
106 /* Pattern MISC bits. */
107 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
108 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
109 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
111 /* Pattern tunnel Layer bits (continued). */
112 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
113 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
114 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
115 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
118 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
121 #define MLX5_FLOW_LAYER_OUTER_L3 \
122 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
123 #define MLX5_FLOW_LAYER_OUTER_L4 \
124 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
125 #define MLX5_FLOW_LAYER_OUTER \
126 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
127 MLX5_FLOW_LAYER_OUTER_L4)
129 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
130 #define MLX5_FLOW_LAYER_IPV4_LRO \
131 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
132 #define MLX5_FLOW_LAYER_IPV6_LRO \
133 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
136 #define MLX5_FLOW_LAYER_TUNNEL \
137 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
138 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
139 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
140 MLX5_FLOW_LAYER_GENEVE)
143 #define MLX5_FLOW_LAYER_INNER_L3 \
144 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
145 #define MLX5_FLOW_LAYER_INNER_L4 \
146 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
147 #define MLX5_FLOW_LAYER_INNER \
148 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
149 MLX5_FLOW_LAYER_INNER_L4)
152 #define MLX5_FLOW_LAYER_L2 \
153 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
154 #define MLX5_FLOW_LAYER_L3_IPV4 \
155 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
156 #define MLX5_FLOW_LAYER_L3_IPV6 \
157 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
158 #define MLX5_FLOW_LAYER_L3 \
159 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
160 #define MLX5_FLOW_LAYER_L4 \
161 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
164 #define MLX5_FLOW_ACTION_DROP (1u << 0)
165 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
166 #define MLX5_FLOW_ACTION_RSS (1u << 2)
167 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
168 #define MLX5_FLOW_ACTION_MARK (1u << 4)
169 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
170 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
171 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
172 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
173 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
174 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
175 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
176 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
177 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
178 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
179 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
180 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
181 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
182 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
183 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
184 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
185 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
186 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
187 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
188 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
189 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
190 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
191 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
192 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
193 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
194 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
195 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
196 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
198 #define MLX5_FLOW_FATE_ACTIONS \
199 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
200 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
202 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
203 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
204 MLX5_FLOW_ACTION_JUMP)
206 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
207 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
208 MLX5_FLOW_ACTION_RAW_ENCAP | \
209 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
211 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
212 MLX5_FLOW_ACTION_NVGRE_DECAP | \
213 MLX5_FLOW_ACTION_RAW_DECAP | \
214 MLX5_FLOW_ACTION_OF_POP_VLAN)
216 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
217 MLX5_FLOW_ACTION_SET_IPV4_DST | \
218 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
219 MLX5_FLOW_ACTION_SET_IPV6_DST | \
220 MLX5_FLOW_ACTION_SET_TP_SRC | \
221 MLX5_FLOW_ACTION_SET_TP_DST | \
222 MLX5_FLOW_ACTION_SET_TTL | \
223 MLX5_FLOW_ACTION_DEC_TTL | \
224 MLX5_FLOW_ACTION_SET_MAC_SRC | \
225 MLX5_FLOW_ACTION_SET_MAC_DST | \
226 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
227 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
228 MLX5_FLOW_ACTION_INC_TCP_ACK | \
229 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
230 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
231 MLX5_FLOW_ACTION_SET_TAG)
233 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
234 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
236 #define IPPROTO_MPLS 137
239 /* UDP port number for MPLS */
240 #define MLX5_UDP_PORT_MPLS 6635
242 /* UDP port numbers for VxLAN. */
243 #define MLX5_UDP_PORT_VXLAN 4789
244 #define MLX5_UDP_PORT_VXLAN_GPE 4790
246 /* UDP port numbers for GENEVE. */
247 #define MLX5_UDP_PORT_GENEVE 6081
249 /* Priority reserved for default flows. */
250 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
253 * Number of sub priorities.
254 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
255 * matching on the NIC (firmware dependent) L4 most have the higher priority
256 * followed by L3 and ending with L2.
258 #define MLX5_PRIORITY_MAP_L2 2
259 #define MLX5_PRIORITY_MAP_L3 1
260 #define MLX5_PRIORITY_MAP_L4 0
261 #define MLX5_PRIORITY_MAP_MAX 3
263 /* Valid layer type for IPV4 RSS. */
264 #define MLX5_IPV4_LAYER_TYPES \
265 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
266 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
267 ETH_RSS_NONFRAG_IPV4_OTHER)
269 /* IBV hash source bits for IPV4. */
270 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
272 /* Valid layer type for IPV6 RSS. */
273 #define MLX5_IPV6_LAYER_TYPES \
274 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
275 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
276 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
278 /* IBV hash source bits for IPV6. */
279 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
282 /* Geneve header first 16Bit */
283 #define MLX5_GENEVE_VER_MASK 0x3
284 #define MLX5_GENEVE_VER_SHIFT 14
285 #define MLX5_GENEVE_VER_VAL(a) \
286 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
287 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
288 #define MLX5_GENEVE_OPTLEN_SHIFT 7
289 #define MLX5_GENEVE_OPTLEN_VAL(a) \
290 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
291 #define MLX5_GENEVE_OAMF_MASK 0x1
292 #define MLX5_GENEVE_OAMF_SHIFT 7
293 #define MLX5_GENEVE_OAMF_VAL(a) \
294 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
295 #define MLX5_GENEVE_CRITO_MASK 0x1
296 #define MLX5_GENEVE_CRITO_SHIFT 6
297 #define MLX5_GENEVE_CRITO_VAL(a) \
298 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
299 #define MLX5_GENEVE_RSVD_MASK 0x3F
300 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
302 * The length of the Geneve options fields, expressed in four byte multiples,
303 * not including the eight byte fixed tunnel.
305 #define MLX5_GENEVE_OPT_LEN_0 14
306 #define MLX5_GENEVE_OPT_LEN_1 63
308 enum mlx5_flow_drv_type {
311 MLX5_FLOW_TYPE_VERBS,
315 /* Matcher PRM representation */
316 struct mlx5_flow_dv_match_params {
318 /**< Size of match value. Do NOT split size and key! */
319 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
320 /**< Matcher value. This value is used as the mask or as a key. */
323 /* Matcher structure. */
324 struct mlx5_flow_dv_matcher {
325 LIST_ENTRY(mlx5_flow_dv_matcher) next;
326 /* Pointer to the next element. */
327 rte_atomic32_t refcnt; /**< Reference counter. */
328 void *matcher_object; /**< Pointer to DV matcher */
329 uint16_t crc; /**< CRC of key. */
330 uint16_t priority; /**< Priority of matcher. */
331 uint8_t egress; /**< Egress matcher. */
332 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
333 uint32_t group; /**< The matcher group. */
334 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
337 #define MLX5_ENCAP_MAX_LEN 132
339 /* Encap/decap resource structure. */
340 struct mlx5_flow_dv_encap_decap_resource {
341 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
342 /* Pointer to next element. */
343 rte_atomic32_t refcnt; /**< Reference counter. */
345 /**< Verbs encap/decap action object. */
346 uint8_t buf[MLX5_ENCAP_MAX_LEN];
348 uint8_t reformat_type;
350 uint64_t flags; /**< Flags for RDMA API. */
353 /* Tag resource structure. */
354 struct mlx5_flow_dv_tag_resource {
355 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
356 /* Pointer to next element. */
357 rte_atomic32_t refcnt; /**< Reference counter. */
359 /**< Verbs tag action object. */
360 uint32_t tag; /**< the tag value. */
364 * Number of modification commands.
365 * If extensive metadata registers are supported
366 * the maximal actions amount is 16 and 8 otherwise.
368 #define MLX5_MODIFY_NUM 16
369 #define MLX5_MODIFY_NUM_NO_MREG 8
371 /* Modify resource structure */
372 struct mlx5_flow_dv_modify_hdr_resource {
373 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
374 /* Pointer to next element. */
375 rte_atomic32_t refcnt; /**< Reference counter. */
376 struct ibv_flow_action *verbs_action;
377 /**< Verbs modify header action object. */
378 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
379 uint32_t actions_num; /**< Number of modification actions. */
380 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
381 /**< Modification actions. */
382 uint64_t flags; /**< Flags for RDMA API. */
385 /* Jump action resource structure. */
386 struct mlx5_flow_dv_jump_tbl_resource {
387 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
388 /* Pointer to next element. */
389 rte_atomic32_t refcnt; /**< Reference counter. */
390 void *action; /**< Pointer to the rdma core action. */
391 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
392 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
395 /* Port ID resource structure. */
396 struct mlx5_flow_dv_port_id_action_resource {
397 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
398 /* Pointer to next element. */
399 rte_atomic32_t refcnt; /**< Reference counter. */
401 /**< Verbs tag action object. */
402 uint32_t port_id; /**< Port ID value. */
405 /* Push VLAN action resource structure */
406 struct mlx5_flow_dv_push_vlan_action_resource {
407 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
408 /* Pointer to next element. */
409 rte_atomic32_t refcnt; /**< Reference counter. */
410 void *action; /**< Direct verbs action object. */
411 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
412 rte_be32_t vlan_tag; /**< VLAN tag value. */
416 * Max number of actions per DV flow.
417 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
418 * In rdma-core file providers/mlx5/verbs.c
420 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
422 /* DV flows structure. */
423 struct mlx5_flow_dv {
424 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
426 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
427 struct mlx5_flow_dv_match_params value;
428 /**< Holds the value that the packet is compared to. */
429 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
430 /**< Pointer to encap/decap resource in cache. */
431 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
432 /**< Pointer to modify header resource in cache. */
433 struct ibv_flow *flow; /**< Installed flow. */
434 struct mlx5_flow_dv_jump_tbl_resource *jump;
435 /**< Pointer to the jump action resource. */
436 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
437 /**< Pointer to port ID action resource. */
438 struct mlx5_vf_vlan vf_vlan;
439 /**< Structure for VF VLAN workaround. */
440 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
441 /**< Pointer to push VLAN action resource in cache. */
442 struct mlx5_flow_dv_tag_resource *tag_resource;
443 /**< pointer to the tag action. */
444 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
445 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
448 int actions_n; /**< number of actions. */
451 /* Verbs specification header. */
452 struct ibv_spec_header {
453 enum ibv_flow_spec_type type;
457 /** Handles information leading to a drop fate. */
458 struct mlx5_flow_verbs {
459 LIST_ENTRY(mlx5_flow_verbs) next;
460 unsigned int size; /**< Size of the attribute. */
462 struct ibv_flow_attr *attr;
463 /**< Pointer to the Specification buffer. */
464 uint8_t *specs; /**< Pointer to the specifications. */
466 struct ibv_flow *flow; /**< Verbs flow pointer. */
467 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
468 struct mlx5_vf_vlan vf_vlan;
469 /**< Structure for VF VLAN workaround. */
472 struct mlx5_flow_rss {
474 uint32_t queue_num; /**< Number of entries in @p queue. */
475 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
476 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
477 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
480 /** Device flow structure. */
482 LIST_ENTRY(mlx5_flow) next;
483 struct rte_flow *flow; /**< Pointer to the main flow. */
485 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
487 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
488 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
489 uint8_t ingress; /**< 1 if the flow is ingress. */
490 uint32_t group; /**< The group index. */
491 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
493 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
494 struct mlx5_flow_dv dv;
496 struct mlx5_flow_verbs verbs;
498 bool external; /**< true if the flow is created external to PMD. */
501 /* Flow structure. */
503 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
504 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
505 struct mlx5_flow_rss rss; /**< RSS context. */
506 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
507 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
508 /**< Device flows that are part of the flow. */
509 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
510 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
513 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
514 const struct rte_flow_attr *attr,
515 const struct rte_flow_item items[],
516 const struct rte_flow_action actions[],
518 struct rte_flow_error *error);
519 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
520 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
521 const struct rte_flow_action actions[], struct rte_flow_error *error);
522 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
523 struct mlx5_flow *dev_flow,
524 const struct rte_flow_attr *attr,
525 const struct rte_flow_item items[],
526 const struct rte_flow_action actions[],
527 struct rte_flow_error *error);
528 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
529 struct rte_flow_error *error);
530 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
531 struct rte_flow *flow);
532 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
533 struct rte_flow *flow);
534 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
535 struct rte_flow *flow,
536 const struct rte_flow_action *actions,
538 struct rte_flow_error *error);
539 struct mlx5_flow_driver_ops {
540 mlx5_flow_validate_t validate;
541 mlx5_flow_prepare_t prepare;
542 mlx5_flow_translate_t translate;
543 mlx5_flow_apply_t apply;
544 mlx5_flow_remove_t remove;
545 mlx5_flow_destroy_t destroy;
546 mlx5_flow_query_t query;
550 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
551 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
552 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
553 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
557 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
558 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
559 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
560 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
562 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
563 bool external, uint32_t group, uint32_t *table,
564 struct rte_flow_error *error);
565 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
566 uint64_t layer_types,
567 uint64_t hash_fields);
568 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
569 uint32_t subpriority);
570 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
571 enum mlx5_feature_name feature,
573 struct rte_flow_error *error);
574 const struct rte_flow_action *mlx5_flow_find_action
575 (const struct rte_flow_action *actions,
576 enum rte_flow_action_type action);
577 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
578 const struct rte_flow_attr *attr,
579 struct rte_flow_error *error);
580 int mlx5_flow_validate_action_drop(uint64_t action_flags,
581 const struct rte_flow_attr *attr,
582 struct rte_flow_error *error);
583 int mlx5_flow_validate_action_flag(uint64_t action_flags,
584 const struct rte_flow_attr *attr,
585 struct rte_flow_error *error);
586 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
587 uint64_t action_flags,
588 const struct rte_flow_attr *attr,
589 struct rte_flow_error *error);
590 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
591 uint64_t action_flags,
592 struct rte_eth_dev *dev,
593 const struct rte_flow_attr *attr,
594 struct rte_flow_error *error);
595 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
596 uint64_t action_flags,
597 struct rte_eth_dev *dev,
598 const struct rte_flow_attr *attr,
600 struct rte_flow_error *error);
601 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
602 const struct rte_flow_attr *attributes,
603 struct rte_flow_error *error);
604 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
606 const uint8_t *nic_mask,
608 struct rte_flow_error *error);
609 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
611 struct rte_flow_error *error);
612 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
614 uint8_t target_protocol,
615 struct rte_flow_error *error);
616 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
618 const struct rte_flow_item *gre_item,
619 struct rte_flow_error *error);
620 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
624 const struct rte_flow_item_ipv4 *acc_mask,
625 struct rte_flow_error *error);
626 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
630 const struct rte_flow_item_ipv6 *acc_mask,
631 struct rte_flow_error *error);
632 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
633 const struct rte_flow_item *item,
636 struct rte_flow_error *error);
637 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
639 uint8_t target_protocol,
640 const struct rte_flow_item_tcp *flow_mask,
641 struct rte_flow_error *error);
642 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
644 uint8_t target_protocol,
645 struct rte_flow_error *error);
646 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
648 struct rte_eth_dev *dev,
649 struct rte_flow_error *error);
650 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
652 struct rte_flow_error *error);
653 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
655 struct rte_eth_dev *dev,
656 struct rte_flow_error *error);
657 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
659 uint8_t target_protocol,
660 struct rte_flow_error *error);
661 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
663 uint8_t target_protocol,
664 struct rte_flow_error *error);
665 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
667 uint8_t target_protocol,
668 struct rte_flow_error *error);
669 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
671 struct rte_eth_dev *dev,
672 struct rte_flow_error *error);
673 #endif /* RTE_PMD_MLX5_FLOW_H_ */