1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
31 /* Private rte flow items. */
32 enum mlx5_rte_flow_item_type {
33 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
35 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
38 /* Private (internal) rte flow actions. */
39 enum mlx5_rte_flow_action_type {
40 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
41 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
42 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
43 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
46 /* Matches on selected register. */
47 struct mlx5_rte_flow_item_tag {
52 /* Modify selected register. */
53 struct mlx5_rte_flow_action_set_tag {
58 struct mlx5_flow_action_copy_mreg {
63 /* Matches on source queue. */
64 struct mlx5_rte_flow_item_tx_queue {
68 /* Feature name to allocate metadata register. */
69 enum mlx5_feature_name {
82 /* Pattern outer Layer bits. */
83 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
84 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
85 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
86 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
87 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
88 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
90 /* Pattern inner Layer bits. */
91 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
92 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
93 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
94 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
95 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
96 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
98 /* Pattern tunnel Layer bits. */
99 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
100 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
101 #define MLX5_FLOW_LAYER_GRE (1u << 14)
102 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
103 /* List of tunnel Layer bits continued below. */
105 /* General pattern items bits. */
106 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
107 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
108 #define MLX5_FLOW_ITEM_TAG (1u << 18)
109 #define MLX5_FLOW_ITEM_MARK (1u << 19)
111 /* Pattern MISC bits. */
112 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
113 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
114 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
116 /* Pattern tunnel Layer bits (continued). */
117 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
118 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
119 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
120 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
123 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
126 #define MLX5_FLOW_LAYER_OUTER_L3 \
127 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
128 #define MLX5_FLOW_LAYER_OUTER_L4 \
129 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
130 #define MLX5_FLOW_LAYER_OUTER \
131 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
132 MLX5_FLOW_LAYER_OUTER_L4)
134 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
135 #define MLX5_FLOW_LAYER_IPV4_LRO \
136 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
137 #define MLX5_FLOW_LAYER_IPV6_LRO \
138 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
141 #define MLX5_FLOW_LAYER_TUNNEL \
142 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
143 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
144 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
145 MLX5_FLOW_LAYER_GENEVE)
148 #define MLX5_FLOW_LAYER_INNER_L3 \
149 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
150 #define MLX5_FLOW_LAYER_INNER_L4 \
151 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
152 #define MLX5_FLOW_LAYER_INNER \
153 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
154 MLX5_FLOW_LAYER_INNER_L4)
157 #define MLX5_FLOW_LAYER_L2 \
158 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
159 #define MLX5_FLOW_LAYER_L3_IPV4 \
160 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
161 #define MLX5_FLOW_LAYER_L3_IPV6 \
162 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
163 #define MLX5_FLOW_LAYER_L3 \
164 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
165 #define MLX5_FLOW_LAYER_L4 \
166 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
169 #define MLX5_FLOW_ACTION_DROP (1u << 0)
170 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
171 #define MLX5_FLOW_ACTION_RSS (1u << 2)
172 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
173 #define MLX5_FLOW_ACTION_MARK (1u << 4)
174 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
175 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
176 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
177 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
178 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
179 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
180 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
181 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
182 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
183 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
184 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
185 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
186 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
187 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
188 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
189 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
190 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
191 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
192 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
193 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
194 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
195 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
196 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
197 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
198 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
199 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
200 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
201 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
202 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33)
203 #define MLX5_FLOW_ACTION_SET_META (1ull << 34)
205 #define MLX5_FLOW_FATE_ACTIONS \
206 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
207 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
209 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
210 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
211 MLX5_FLOW_ACTION_JUMP)
213 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
214 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
215 MLX5_FLOW_ACTION_RAW_ENCAP | \
216 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
218 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
219 MLX5_FLOW_ACTION_NVGRE_DECAP | \
220 MLX5_FLOW_ACTION_RAW_DECAP | \
221 MLX5_FLOW_ACTION_OF_POP_VLAN)
223 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
224 MLX5_FLOW_ACTION_SET_IPV4_DST | \
225 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
226 MLX5_FLOW_ACTION_SET_IPV6_DST | \
227 MLX5_FLOW_ACTION_SET_TP_SRC | \
228 MLX5_FLOW_ACTION_SET_TP_DST | \
229 MLX5_FLOW_ACTION_SET_TTL | \
230 MLX5_FLOW_ACTION_DEC_TTL | \
231 MLX5_FLOW_ACTION_SET_MAC_SRC | \
232 MLX5_FLOW_ACTION_SET_MAC_DST | \
233 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
234 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
235 MLX5_FLOW_ACTION_INC_TCP_ACK | \
236 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
237 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
238 MLX5_FLOW_ACTION_SET_TAG | \
239 MLX5_FLOW_ACTION_MARK_EXT | \
240 MLX5_FLOW_ACTION_SET_META)
242 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
243 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
245 #define IPPROTO_MPLS 137
248 /* UDP port number for MPLS */
249 #define MLX5_UDP_PORT_MPLS 6635
251 /* UDP port numbers for VxLAN. */
252 #define MLX5_UDP_PORT_VXLAN 4789
253 #define MLX5_UDP_PORT_VXLAN_GPE 4790
255 /* UDP port numbers for GENEVE. */
256 #define MLX5_UDP_PORT_GENEVE 6081
258 /* Priority reserved for default flows. */
259 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
262 * Number of sub priorities.
263 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
264 * matching on the NIC (firmware dependent) L4 most have the higher priority
265 * followed by L3 and ending with L2.
267 #define MLX5_PRIORITY_MAP_L2 2
268 #define MLX5_PRIORITY_MAP_L3 1
269 #define MLX5_PRIORITY_MAP_L4 0
270 #define MLX5_PRIORITY_MAP_MAX 3
272 /* Valid layer type for IPV4 RSS. */
273 #define MLX5_IPV4_LAYER_TYPES \
274 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
275 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
276 ETH_RSS_NONFRAG_IPV4_OTHER)
278 /* IBV hash source bits for IPV4. */
279 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
281 /* Valid layer type for IPV6 RSS. */
282 #define MLX5_IPV6_LAYER_TYPES \
283 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
284 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
285 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
287 /* IBV hash source bits for IPV6. */
288 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
291 /* Geneve header first 16Bit */
292 #define MLX5_GENEVE_VER_MASK 0x3
293 #define MLX5_GENEVE_VER_SHIFT 14
294 #define MLX5_GENEVE_VER_VAL(a) \
295 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
296 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
297 #define MLX5_GENEVE_OPTLEN_SHIFT 7
298 #define MLX5_GENEVE_OPTLEN_VAL(a) \
299 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
300 #define MLX5_GENEVE_OAMF_MASK 0x1
301 #define MLX5_GENEVE_OAMF_SHIFT 7
302 #define MLX5_GENEVE_OAMF_VAL(a) \
303 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
304 #define MLX5_GENEVE_CRITO_MASK 0x1
305 #define MLX5_GENEVE_CRITO_SHIFT 6
306 #define MLX5_GENEVE_CRITO_VAL(a) \
307 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
308 #define MLX5_GENEVE_RSVD_MASK 0x3F
309 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
311 * The length of the Geneve options fields, expressed in four byte multiples,
312 * not including the eight byte fixed tunnel.
314 #define MLX5_GENEVE_OPT_LEN_0 14
315 #define MLX5_GENEVE_OPT_LEN_1 63
317 enum mlx5_flow_drv_type {
320 MLX5_FLOW_TYPE_VERBS,
324 /* Matcher PRM representation */
325 struct mlx5_flow_dv_match_params {
327 /**< Size of match value. Do NOT split size and key! */
328 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
329 /**< Matcher value. This value is used as the mask or as a key. */
332 /* Matcher structure. */
333 struct mlx5_flow_dv_matcher {
334 LIST_ENTRY(mlx5_flow_dv_matcher) next;
335 /* Pointer to the next element. */
336 rte_atomic32_t refcnt; /**< Reference counter. */
337 void *matcher_object; /**< Pointer to DV matcher */
338 uint16_t crc; /**< CRC of key. */
339 uint16_t priority; /**< Priority of matcher. */
340 uint8_t egress; /**< Egress matcher. */
341 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
342 uint32_t group; /**< The matcher group. */
343 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
346 #define MLX5_ENCAP_MAX_LEN 132
348 /* Encap/decap resource structure. */
349 struct mlx5_flow_dv_encap_decap_resource {
350 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
351 /* Pointer to next element. */
352 rte_atomic32_t refcnt; /**< Reference counter. */
354 /**< Verbs encap/decap action object. */
355 uint8_t buf[MLX5_ENCAP_MAX_LEN];
357 uint8_t reformat_type;
359 uint64_t flags; /**< Flags for RDMA API. */
362 /* Tag resource structure. */
363 struct mlx5_flow_dv_tag_resource {
364 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
365 /* Pointer to next element. */
366 rte_atomic32_t refcnt; /**< Reference counter. */
368 /**< Verbs tag action object. */
369 uint32_t tag; /**< the tag value. */
373 * Number of modification commands.
374 * If extensive metadata registers are supported
375 * the maximal actions amount is 16 and 8 otherwise.
377 #define MLX5_MODIFY_NUM 16
378 #define MLX5_MODIFY_NUM_NO_MREG 8
380 /* Modify resource structure */
381 struct mlx5_flow_dv_modify_hdr_resource {
382 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
383 /* Pointer to next element. */
384 rte_atomic32_t refcnt; /**< Reference counter. */
385 struct ibv_flow_action *verbs_action;
386 /**< Verbs modify header action object. */
387 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
388 uint32_t actions_num; /**< Number of modification actions. */
389 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
390 /**< Modification actions. */
391 uint64_t flags; /**< Flags for RDMA API. */
394 /* Jump action resource structure. */
395 struct mlx5_flow_dv_jump_tbl_resource {
396 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
397 /* Pointer to next element. */
398 rte_atomic32_t refcnt; /**< Reference counter. */
399 void *action; /**< Pointer to the rdma core action. */
400 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
401 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
404 /* Port ID resource structure. */
405 struct mlx5_flow_dv_port_id_action_resource {
406 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
407 /* Pointer to next element. */
408 rte_atomic32_t refcnt; /**< Reference counter. */
410 /**< Verbs tag action object. */
411 uint32_t port_id; /**< Port ID value. */
414 /* Push VLAN action resource structure */
415 struct mlx5_flow_dv_push_vlan_action_resource {
416 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
417 /* Pointer to next element. */
418 rte_atomic32_t refcnt; /**< Reference counter. */
419 void *action; /**< Direct verbs action object. */
420 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
421 rte_be32_t vlan_tag; /**< VLAN tag value. */
424 /* Metadata register copy table entry. */
425 struct mlx5_flow_mreg_copy_resource {
427 * Hash list entry for copy table.
428 * - Key is 32/64-bit MARK action ID.
429 * - MUST be the first entry.
431 struct mlx5_hlist_entry hlist_ent;
432 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
433 /* List entry for device flows. */
434 uint32_t refcnt; /* Reference counter. */
435 uint32_t appcnt; /* Apply/Remove counter. */
436 struct rte_flow *flow; /* Built flow for copy. */
440 * Max number of actions per DV flow.
441 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
442 * In rdma-core file providers/mlx5/verbs.c
444 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
446 /* DV flows structure. */
447 struct mlx5_flow_dv {
448 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
450 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
451 struct mlx5_flow_dv_match_params value;
452 /**< Holds the value that the packet is compared to. */
453 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
454 /**< Pointer to encap/decap resource in cache. */
455 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
456 /**< Pointer to modify header resource in cache. */
457 struct ibv_flow *flow; /**< Installed flow. */
458 struct mlx5_flow_dv_jump_tbl_resource *jump;
459 /**< Pointer to the jump action resource. */
460 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
461 /**< Pointer to port ID action resource. */
462 struct mlx5_vf_vlan vf_vlan;
463 /**< Structure for VF VLAN workaround. */
464 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
465 /**< Pointer to push VLAN action resource in cache. */
466 struct mlx5_flow_dv_tag_resource *tag_resource;
467 /**< pointer to the tag action. */
468 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
469 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
472 int actions_n; /**< number of actions. */
475 /* Verbs specification header. */
476 struct ibv_spec_header {
477 enum ibv_flow_spec_type type;
481 /** Handles information leading to a drop fate. */
482 struct mlx5_flow_verbs {
483 LIST_ENTRY(mlx5_flow_verbs) next;
484 unsigned int size; /**< Size of the attribute. */
486 struct ibv_flow_attr *attr;
487 /**< Pointer to the Specification buffer. */
488 uint8_t *specs; /**< Pointer to the specifications. */
490 struct ibv_flow *flow; /**< Verbs flow pointer. */
491 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
492 struct mlx5_vf_vlan vf_vlan;
493 /**< Structure for VF VLAN workaround. */
496 struct mlx5_flow_rss {
498 uint32_t queue_num; /**< Number of entries in @p queue. */
499 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
500 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
501 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
504 /** Device flow structure. */
506 LIST_ENTRY(mlx5_flow) next;
507 struct rte_flow *flow; /**< Pointer to the main flow. */
509 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
511 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
512 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
513 uint8_t ingress; /**< 1 if the flow is ingress. */
514 uint32_t group; /**< The group index. */
515 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
517 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
518 struct mlx5_flow_dv dv;
520 struct mlx5_flow_verbs verbs;
522 uint32_t qrss_id; /**< Uniqie Q/RSS suffix subflow tag. */
523 bool external; /**< true if the flow is created external to PMD. */
526 #define MLX5_MAN_WIDTH 8
528 /* RFC2697 parameter structure. */
529 struct mlx5_flow_meter_srtcm_rfc2697_prm {
530 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
531 uint32_t cbs_exponent:5;
532 uint32_t cbs_mantissa:8;
533 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
534 uint32_t cir_exponent:5;
535 uint32_t cir_mantissa:8;
536 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
537 uint32_t ebs_exponent:5;
538 uint32_t ebs_mantissa:8;
541 /* Flow meter profile structure. */
542 struct mlx5_flow_meter_profile {
543 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
544 /**< Pointer to the next flow meter structure. */
545 uint32_t meter_profile_id; /**< Profile id. */
546 struct rte_mtr_meter_profile profile; /**< Profile detail. */
548 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
549 /**< srtcm_rfc2697 struct. */
551 uint32_t ref_cnt; /**< Use count. */
554 /* Flow structure. */
556 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
557 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
558 struct mlx5_flow_rss rss; /**< RSS context. */
559 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
560 struct mlx5_flow_mreg_copy_resource *mreg_copy;
561 /**< pointer to metadata register copy table resource. */
562 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
563 /**< Device flows that are part of the flow. */
564 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
565 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
566 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
569 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
570 const struct rte_flow_attr *attr,
571 const struct rte_flow_item items[],
572 const struct rte_flow_action actions[],
574 struct rte_flow_error *error);
575 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
576 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
577 const struct rte_flow_action actions[], struct rte_flow_error *error);
578 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
579 struct mlx5_flow *dev_flow,
580 const struct rte_flow_attr *attr,
581 const struct rte_flow_item items[],
582 const struct rte_flow_action actions[],
583 struct rte_flow_error *error);
584 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
585 struct rte_flow_error *error);
586 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
587 struct rte_flow *flow);
588 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
589 struct rte_flow *flow);
590 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
591 struct rte_flow *flow,
592 const struct rte_flow_action *actions,
594 struct rte_flow_error *error);
595 struct mlx5_flow_driver_ops {
596 mlx5_flow_validate_t validate;
597 mlx5_flow_prepare_t prepare;
598 mlx5_flow_translate_t translate;
599 mlx5_flow_apply_t apply;
600 mlx5_flow_remove_t remove;
601 mlx5_flow_destroy_t destroy;
602 mlx5_flow_query_t query;
606 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
607 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
608 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
609 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
613 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
614 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
615 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
616 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
618 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
619 bool external, uint32_t group, uint32_t *table,
620 struct rte_flow_error *error);
621 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
622 uint64_t layer_types,
623 uint64_t hash_fields);
624 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
625 uint32_t subpriority);
626 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
627 enum mlx5_feature_name feature,
629 struct rte_flow_error *error);
630 const struct rte_flow_action *mlx5_flow_find_action
631 (const struct rte_flow_action *actions,
632 enum rte_flow_action_type action);
633 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
634 const struct rte_flow_attr *attr,
635 struct rte_flow_error *error);
636 int mlx5_flow_validate_action_drop(uint64_t action_flags,
637 const struct rte_flow_attr *attr,
638 struct rte_flow_error *error);
639 int mlx5_flow_validate_action_flag(uint64_t action_flags,
640 const struct rte_flow_attr *attr,
641 struct rte_flow_error *error);
642 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
643 uint64_t action_flags,
644 const struct rte_flow_attr *attr,
645 struct rte_flow_error *error);
646 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
647 uint64_t action_flags,
648 struct rte_eth_dev *dev,
649 const struct rte_flow_attr *attr,
650 struct rte_flow_error *error);
651 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
652 uint64_t action_flags,
653 struct rte_eth_dev *dev,
654 const struct rte_flow_attr *attr,
656 struct rte_flow_error *error);
657 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
658 const struct rte_flow_attr *attributes,
659 struct rte_flow_error *error);
660 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
662 const uint8_t *nic_mask,
664 struct rte_flow_error *error);
665 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
667 struct rte_flow_error *error);
668 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
670 uint8_t target_protocol,
671 struct rte_flow_error *error);
672 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
674 const struct rte_flow_item *gre_item,
675 struct rte_flow_error *error);
676 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
680 const struct rte_flow_item_ipv4 *acc_mask,
681 struct rte_flow_error *error);
682 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
686 const struct rte_flow_item_ipv6 *acc_mask,
687 struct rte_flow_error *error);
688 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
689 const struct rte_flow_item *item,
692 struct rte_flow_error *error);
693 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
695 uint8_t target_protocol,
696 const struct rte_flow_item_tcp *flow_mask,
697 struct rte_flow_error *error);
698 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
700 uint8_t target_protocol,
701 struct rte_flow_error *error);
702 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
704 struct rte_eth_dev *dev,
705 struct rte_flow_error *error);
706 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
708 struct rte_flow_error *error);
709 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
711 struct rte_eth_dev *dev,
712 struct rte_flow_error *error);
713 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
715 uint8_t target_protocol,
716 struct rte_flow_error *error);
717 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
719 uint8_t target_protocol,
720 struct rte_flow_error *error);
721 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
723 uint8_t target_protocol,
724 struct rte_flow_error *error);
725 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
727 struct rte_eth_dev *dev,
728 struct rte_flow_error *error);
729 #endif /* RTE_PMD_MLX5_FLOW_H_ */