1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_alarm.h>
17 #include <mlx5_glue.h>
22 /* Private rte flow items. */
23 enum mlx5_rte_flow_item_type {
24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
25 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
38 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
39 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 #define MLX5_SHARED_ACTION_TYPE_OFFSET 30
45 MLX5_SHARED_ACTION_TYPE_RSS,
46 MLX5_SHARED_ACTION_TYPE_AGE,
49 /* Matches on selected register. */
50 struct mlx5_rte_flow_item_tag {
55 /* Modify selected register. */
56 struct mlx5_rte_flow_action_set_tag {
61 struct mlx5_flow_action_copy_mreg {
66 /* Matches on source queue. */
67 struct mlx5_rte_flow_item_tx_queue {
71 /* Feature name to allocate metadata register. */
72 enum mlx5_feature_name {
86 /* Default queue number. */
87 #define MLX5_RSSQ_DEFAULT_NUM 16
89 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
90 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
91 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
92 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
93 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
94 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
96 /* Pattern inner Layer bits. */
97 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
98 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
99 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
100 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
101 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
102 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
104 /* Pattern tunnel Layer bits. */
105 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
106 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
107 #define MLX5_FLOW_LAYER_GRE (1u << 14)
108 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
109 /* List of tunnel Layer bits continued below. */
111 /* General pattern items bits. */
112 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
113 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
114 #define MLX5_FLOW_ITEM_TAG (1u << 18)
115 #define MLX5_FLOW_ITEM_MARK (1u << 19)
117 /* Pattern MISC bits. */
118 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
119 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
120 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
122 /* Pattern tunnel Layer bits (continued). */
123 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
124 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
125 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
126 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
129 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
131 /* Pattern tunnel Layer bits (continued). */
132 #define MLX5_FLOW_LAYER_GTP (1u << 28)
134 /* Pattern eCPRI Layer bit. */
135 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
137 /* IPv6 Fragment Extension Header bit. */
138 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
139 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
142 #define MLX5_FLOW_LAYER_OUTER_L3 \
143 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
144 #define MLX5_FLOW_LAYER_OUTER_L4 \
145 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
146 #define MLX5_FLOW_LAYER_OUTER \
147 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
148 MLX5_FLOW_LAYER_OUTER_L4)
151 #define MLX5_FLOW_LAYER_TUNNEL \
152 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
153 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
154 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
155 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
158 #define MLX5_FLOW_LAYER_INNER_L3 \
159 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
160 #define MLX5_FLOW_LAYER_INNER_L4 \
161 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
162 #define MLX5_FLOW_LAYER_INNER \
163 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
164 MLX5_FLOW_LAYER_INNER_L4)
167 #define MLX5_FLOW_LAYER_L2 \
168 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
169 #define MLX5_FLOW_LAYER_L3_IPV4 \
170 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
171 #define MLX5_FLOW_LAYER_L3_IPV6 \
172 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
173 #define MLX5_FLOW_LAYER_L3 \
174 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
175 #define MLX5_FLOW_LAYER_L4 \
176 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
179 #define MLX5_FLOW_ACTION_DROP (1u << 0)
180 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
181 #define MLX5_FLOW_ACTION_RSS (1u << 2)
182 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
183 #define MLX5_FLOW_ACTION_MARK (1u << 4)
184 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
185 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
186 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
187 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
188 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
189 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
190 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
191 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
192 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
193 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
194 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
195 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
196 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
197 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
198 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
199 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
200 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
201 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
202 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
203 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
204 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
205 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
206 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
207 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
208 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
209 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
210 #define MLX5_FLOW_ACTION_METER (1ull << 31)
211 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
212 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
213 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
214 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
215 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
216 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
217 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
219 #define MLX5_FLOW_FATE_ACTIONS \
220 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
221 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
222 MLX5_FLOW_ACTION_DEFAULT_MISS)
224 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
225 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
226 MLX5_FLOW_ACTION_JUMP)
229 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
230 MLX5_FLOW_ACTION_SET_IPV4_DST | \
231 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
232 MLX5_FLOW_ACTION_SET_IPV6_DST | \
233 MLX5_FLOW_ACTION_SET_TP_SRC | \
234 MLX5_FLOW_ACTION_SET_TP_DST | \
235 MLX5_FLOW_ACTION_SET_TTL | \
236 MLX5_FLOW_ACTION_DEC_TTL | \
237 MLX5_FLOW_ACTION_SET_MAC_SRC | \
238 MLX5_FLOW_ACTION_SET_MAC_DST | \
239 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
240 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
241 MLX5_FLOW_ACTION_INC_TCP_ACK | \
242 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
243 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
244 MLX5_FLOW_ACTION_SET_TAG | \
245 MLX5_FLOW_ACTION_MARK_EXT | \
246 MLX5_FLOW_ACTION_SET_META | \
247 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
248 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
250 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
251 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
253 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
256 #define IPPROTO_MPLS 137
259 /* UDP port number for MPLS */
260 #define MLX5_UDP_PORT_MPLS 6635
262 /* UDP port numbers for VxLAN. */
263 #define MLX5_UDP_PORT_VXLAN 4789
264 #define MLX5_UDP_PORT_VXLAN_GPE 4790
266 /* UDP port numbers for GENEVE. */
267 #define MLX5_UDP_PORT_GENEVE 6081
269 /* Priority reserved for default flows. */
270 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
273 * Number of sub priorities.
274 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
275 * matching on the NIC (firmware dependent) L4 most have the higher priority
276 * followed by L3 and ending with L2.
278 #define MLX5_PRIORITY_MAP_L2 2
279 #define MLX5_PRIORITY_MAP_L3 1
280 #define MLX5_PRIORITY_MAP_L4 0
281 #define MLX5_PRIORITY_MAP_MAX 3
283 /* Valid layer type for IPV4 RSS. */
284 #define MLX5_IPV4_LAYER_TYPES \
285 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
286 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
287 ETH_RSS_NONFRAG_IPV4_OTHER)
289 /* IBV hash source bits for IPV4. */
290 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
292 /* Valid layer type for IPV6 RSS. */
293 #define MLX5_IPV6_LAYER_TYPES \
294 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
295 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
296 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
298 /* IBV hash source bits for IPV6. */
299 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
301 /* IBV hash bits for L3 SRC. */
302 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
304 /* IBV hash bits for L3 DST. */
305 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
307 /* IBV hash bits for TCP. */
308 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
309 IBV_RX_HASH_DST_PORT_TCP)
311 /* IBV hash bits for UDP. */
312 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
313 IBV_RX_HASH_DST_PORT_UDP)
315 /* IBV hash bits for L4 SRC. */
316 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
317 IBV_RX_HASH_SRC_PORT_UDP)
319 /* IBV hash bits for L4 DST. */
320 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
321 IBV_RX_HASH_DST_PORT_UDP)
323 /* Geneve header first 16Bit */
324 #define MLX5_GENEVE_VER_MASK 0x3
325 #define MLX5_GENEVE_VER_SHIFT 14
326 #define MLX5_GENEVE_VER_VAL(a) \
327 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
328 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
329 #define MLX5_GENEVE_OPTLEN_SHIFT 7
330 #define MLX5_GENEVE_OPTLEN_VAL(a) \
331 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
332 #define MLX5_GENEVE_OAMF_MASK 0x1
333 #define MLX5_GENEVE_OAMF_SHIFT 7
334 #define MLX5_GENEVE_OAMF_VAL(a) \
335 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
336 #define MLX5_GENEVE_CRITO_MASK 0x1
337 #define MLX5_GENEVE_CRITO_SHIFT 6
338 #define MLX5_GENEVE_CRITO_VAL(a) \
339 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
340 #define MLX5_GENEVE_RSVD_MASK 0x3F
341 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
343 * The length of the Geneve options fields, expressed in four byte multiples,
344 * not including the eight byte fixed tunnel.
346 #define MLX5_GENEVE_OPT_LEN_0 14
347 #define MLX5_GENEVE_OPT_LEN_1 63
349 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
350 sizeof(struct rte_ipv4_hdr))
352 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
353 #define MLX5_IPV4_FRAG_OFFSET_MASK \
354 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
356 /* Specific item's fields can accept a range of values (using spec and last). */
357 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
358 #define MLX5_ITEM_RANGE_ACCEPTED true
360 /* Software header modify action numbers of a flow. */
361 #define MLX5_ACT_NUM_MDF_IPV4 1
362 #define MLX5_ACT_NUM_MDF_IPV6 4
363 #define MLX5_ACT_NUM_MDF_MAC 2
364 #define MLX5_ACT_NUM_MDF_VID 1
365 #define MLX5_ACT_NUM_MDF_PORT 2
366 #define MLX5_ACT_NUM_MDF_TTL 1
367 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
368 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
369 #define MLX5_ACT_NUM_MDF_TCPACK 1
370 #define MLX5_ACT_NUM_SET_REG 1
371 #define MLX5_ACT_NUM_SET_TAG 1
372 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
373 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
374 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
375 #define MLX5_ACT_NUM_SET_DSCP 1
377 enum mlx5_flow_drv_type {
380 MLX5_FLOW_TYPE_VERBS,
384 /* Fate action type. */
385 enum mlx5_flow_fate_type {
386 MLX5_FLOW_FATE_NONE, /* Egress flow. */
387 MLX5_FLOW_FATE_QUEUE,
389 MLX5_FLOW_FATE_PORT_ID,
391 MLX5_FLOW_FATE_DEFAULT_MISS,
392 MLX5_FLOW_FATE_SHARED_RSS,
396 /* Matcher PRM representation */
397 struct mlx5_flow_dv_match_params {
399 /**< Size of match value. Do NOT split size and key! */
400 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
401 /**< Matcher value. This value is used as the mask or as a key. */
404 /* Matcher structure. */
405 struct mlx5_flow_dv_matcher {
406 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
407 struct mlx5_flow_tbl_resource *tbl;
408 /**< Pointer to the table(group) the matcher associated with. */
409 void *matcher_object; /**< Pointer to DV matcher */
410 uint16_t crc; /**< CRC of key. */
411 uint16_t priority; /**< Priority of matcher. */
412 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
415 #define MLX5_ENCAP_MAX_LEN 132
417 /* Encap/decap resource structure. */
418 struct mlx5_flow_dv_encap_decap_resource {
419 struct mlx5_hlist_entry entry;
420 /* Pointer to next element. */
421 uint32_t refcnt; /**< Reference counter. */
423 /**< Encap/decap action object. */
424 uint8_t buf[MLX5_ENCAP_MAX_LEN];
426 uint8_t reformat_type;
428 uint64_t flags; /**< Flags for RDMA API. */
429 uint32_t idx; /**< Index for the index memory pool. */
432 /* Tag resource structure. */
433 struct mlx5_flow_dv_tag_resource {
434 struct mlx5_hlist_entry entry;
435 /**< hash list entry for tag resource, tag value as the key. */
437 /**< Tag action object. */
438 uint32_t refcnt; /**< Reference counter. */
439 uint32_t idx; /**< Index for the index memory pool. */
440 uint32_t tag_id; /**< Tag ID. */
444 * Number of modification commands.
445 * The maximal actions amount in FW is some constant, and it is 16 in the
446 * latest releases. In some old releases, it will be limited to 8.
447 * Since there is no interface to query the capacity, the maximal value should
448 * be used to allow PMD to create the flow. The validation will be done in the
449 * lower driver layer or FW. A failure will be returned if exceeds the maximal
450 * supported actions number on the root table.
451 * On non-root tables, there is no limitation, but 32 is enough right now.
453 #define MLX5_MAX_MODIFY_NUM 32
454 #define MLX5_ROOT_TBL_MODIFY_NUM 16
456 /* Modify resource structure */
457 struct mlx5_flow_dv_modify_hdr_resource {
458 struct mlx5_hlist_entry entry;
459 void *action; /**< Modify header action object. */
460 /* Key area for hash list matching: */
461 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
462 uint32_t actions_num; /**< Number of modification actions. */
463 uint64_t flags; /**< Flags for RDMA API. */
464 struct mlx5_modification_cmd actions[];
465 /**< Modification actions. */
468 /* Modify resource key of the hash organization. */
469 union mlx5_flow_modify_hdr_key {
471 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
472 uint32_t actions_num:5; /**< Number of modification actions. */
473 uint32_t group:19; /**< Flow group id. */
474 uint32_t cksum; /**< Actions check sum. */
476 uint64_t v64; /**< full 64bits value of key */
479 /* Jump action resource structure. */
480 struct mlx5_flow_dv_jump_tbl_resource {
481 void *action; /**< Pointer to the rdma core action. */
484 /* Port ID resource structure. */
485 struct mlx5_flow_dv_port_id_action_resource {
486 struct mlx5_cache_entry entry;
487 void *action; /**< Action object. */
488 uint32_t port_id; /**< Port ID value. */
489 uint32_t idx; /**< Indexed pool memory index. */
492 /* Push VLAN action resource structure */
493 struct mlx5_flow_dv_push_vlan_action_resource {
494 struct mlx5_cache_entry entry; /* Cache entry. */
495 void *action; /**< Action object. */
496 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
497 rte_be32_t vlan_tag; /**< VLAN tag value. */
498 uint32_t idx; /**< Indexed pool memory index. */
501 /* Metadata register copy table entry. */
502 struct mlx5_flow_mreg_copy_resource {
504 * Hash list entry for copy table.
505 * - Key is 32/64-bit MARK action ID.
506 * - MUST be the first entry.
508 struct mlx5_hlist_entry hlist_ent;
509 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
510 /* List entry for device flows. */
512 uint32_t rix_flow; /* Built flow for copy. */
516 /* Table tunnel parameter. */
517 struct mlx5_flow_tbl_tunnel_prm {
518 const struct mlx5_flow_tunnel *tunnel;
523 /* Table data structure of the hash organization. */
524 struct mlx5_flow_tbl_data_entry {
525 struct mlx5_hlist_entry entry;
526 /**< hash list entry, 64-bits key inside. */
527 struct mlx5_flow_tbl_resource tbl;
528 /**< flow table resource. */
529 struct mlx5_cache_list matchers;
530 /**< matchers' header associated with the flow table. */
531 struct mlx5_flow_dv_jump_tbl_resource jump;
532 /**< jump resource, at most one for each table created. */
533 uint32_t idx; /**< index for the indexed mempool. */
534 /**< tunnel offload */
535 const struct mlx5_flow_tunnel *tunnel;
538 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
539 uint32_t is_egress:1; /**< Egress table. */
540 uint32_t is_transfer:1; /**< Transfer table. */
541 uint32_t dummy:1; /**< DR table. */
542 uint32_t reserve:27; /**< Reserved to future using. */
543 uint32_t table_id; /**< Table ID. */
546 /* Sub rdma-core actions list. */
547 struct mlx5_flow_sub_actions_list {
548 uint32_t actions_num; /**< Number of sample actions. */
549 uint64_t action_flags;
550 void *dr_queue_action;
553 void *dr_port_id_action;
554 void *dr_encap_action;
557 /* Sample sub-actions resource list. */
558 struct mlx5_flow_sub_actions_idx {
559 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
560 uint32_t rix_tag; /**< Index to the tag action. */
562 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
563 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
566 /* Sample action resource structure. */
567 struct mlx5_flow_dv_sample_resource {
568 struct mlx5_cache_entry entry; /**< Cache entry. */
570 void *verbs_action; /**< Verbs sample action object. */
571 void **sub_actions; /**< Sample sub-action array. */
573 struct rte_eth_dev *dev; /**< Device registers the action. */
574 uint32_t idx; /** Sample object index. */
575 uint8_t ft_type; /** Flow Table Type */
576 uint32_t ft_id; /** Flow Table Level */
577 uint32_t ratio; /** Sample Ratio */
578 uint64_t set_action; /** Restore reg_c0 value */
579 void *normal_path_tbl; /** Flow Table pointer */
580 void *default_miss; /** default_miss dr_action. */
581 struct mlx5_flow_sub_actions_idx sample_idx;
582 /**< Action index resources. */
583 struct mlx5_flow_sub_actions_list sample_act;
584 /**< Action resources. */
587 #define MLX5_MAX_DEST_NUM 2
589 /* Destination array action resource structure. */
590 struct mlx5_flow_dv_dest_array_resource {
591 struct mlx5_cache_entry entry; /**< Cache entry. */
592 uint32_t idx; /** Destination array action object index. */
593 uint8_t ft_type; /** Flow Table Type */
594 uint8_t num_of_dest; /**< Number of destination actions. */
595 struct rte_eth_dev *dev; /**< Device registers the action. */
596 void *action; /**< Pointer to the rdma core action. */
597 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
598 /**< Action index resources. */
599 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
600 /**< Action resources. */
603 /* Verbs specification header. */
604 struct ibv_spec_header {
605 enum ibv_flow_spec_type type;
609 /* PMD flow priority for tunnel */
610 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
611 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
614 /** Device flow handle structure for DV mode only. */
615 struct mlx5_flow_handle_dv {
617 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
618 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
619 /**< Pointer to modify header resource in cache. */
620 uint32_t rix_encap_decap;
621 /**< Index to encap/decap resource in cache. */
622 uint32_t rix_push_vlan;
623 /**< Index to push VLAN action resource in cache. */
625 /**< Index to the tag action. */
627 /**< Index to sample action resource in cache. */
628 uint32_t rix_dest_array;
629 /**< Index to destination array resource in cache. */
632 /** Device flow handle structure: used both for creating & destroying. */
633 struct mlx5_flow_handle {
634 SILIST_ENTRY(uint32_t)next;
635 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
636 /**< Index to next device flow handle. */
638 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
639 void *drv_flow; /**< pointer to driver flow object. */
640 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
641 uint32_t mark:1; /**< Metadate rxq mark flag. */
642 uint32_t fate_action:3; /**< Fate action type. */
644 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
645 uint32_t rix_jump; /**< Index to the jump action resource. */
646 uint32_t rix_port_id_action;
647 /**< Index to port ID action resource. */
649 /**< Generic value indicates the fate action. */
650 uint32_t rix_default_fate;
651 /**< Indicates default miss fate action. */
653 /**< Indicates shared RSS fate action. */
655 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
656 struct mlx5_flow_handle_dv dvh;
661 * Size for Verbs device flow handle structure only. Do not use the DV only
662 * structure in Verbs. No DV flows attributes will be accessed.
663 * Macro offsetof() could also be used here.
665 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
666 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
667 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
669 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
673 * Max number of actions per DV flow.
674 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
675 * in rdma-core file providers/mlx5/verbs.c.
677 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
679 /** Device flow structure only for DV flow creation. */
680 struct mlx5_flow_dv_workspace {
681 uint32_t group; /**< The group index. */
682 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
683 int actions_n; /**< number of actions. */
684 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
685 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
686 /**< Pointer to encap/decap resource in cache. */
687 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
688 /**< Pointer to push VLAN action resource in cache. */
689 struct mlx5_flow_dv_tag_resource *tag_resource;
690 /**< pointer to the tag action. */
691 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
692 /**< Pointer to port ID action resource. */
693 struct mlx5_flow_dv_jump_tbl_resource *jump;
694 /**< Pointer to the jump action resource. */
695 struct mlx5_flow_dv_match_params value;
696 /**< Holds the value that the packet is compared to. */
697 struct mlx5_flow_dv_sample_resource *sample_res;
698 /**< Pointer to the sample action resource. */
699 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
700 /**< Pointer to the destination array resource. */
704 * Maximal Verbs flow specifications & actions size.
705 * Some elements are mutually exclusive, but enough space should be allocated.
706 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
707 * 2. One tunnel header (exception: GRE + MPLS),
708 * SPEC length: GRE == tunnel.
709 * Actions: 1. 1 Mark OR Flag.
710 * 2. 1 Drop (if any).
711 * 3. No limitation for counters, but it makes no sense to support too
712 * many counters in a single device flow.
714 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
715 #define MLX5_VERBS_MAX_SPEC_SIZE \
717 (2 * (sizeof(struct ibv_flow_spec_eth) + \
718 sizeof(struct ibv_flow_spec_ipv6) + \
719 sizeof(struct ibv_flow_spec_tcp_udp)) + \
720 sizeof(struct ibv_flow_spec_gre) + \
721 sizeof(struct ibv_flow_spec_mpls)) \
724 #define MLX5_VERBS_MAX_SPEC_SIZE \
726 (2 * (sizeof(struct ibv_flow_spec_eth) + \
727 sizeof(struct ibv_flow_spec_ipv6) + \
728 sizeof(struct ibv_flow_spec_tcp_udp)) + \
729 sizeof(struct ibv_flow_spec_tunnel)) \
733 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
734 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
735 #define MLX5_VERBS_MAX_ACT_SIZE \
737 sizeof(struct ibv_flow_spec_action_tag) + \
738 sizeof(struct ibv_flow_spec_action_drop) + \
739 sizeof(struct ibv_flow_spec_counter_action) * 4 \
742 #define MLX5_VERBS_MAX_ACT_SIZE \
744 sizeof(struct ibv_flow_spec_action_tag) + \
745 sizeof(struct ibv_flow_spec_action_drop) \
749 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
750 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
752 /** Device flow structure only for Verbs flow creation. */
753 struct mlx5_flow_verbs_workspace {
754 unsigned int size; /**< Size of the attribute. */
755 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
756 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
757 /**< Specifications & actions buffer of verbs flow. */
760 /** Maximal number of device sub-flows supported. */
761 #define MLX5_NUM_MAX_DEV_FLOWS 32
763 /** Device flow structure. */
766 struct rte_flow *flow; /**< Pointer to the main flow. */
767 uint32_t flow_idx; /**< The memory pool index to the main flow. */
768 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
770 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
771 bool external; /**< true if the flow is created external to PMD. */
772 uint8_t ingress:1; /**< 1 if the flow is ingress. */
773 uint8_t skip_scale:1;
774 /**< 1 if skip the scale the table with factor. */
776 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
777 struct mlx5_flow_dv_workspace dv;
779 struct mlx5_flow_verbs_workspace verbs;
781 struct mlx5_flow_handle *handle;
782 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
783 const struct mlx5_flow_tunnel *tunnel;
786 /* Flow meter state. */
787 #define MLX5_FLOW_METER_DISABLE 0
788 #define MLX5_FLOW_METER_ENABLE 1
790 #define MLX5_MAN_WIDTH 8
791 /* Modify this value if enum rte_mtr_color changes. */
792 #define RTE_MTR_DROPPED RTE_COLORS
794 /* Meter policer statistics */
795 struct mlx5_flow_policer_stats {
796 uint32_t cnt[RTE_COLORS + 1];
797 /**< Color counter, extra for drop. */
799 /**< Statistics mask for the colors. */
802 /* Meter table structure. */
803 struct mlx5_meter_domain_info {
804 struct mlx5_flow_tbl_resource *tbl;
806 struct mlx5_flow_tbl_resource *sfx_tbl;
807 /**< Meter suffix table. */
809 /**< Meter color not match default criteria. */
811 /**< Meter color match criteria. */
813 /**< Meter match action. */
814 void *policer_rules[RTE_MTR_DROPPED + 1];
815 /**< Meter policer for the match. */
818 /* Meter table set for TX RX FDB. */
819 struct mlx5_meter_domains_infos {
821 /**< Table user count. */
822 struct mlx5_meter_domain_info egress;
823 /**< TX meter table. */
824 struct mlx5_meter_domain_info ingress;
825 /**< RX meter table. */
826 struct mlx5_meter_domain_info transfer;
827 /**< FDB meter table. */
829 /**< Drop action as not matched. */
830 void *count_actns[RTE_MTR_DROPPED + 1];
831 /**< Counters for match and unmatched statistics. */
832 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
833 /**< Flow meter parameter. */
835 /**< Flow meter parameter size. */
837 /**< Flow meter action. */
840 /* Meter parameter structure. */
841 struct mlx5_flow_meter {
842 TAILQ_ENTRY(mlx5_flow_meter) next;
843 /**< Pointer to the next flow meter structure. */
844 uint32_t idx; /* Index to meter object. */
847 struct mlx5_flow_meter_profile *profile;
848 /**< Meter profile parameters. */
850 rte_spinlock_t sl; /**< Meter action spinlock. */
852 /** Policer actions (per meter output color). */
853 enum rte_mtr_policer_action action[RTE_COLORS];
855 /** Set of stats counters to be enabled.
856 * @see enum rte_mtr_stats_type
860 /**< Rule applies to ingress traffic. */
863 /**< Rule applies to egress traffic. */
866 * Instead of simply matching the properties of traffic as it would
867 * appear on a given DPDK port ID, enabling this attribute transfers
868 * a flow rule to the lowest possible level of any device endpoints
869 * found in the pattern.
871 * When supported, this effectively enables an application to
872 * re-route traffic not necessarily intended for it (e.g. coming
873 * from or addressed to different physical ports, VFs or
874 * applications) at the device level.
876 * It complements the behavior of some pattern items such as
877 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
879 * When transferring flow rules, ingress and egress attributes keep
880 * their original meaning, as if processing traffic emitted or
881 * received by the application.
884 struct mlx5_meter_domains_infos *mfts;
885 /**< Flow table created for this meter. */
886 struct mlx5_flow_policer_stats policer_stats;
887 /**< Meter policer statistics. */
890 uint32_t active_state:1;
893 /**< Meter shared or not. */
896 /* RFC2697 parameter structure. */
897 struct mlx5_flow_meter_srtcm_rfc2697_prm {
898 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
899 uint32_t cbs_exponent:5;
900 uint32_t cbs_mantissa:8;
901 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
902 uint32_t cir_exponent:5;
903 uint32_t cir_mantissa:8;
904 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
905 uint32_t ebs_exponent:5;
906 uint32_t ebs_mantissa:8;
909 /* Flow meter profile structure. */
910 struct mlx5_flow_meter_profile {
911 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
912 /**< Pointer to the next flow meter structure. */
913 uint32_t meter_profile_id; /**< Profile id. */
914 struct rte_mtr_meter_profile profile; /**< Profile detail. */
916 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
917 /**< srtcm_rfc2697 struct. */
919 uint32_t ref_cnt; /**< Use count. */
922 #define MLX5_MAX_TUNNELS 256
923 #define MLX5_TNL_MISS_RULE_PRIORITY 3
924 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
927 * When tunnel offload is active, all JUMP group ids are converted
928 * using the same method. That conversion is applied both to tunnel and
929 * regular rule types.
930 * Group ids used in tunnel rules are relative to it's tunnel (!).
931 * Application can create number of steer rules, using the same
932 * tunnel, with different group id in each rule.
933 * Each tunnel stores its groups internally in PMD tunnel object.
934 * Groups used in regular rules do not belong to any tunnel and are stored
938 struct mlx5_flow_tunnel {
939 LIST_ENTRY(mlx5_flow_tunnel) chain;
940 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
941 uint32_t tunnel_id; /** unique tunnel ID */
943 struct rte_flow_action action;
944 struct rte_flow_item item;
945 struct mlx5_hlist *groups; /** tunnel groups */
948 /** PMD tunnel related context */
949 struct mlx5_flow_tunnel_hub {
951 * Access to the list MUST be MT protected
953 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
954 /* protect access to the tunnels list */
956 struct mlx5_hlist *groups; /** non tunnel groups */
959 /* convert jump group to flow table ID in tunnel rules */
960 struct tunnel_tbl_entry {
961 struct mlx5_hlist_entry hash;
967 static inline uint32_t
968 tunnel_id_to_flow_tbl(uint32_t id)
970 return id | (1u << 16);
973 static inline uint32_t
974 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
976 return flow_tbl & ~(1u << 16);
979 union tunnel_tbl_key {
987 static inline struct mlx5_flow_tunnel_hub *
988 mlx5_tunnel_hub(struct rte_eth_dev *dev)
990 struct mlx5_priv *priv = dev->data->dev_private;
991 return priv->sh->tunnel_hub;
995 is_tunnel_offload_active(struct rte_eth_dev *dev)
997 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
998 struct mlx5_priv *priv = dev->data->dev_private;
999 return !!priv->config.dv_miss_info;
1007 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
1008 __rte_unused const struct rte_flow_attr *attr,
1009 __rte_unused const struct rte_flow_item items[],
1010 __rte_unused const struct rte_flow_action actions[])
1012 return (items[0].type == (typeof(items[0].type))
1013 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1017 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1018 __rte_unused const struct rte_flow_attr *attr,
1019 __rte_unused const struct rte_flow_item items[],
1020 __rte_unused const struct rte_flow_action actions[])
1022 return (actions[0].type == (typeof(actions[0].type))
1023 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1026 static inline const struct mlx5_flow_tunnel *
1027 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1029 return actions[0].conf;
1032 static inline const struct mlx5_flow_tunnel *
1033 flow_items_to_tunnel(const struct rte_flow_item items[])
1035 return items[0].spec;
1038 /* Flow structure. */
1040 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1041 uint32_t dev_handles;
1042 /**< Device flow handles that are part of the flow. */
1043 uint32_t drv_type:2; /**< Driver type. */
1045 uint32_t meter:16; /**< Holds flow meter id. */
1046 uint32_t rix_mreg_copy;
1047 /**< Index to metadata register copy table resource. */
1048 uint32_t counter; /**< Holds flow counter. */
1049 uint32_t tunnel_id; /**< Tunnel id */
1050 uint32_t age; /**< Holds ASO age bit index. */
1054 * Define list of valid combinations of RX Hash fields
1055 * (see enum ibv_rx_hash_fields).
1057 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1058 #define MLX5_RSS_HASH_IPV4_TCP \
1059 (MLX5_RSS_HASH_IPV4 | \
1060 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1061 #define MLX5_RSS_HASH_IPV4_UDP \
1062 (MLX5_RSS_HASH_IPV4 | \
1063 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1064 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1065 #define MLX5_RSS_HASH_IPV6_TCP \
1066 (MLX5_RSS_HASH_IPV6 | \
1067 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1068 #define MLX5_RSS_HASH_IPV6_UDP \
1069 (MLX5_RSS_HASH_IPV6 | \
1070 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1071 #define MLX5_RSS_HASH_NONE 0ULL
1073 /* array of valid combinations of RX Hash fields for RSS */
1074 static const uint64_t mlx5_rss_hash_fields[] = {
1076 MLX5_RSS_HASH_IPV4_TCP,
1077 MLX5_RSS_HASH_IPV4_UDP,
1079 MLX5_RSS_HASH_IPV6_TCP,
1080 MLX5_RSS_HASH_IPV6_UDP,
1084 /* Shared RSS action structure */
1085 struct mlx5_shared_action_rss {
1086 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1087 uint32_t refcnt; /**< Atomically accessed refcnt. */
1088 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1089 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1090 struct mlx5_ind_table_obj *ind_tbl;
1091 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1092 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1093 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1094 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
1095 /**< Hash RX queue indexes for tunneled RSS */
1096 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1099 struct rte_flow_shared_action {
1103 /* Thread specific flow workspace intermediate data. */
1104 struct mlx5_flow_workspace {
1105 /* If creating another flow in same thread, push new as stack. */
1106 struct mlx5_flow_workspace *prev;
1107 struct mlx5_flow_workspace *next;
1108 uint32_t inuse; /* can't create new flow with current. */
1109 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1110 struct mlx5_flow_rss_desc rss_desc;
1111 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1112 uint32_t flow_idx; /* Intermediate device flow index. */
1115 struct mlx5_flow_split_info {
1117 /**< True if flow is created by request external to PMD. */
1118 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1119 uint32_t flow_idx; /**< This memory pool index to the flow. */
1120 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1121 uint64_t prefix_layers; /**< Prefix subflow layers. */
1124 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1125 const struct rte_flow_attr *attr,
1126 const struct rte_flow_item items[],
1127 const struct rte_flow_action actions[],
1130 struct rte_flow_error *error);
1131 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1132 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1133 const struct rte_flow_item items[],
1134 const struct rte_flow_action actions[], struct rte_flow_error *error);
1135 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1136 struct mlx5_flow *dev_flow,
1137 const struct rte_flow_attr *attr,
1138 const struct rte_flow_item items[],
1139 const struct rte_flow_action actions[],
1140 struct rte_flow_error *error);
1141 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1142 struct rte_flow_error *error);
1143 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1144 struct rte_flow *flow);
1145 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1146 struct rte_flow *flow);
1147 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1148 struct rte_flow *flow,
1149 const struct rte_flow_action *actions,
1151 struct rte_flow_error *error);
1152 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1153 (struct rte_eth_dev *dev,
1154 const struct mlx5_flow_meter *fm);
1155 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1156 struct mlx5_meter_domains_infos *tbls);
1157 typedef int (*mlx5_flow_create_policer_rules_t)
1158 (struct rte_eth_dev *dev,
1159 struct mlx5_flow_meter *fm,
1160 const struct rte_flow_attr *attr);
1161 typedef int (*mlx5_flow_destroy_policer_rules_t)
1162 (struct rte_eth_dev *dev,
1163 const struct mlx5_flow_meter *fm,
1164 const struct rte_flow_attr *attr);
1165 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1166 (struct rte_eth_dev *dev);
1167 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1169 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1171 bool clear, uint64_t *pkts,
1173 typedef int (*mlx5_flow_get_aged_flows_t)
1174 (struct rte_eth_dev *dev,
1176 uint32_t nb_contexts,
1177 struct rte_flow_error *error);
1178 typedef int (*mlx5_flow_action_validate_t)
1179 (struct rte_eth_dev *dev,
1180 const struct rte_flow_shared_action_conf *conf,
1181 const struct rte_flow_action *action,
1182 struct rte_flow_error *error);
1183 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1184 (struct rte_eth_dev *dev,
1185 const struct rte_flow_shared_action_conf *conf,
1186 const struct rte_flow_action *action,
1187 struct rte_flow_error *error);
1188 typedef int (*mlx5_flow_action_destroy_t)
1189 (struct rte_eth_dev *dev,
1190 struct rte_flow_shared_action *action,
1191 struct rte_flow_error *error);
1192 typedef int (*mlx5_flow_action_update_t)
1193 (struct rte_eth_dev *dev,
1194 struct rte_flow_shared_action *action,
1195 const void *action_conf,
1196 struct rte_flow_error *error);
1197 typedef int (*mlx5_flow_action_query_t)
1198 (struct rte_eth_dev *dev,
1199 const struct rte_flow_shared_action *action,
1201 struct rte_flow_error *error);
1202 typedef int (*mlx5_flow_sync_domain_t)
1203 (struct rte_eth_dev *dev,
1207 struct mlx5_flow_driver_ops {
1208 mlx5_flow_validate_t validate;
1209 mlx5_flow_prepare_t prepare;
1210 mlx5_flow_translate_t translate;
1211 mlx5_flow_apply_t apply;
1212 mlx5_flow_remove_t remove;
1213 mlx5_flow_destroy_t destroy;
1214 mlx5_flow_query_t query;
1215 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1216 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1217 mlx5_flow_create_policer_rules_t create_policer_rules;
1218 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1219 mlx5_flow_counter_alloc_t counter_alloc;
1220 mlx5_flow_counter_free_t counter_free;
1221 mlx5_flow_counter_query_t counter_query;
1222 mlx5_flow_get_aged_flows_t get_aged_flows;
1223 mlx5_flow_action_validate_t action_validate;
1224 mlx5_flow_action_create_t action_create;
1225 mlx5_flow_action_destroy_t action_destroy;
1226 mlx5_flow_action_update_t action_update;
1227 mlx5_flow_action_query_t action_query;
1228 mlx5_flow_sync_domain_t sync_domain;
1233 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1235 struct flow_grp_info {
1236 uint64_t external:1;
1237 uint64_t transfer:1;
1238 uint64_t fdb_def_rule:1;
1239 /* force standard group translation */
1240 uint64_t std_tbl_fix:1;
1241 uint64_t skip_scale:1;
1245 tunnel_use_standard_attr_group_translate
1246 (struct rte_eth_dev *dev,
1247 const struct mlx5_flow_tunnel *tunnel,
1248 const struct rte_flow_attr *attr,
1249 const struct rte_flow_item items[],
1250 const struct rte_flow_action actions[])
1254 if (!is_tunnel_offload_active(dev))
1255 /* no tunnel offload API */
1259 * OvS will use jump to group 0 in tunnel steer rule.
1260 * If tunnel steer rule starts from group 0 (attr.group == 0)
1261 * that 0 group must be translated with standard method.
1262 * attr.group == 0 in tunnel match rule translated with tunnel
1265 verdict = !attr->group &&
1266 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1269 * non-tunnel group translation uses standard method for
1270 * root group only: attr.group == 0
1272 verdict = !attr->group;
1278 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1279 const struct mlx5_flow_tunnel *tunnel,
1280 uint32_t group, uint32_t *table,
1281 const struct flow_grp_info *flags,
1282 struct rte_flow_error *error);
1283 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1284 int tunnel, uint64_t layer_types,
1285 uint64_t hash_fields);
1286 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1287 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1288 uint32_t subpriority);
1289 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1290 enum mlx5_feature_name feature,
1292 struct rte_flow_error *error);
1293 const struct rte_flow_action *mlx5_flow_find_action
1294 (const struct rte_flow_action *actions,
1295 enum rte_flow_action_type action);
1296 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1297 const struct rte_flow_action *action,
1298 struct rte_flow_error *error);
1299 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1300 const struct rte_flow_attr *attr,
1301 struct rte_flow_error *error);
1302 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1303 const struct rte_flow_attr *attr,
1304 struct rte_flow_error *error);
1305 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1306 const struct rte_flow_attr *attr,
1307 struct rte_flow_error *error);
1308 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1309 uint64_t action_flags,
1310 const struct rte_flow_attr *attr,
1311 struct rte_flow_error *error);
1312 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1313 uint64_t action_flags,
1314 struct rte_eth_dev *dev,
1315 const struct rte_flow_attr *attr,
1316 struct rte_flow_error *error);
1317 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1318 uint64_t action_flags,
1319 struct rte_eth_dev *dev,
1320 const struct rte_flow_attr *attr,
1321 uint64_t item_flags,
1322 struct rte_flow_error *error);
1323 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1324 const struct rte_flow_attr *attr,
1325 struct rte_flow_error *error);
1326 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1327 const struct rte_flow_attr *attributes,
1328 struct rte_flow_error *error);
1329 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1330 const uint8_t *mask,
1331 const uint8_t *nic_mask,
1333 bool range_accepted,
1334 struct rte_flow_error *error);
1335 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1336 uint64_t item_flags, bool ext_vlan_sup,
1337 struct rte_flow_error *error);
1338 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1339 uint64_t item_flags,
1340 uint8_t target_protocol,
1341 struct rte_flow_error *error);
1342 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1343 uint64_t item_flags,
1344 const struct rte_flow_item *gre_item,
1345 struct rte_flow_error *error);
1346 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1347 uint64_t item_flags,
1349 uint16_t ether_type,
1350 const struct rte_flow_item_ipv4 *acc_mask,
1351 bool range_accepted,
1352 struct rte_flow_error *error);
1353 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1354 uint64_t item_flags,
1356 uint16_t ether_type,
1357 const struct rte_flow_item_ipv6 *acc_mask,
1358 struct rte_flow_error *error);
1359 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1360 const struct rte_flow_item *item,
1361 uint64_t item_flags,
1362 uint64_t prev_layer,
1363 struct rte_flow_error *error);
1364 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1365 uint64_t item_flags,
1366 uint8_t target_protocol,
1367 const struct rte_flow_item_tcp *flow_mask,
1368 struct rte_flow_error *error);
1369 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1370 uint64_t item_flags,
1371 uint8_t target_protocol,
1372 struct rte_flow_error *error);
1373 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1374 uint64_t item_flags,
1375 struct rte_eth_dev *dev,
1376 struct rte_flow_error *error);
1377 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1378 uint64_t item_flags,
1379 struct rte_flow_error *error);
1380 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1381 uint64_t item_flags,
1382 struct rte_eth_dev *dev,
1383 struct rte_flow_error *error);
1384 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1385 uint64_t item_flags,
1386 uint8_t target_protocol,
1387 struct rte_flow_error *error);
1388 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1389 uint64_t item_flags,
1390 uint8_t target_protocol,
1391 struct rte_flow_error *error);
1392 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1393 uint64_t item_flags,
1394 uint8_t target_protocol,
1395 struct rte_flow_error *error);
1396 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1397 uint64_t item_flags,
1398 struct rte_eth_dev *dev,
1399 struct rte_flow_error *error);
1400 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1401 uint64_t item_flags,
1403 uint16_t ether_type,
1404 const struct rte_flow_item_ecpri *acc_mask,
1405 struct rte_flow_error *error);
1406 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1407 (struct rte_eth_dev *dev,
1408 const struct mlx5_flow_meter *fm);
1409 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1410 struct mlx5_meter_domains_infos *tbl);
1411 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1412 struct mlx5_flow_meter *fm,
1413 const struct rte_flow_attr *attr);
1414 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1415 struct mlx5_flow_meter *fm,
1416 const struct rte_flow_attr *attr);
1417 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1418 struct rte_mtr_error *error);
1419 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1420 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1421 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1422 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1424 /* Hash list callbacks for flow tables: */
1425 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1426 uint64_t key, void *entry_ctx);
1427 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1428 struct mlx5_hlist_entry *entry, uint64_t key,
1430 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1431 struct mlx5_hlist_entry *entry);
1432 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1433 uint32_t table_id, uint8_t egress, uint8_t transfer,
1434 bool external, const struct mlx5_flow_tunnel *tunnel,
1435 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error);
1437 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1438 uint64_t key, void *cb_ctx);
1439 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1440 struct mlx5_hlist_entry *entry, uint64_t key,
1442 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1443 struct mlx5_hlist_entry *entry);
1445 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1446 struct mlx5_hlist_entry *entry,
1447 uint64_t key, void *cb_ctx);
1448 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1449 uint64_t key, void *ctx);
1450 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1451 struct mlx5_hlist_entry *entry);
1453 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1454 uint64_t key, void *ctx);
1455 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1456 struct mlx5_hlist_entry *entry, uint64_t key,
1458 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1459 struct mlx5_hlist_entry *entry);
1461 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1462 struct mlx5_hlist_entry *entry,
1463 uint64_t key, void *cb_ctx);
1464 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1465 uint64_t key, void *cb_ctx);
1466 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1467 struct mlx5_hlist_entry *entry);
1469 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1470 struct mlx5_cache_entry *entry, void *ctx);
1471 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1472 struct mlx5_cache_entry *entry, void *ctx);
1473 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1474 struct mlx5_cache_entry *entry);
1476 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1477 struct mlx5_cache_entry *entry, void *cb_ctx);
1478 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1479 struct mlx5_cache_entry *entry, void *cb_ctx);
1480 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1481 struct mlx5_cache_entry *entry);
1483 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1484 struct mlx5_cache_entry *entry, void *cb_ctx);
1485 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1486 (struct mlx5_cache_list *list,
1487 struct mlx5_cache_entry *entry, void *cb_ctx);
1488 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1489 struct mlx5_cache_entry *entry);
1491 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1492 struct mlx5_cache_entry *entry, void *cb_ctx);
1493 struct mlx5_cache_entry *flow_dv_sample_create_cb
1494 (struct mlx5_cache_list *list,
1495 struct mlx5_cache_entry *entry, void *cb_ctx);
1496 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1497 struct mlx5_cache_entry *entry);
1499 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1500 struct mlx5_cache_entry *entry, void *cb_ctx);
1501 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1502 (struct mlx5_cache_list *list,
1503 struct mlx5_cache_entry *entry, void *cb_ctx);
1504 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1505 struct mlx5_cache_entry *entry);
1506 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1508 #endif /* RTE_PMD_MLX5_FLOW_H_ */