1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_alarm.h>
17 #include <mlx5_glue.h>
22 /* Private rte flow items. */
23 enum mlx5_rte_flow_item_type {
24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
25 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
38 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
39 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 #define MLX5_SHARED_ACTION_TYPE_OFFSET 30
45 MLX5_SHARED_ACTION_TYPE_RSS,
46 MLX5_SHARED_ACTION_TYPE_AGE,
49 /* Matches on selected register. */
50 struct mlx5_rte_flow_item_tag {
55 /* Modify selected register. */
56 struct mlx5_rte_flow_action_set_tag {
61 struct mlx5_flow_action_copy_mreg {
66 /* Matches on source queue. */
67 struct mlx5_rte_flow_item_tx_queue {
71 /* Feature name to allocate metadata register. */
72 enum mlx5_feature_name {
86 /* Default queue number. */
87 #define MLX5_RSSQ_DEFAULT_NUM 16
89 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
90 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
91 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
92 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
93 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
94 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
96 /* Pattern inner Layer bits. */
97 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
98 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
99 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
100 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
101 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
102 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
104 /* Pattern tunnel Layer bits. */
105 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
106 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
107 #define MLX5_FLOW_LAYER_GRE (1u << 14)
108 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
109 /* List of tunnel Layer bits continued below. */
111 /* General pattern items bits. */
112 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
113 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
114 #define MLX5_FLOW_ITEM_TAG (1u << 18)
115 #define MLX5_FLOW_ITEM_MARK (1u << 19)
117 /* Pattern MISC bits. */
118 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
119 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
120 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
122 /* Pattern tunnel Layer bits (continued). */
123 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
124 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
125 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
126 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
129 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
131 /* Pattern tunnel Layer bits (continued). */
132 #define MLX5_FLOW_LAYER_GTP (1u << 28)
134 /* Pattern eCPRI Layer bit. */
135 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
137 /* IPv6 Fragment Extension Header bit. */
138 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
139 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
141 /* Pattern tunnel Layer bits (continued). */
142 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
143 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
146 #define MLX5_FLOW_LAYER_OUTER_L3 \
147 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
148 #define MLX5_FLOW_LAYER_OUTER_L4 \
149 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
150 #define MLX5_FLOW_LAYER_OUTER \
151 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
152 MLX5_FLOW_LAYER_OUTER_L4)
155 #define MLX5_FLOW_LAYER_TUNNEL \
156 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
157 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
158 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
159 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
162 #define MLX5_FLOW_LAYER_INNER_L3 \
163 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
164 #define MLX5_FLOW_LAYER_INNER_L4 \
165 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
166 #define MLX5_FLOW_LAYER_INNER \
167 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
168 MLX5_FLOW_LAYER_INNER_L4)
171 #define MLX5_FLOW_LAYER_L2 \
172 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
173 #define MLX5_FLOW_LAYER_L3_IPV4 \
174 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
175 #define MLX5_FLOW_LAYER_L3_IPV6 \
176 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
177 #define MLX5_FLOW_LAYER_L3 \
178 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
179 #define MLX5_FLOW_LAYER_L4 \
180 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
183 #define MLX5_FLOW_ACTION_DROP (1u << 0)
184 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
185 #define MLX5_FLOW_ACTION_RSS (1u << 2)
186 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
187 #define MLX5_FLOW_ACTION_MARK (1u << 4)
188 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
189 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
190 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
191 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
192 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
193 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
194 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
195 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
196 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
197 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
198 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
199 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
200 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
201 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
202 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
203 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
204 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
205 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
206 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
207 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
208 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
209 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
210 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
211 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
212 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
213 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
214 #define MLX5_FLOW_ACTION_METER (1ull << 31)
215 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
216 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
217 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
218 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
219 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
220 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
221 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
223 #define MLX5_FLOW_FATE_ACTIONS \
224 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
225 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
226 MLX5_FLOW_ACTION_DEFAULT_MISS)
228 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
229 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
230 MLX5_FLOW_ACTION_JUMP)
233 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
234 MLX5_FLOW_ACTION_SET_IPV4_DST | \
235 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
236 MLX5_FLOW_ACTION_SET_IPV6_DST | \
237 MLX5_FLOW_ACTION_SET_TP_SRC | \
238 MLX5_FLOW_ACTION_SET_TP_DST | \
239 MLX5_FLOW_ACTION_SET_TTL | \
240 MLX5_FLOW_ACTION_DEC_TTL | \
241 MLX5_FLOW_ACTION_SET_MAC_SRC | \
242 MLX5_FLOW_ACTION_SET_MAC_DST | \
243 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
244 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
245 MLX5_FLOW_ACTION_INC_TCP_ACK | \
246 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
247 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
248 MLX5_FLOW_ACTION_SET_TAG | \
249 MLX5_FLOW_ACTION_MARK_EXT | \
250 MLX5_FLOW_ACTION_SET_META | \
251 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
252 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
254 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
255 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
257 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
260 #define IPPROTO_MPLS 137
263 /* UDP port number for MPLS */
264 #define MLX5_UDP_PORT_MPLS 6635
266 /* UDP port numbers for VxLAN. */
267 #define MLX5_UDP_PORT_VXLAN 4789
268 #define MLX5_UDP_PORT_VXLAN_GPE 4790
270 /* UDP port numbers for GENEVE. */
271 #define MLX5_UDP_PORT_GENEVE 6081
273 /* Lowest priority indicator. */
274 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
277 * Max priority for ingress\egress flow groups
278 * greater than 0 and for any transfer flow group.
279 * From user configation: 0 - 21843.
281 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
284 * Number of sub priorities.
285 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
286 * matching on the NIC (firmware dependent) L4 most have the higher priority
287 * followed by L3 and ending with L2.
289 #define MLX5_PRIORITY_MAP_L2 2
290 #define MLX5_PRIORITY_MAP_L3 1
291 #define MLX5_PRIORITY_MAP_L4 0
292 #define MLX5_PRIORITY_MAP_MAX 3
294 /* Valid layer type for IPV4 RSS. */
295 #define MLX5_IPV4_LAYER_TYPES \
296 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
297 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
298 ETH_RSS_NONFRAG_IPV4_OTHER)
300 /* IBV hash source bits for IPV4. */
301 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
303 /* Valid layer type for IPV6 RSS. */
304 #define MLX5_IPV6_LAYER_TYPES \
305 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
306 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
307 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
309 /* IBV hash source bits for IPV6. */
310 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
312 /* IBV hash bits for L3 SRC. */
313 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
315 /* IBV hash bits for L3 DST. */
316 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
318 /* IBV hash bits for TCP. */
319 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
320 IBV_RX_HASH_DST_PORT_TCP)
322 /* IBV hash bits for UDP. */
323 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
324 IBV_RX_HASH_DST_PORT_UDP)
326 /* IBV hash bits for L4 SRC. */
327 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
328 IBV_RX_HASH_SRC_PORT_UDP)
330 /* IBV hash bits for L4 DST. */
331 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
332 IBV_RX_HASH_DST_PORT_UDP)
334 /* Geneve header first 16Bit */
335 #define MLX5_GENEVE_VER_MASK 0x3
336 #define MLX5_GENEVE_VER_SHIFT 14
337 #define MLX5_GENEVE_VER_VAL(a) \
338 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
339 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
340 #define MLX5_GENEVE_OPTLEN_SHIFT 8
341 #define MLX5_GENEVE_OPTLEN_VAL(a) \
342 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
343 #define MLX5_GENEVE_OAMF_MASK 0x1
344 #define MLX5_GENEVE_OAMF_SHIFT 7
345 #define MLX5_GENEVE_OAMF_VAL(a) \
346 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
347 #define MLX5_GENEVE_CRITO_MASK 0x1
348 #define MLX5_GENEVE_CRITO_SHIFT 6
349 #define MLX5_GENEVE_CRITO_VAL(a) \
350 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
351 #define MLX5_GENEVE_RSVD_MASK 0x3F
352 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
354 * The length of the Geneve options fields, expressed in four byte multiples,
355 * not including the eight byte fixed tunnel.
357 #define MLX5_GENEVE_OPT_LEN_0 14
358 #define MLX5_GENEVE_OPT_LEN_1 63
360 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
361 sizeof(struct rte_ipv4_hdr))
362 /* GTP extension header flag. */
363 #define MLX5_GTP_EXT_HEADER_FLAG 4
365 /* GTP extension header max PDU type value. */
366 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
368 /* GTP extension header PDU type shift. */
369 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
371 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
372 #define MLX5_IPV4_FRAG_OFFSET_MASK \
373 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
375 /* Specific item's fields can accept a range of values (using spec and last). */
376 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
377 #define MLX5_ITEM_RANGE_ACCEPTED true
379 /* Software header modify action numbers of a flow. */
380 #define MLX5_ACT_NUM_MDF_IPV4 1
381 #define MLX5_ACT_NUM_MDF_IPV6 4
382 #define MLX5_ACT_NUM_MDF_MAC 2
383 #define MLX5_ACT_NUM_MDF_VID 1
384 #define MLX5_ACT_NUM_MDF_PORT 2
385 #define MLX5_ACT_NUM_MDF_TTL 1
386 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
387 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
388 #define MLX5_ACT_NUM_MDF_TCPACK 1
389 #define MLX5_ACT_NUM_SET_REG 1
390 #define MLX5_ACT_NUM_SET_TAG 1
391 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
392 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
393 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
394 #define MLX5_ACT_NUM_SET_DSCP 1
396 enum mlx5_flow_drv_type {
399 MLX5_FLOW_TYPE_VERBS,
403 /* Fate action type. */
404 enum mlx5_flow_fate_type {
405 MLX5_FLOW_FATE_NONE, /* Egress flow. */
406 MLX5_FLOW_FATE_QUEUE,
408 MLX5_FLOW_FATE_PORT_ID,
410 MLX5_FLOW_FATE_DEFAULT_MISS,
411 MLX5_FLOW_FATE_SHARED_RSS,
415 /* Matcher PRM representation */
416 struct mlx5_flow_dv_match_params {
418 /**< Size of match value. Do NOT split size and key! */
419 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
420 /**< Matcher value. This value is used as the mask or as a key. */
423 /* Matcher structure. */
424 struct mlx5_flow_dv_matcher {
425 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
426 struct mlx5_flow_tbl_resource *tbl;
427 /**< Pointer to the table(group) the matcher associated with. */
428 void *matcher_object; /**< Pointer to DV matcher */
429 uint16_t crc; /**< CRC of key. */
430 uint16_t priority; /**< Priority of matcher. */
431 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
434 #define MLX5_ENCAP_MAX_LEN 132
436 /* Encap/decap resource structure. */
437 struct mlx5_flow_dv_encap_decap_resource {
438 struct mlx5_hlist_entry entry;
439 /* Pointer to next element. */
440 uint32_t refcnt; /**< Reference counter. */
442 /**< Encap/decap action object. */
443 uint8_t buf[MLX5_ENCAP_MAX_LEN];
445 uint8_t reformat_type;
447 uint64_t flags; /**< Flags for RDMA API. */
448 uint32_t idx; /**< Index for the index memory pool. */
451 /* Tag resource structure. */
452 struct mlx5_flow_dv_tag_resource {
453 struct mlx5_hlist_entry entry;
454 /**< hash list entry for tag resource, tag value as the key. */
456 /**< Tag action object. */
457 uint32_t refcnt; /**< Reference counter. */
458 uint32_t idx; /**< Index for the index memory pool. */
459 uint32_t tag_id; /**< Tag ID. */
463 * Number of modification commands.
464 * The maximal actions amount in FW is some constant, and it is 16 in the
465 * latest releases. In some old releases, it will be limited to 8.
466 * Since there is no interface to query the capacity, the maximal value should
467 * be used to allow PMD to create the flow. The validation will be done in the
468 * lower driver layer or FW. A failure will be returned if exceeds the maximal
469 * supported actions number on the root table.
470 * On non-root tables, there is no limitation, but 32 is enough right now.
472 #define MLX5_MAX_MODIFY_NUM 32
473 #define MLX5_ROOT_TBL_MODIFY_NUM 16
475 /* Modify resource structure */
476 struct mlx5_flow_dv_modify_hdr_resource {
477 struct mlx5_hlist_entry entry;
478 void *action; /**< Modify header action object. */
479 /* Key area for hash list matching: */
480 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
481 uint32_t actions_num; /**< Number of modification actions. */
482 uint64_t flags; /**< Flags for RDMA API. */
483 struct mlx5_modification_cmd actions[];
484 /**< Modification actions. */
487 /* Modify resource key of the hash organization. */
488 union mlx5_flow_modify_hdr_key {
490 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
491 uint32_t actions_num:5; /**< Number of modification actions. */
492 uint32_t group:19; /**< Flow group id. */
493 uint32_t cksum; /**< Actions check sum. */
495 uint64_t v64; /**< full 64bits value of key */
498 /* Jump action resource structure. */
499 struct mlx5_flow_dv_jump_tbl_resource {
500 void *action; /**< Pointer to the rdma core action. */
503 /* Port ID resource structure. */
504 struct mlx5_flow_dv_port_id_action_resource {
505 struct mlx5_cache_entry entry;
506 void *action; /**< Action object. */
507 uint32_t port_id; /**< Port ID value. */
508 uint32_t idx; /**< Indexed pool memory index. */
511 /* Push VLAN action resource structure */
512 struct mlx5_flow_dv_push_vlan_action_resource {
513 struct mlx5_cache_entry entry; /* Cache entry. */
514 void *action; /**< Action object. */
515 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
516 rte_be32_t vlan_tag; /**< VLAN tag value. */
517 uint32_t idx; /**< Indexed pool memory index. */
520 /* Metadata register copy table entry. */
521 struct mlx5_flow_mreg_copy_resource {
523 * Hash list entry for copy table.
524 * - Key is 32/64-bit MARK action ID.
525 * - MUST be the first entry.
527 struct mlx5_hlist_entry hlist_ent;
528 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
529 /* List entry for device flows. */
531 uint32_t rix_flow; /* Built flow for copy. */
535 /* Table tunnel parameter. */
536 struct mlx5_flow_tbl_tunnel_prm {
537 const struct mlx5_flow_tunnel *tunnel;
542 /* Table data structure of the hash organization. */
543 struct mlx5_flow_tbl_data_entry {
544 struct mlx5_hlist_entry entry;
545 /**< hash list entry, 64-bits key inside. */
546 struct mlx5_flow_tbl_resource tbl;
547 /**< flow table resource. */
548 struct mlx5_cache_list matchers;
549 /**< matchers' header associated with the flow table. */
550 struct mlx5_flow_dv_jump_tbl_resource jump;
551 /**< jump resource, at most one for each table created. */
552 uint32_t idx; /**< index for the indexed mempool. */
553 /**< tunnel offload */
554 const struct mlx5_flow_tunnel *tunnel;
557 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
558 uint32_t is_egress:1; /**< Egress table. */
559 uint32_t is_transfer:1; /**< Transfer table. */
560 uint32_t dummy:1; /**< DR table. */
561 uint32_t reserve:27; /**< Reserved to future using. */
562 uint32_t table_id; /**< Table ID. */
565 /* Sub rdma-core actions list. */
566 struct mlx5_flow_sub_actions_list {
567 uint32_t actions_num; /**< Number of sample actions. */
568 uint64_t action_flags;
569 void *dr_queue_action;
572 void *dr_port_id_action;
573 void *dr_encap_action;
574 void *dr_jump_action;
577 /* Sample sub-actions resource list. */
578 struct mlx5_flow_sub_actions_idx {
579 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
580 uint32_t rix_tag; /**< Index to the tag action. */
582 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
583 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
584 uint32_t rix_jump; /**< Index to the jump action resource. */
587 /* Sample action resource structure. */
588 struct mlx5_flow_dv_sample_resource {
589 struct mlx5_cache_entry entry; /**< Cache entry. */
591 void *verbs_action; /**< Verbs sample action object. */
592 void **sub_actions; /**< Sample sub-action array. */
594 struct rte_eth_dev *dev; /**< Device registers the action. */
595 uint32_t idx; /** Sample object index. */
596 uint8_t ft_type; /** Flow Table Type */
597 uint32_t ft_id; /** Flow Table Level */
598 uint32_t ratio; /** Sample Ratio */
599 uint64_t set_action; /** Restore reg_c0 value */
600 void *normal_path_tbl; /** Flow Table pointer */
601 struct mlx5_flow_sub_actions_idx sample_idx;
602 /**< Action index resources. */
603 struct mlx5_flow_sub_actions_list sample_act;
604 /**< Action resources. */
607 #define MLX5_MAX_DEST_NUM 2
609 /* Destination array action resource structure. */
610 struct mlx5_flow_dv_dest_array_resource {
611 struct mlx5_cache_entry entry; /**< Cache entry. */
612 uint32_t idx; /** Destination array action object index. */
613 uint8_t ft_type; /** Flow Table Type */
614 uint8_t num_of_dest; /**< Number of destination actions. */
615 struct rte_eth_dev *dev; /**< Device registers the action. */
616 void *action; /**< Pointer to the rdma core action. */
617 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
618 /**< Action index resources. */
619 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
620 /**< Action resources. */
623 /* PMD flow priority for tunnel */
624 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
625 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
628 /** Device flow handle structure for DV mode only. */
629 struct mlx5_flow_handle_dv {
631 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
632 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
633 /**< Pointer to modify header resource in cache. */
634 uint32_t rix_encap_decap;
635 /**< Index to encap/decap resource in cache. */
636 uint32_t rix_push_vlan;
637 /**< Index to push VLAN action resource in cache. */
639 /**< Index to the tag action. */
641 /**< Index to sample action resource in cache. */
642 uint32_t rix_dest_array;
643 /**< Index to destination array resource in cache. */
646 /** Device flow handle structure: used both for creating & destroying. */
647 struct mlx5_flow_handle {
648 SILIST_ENTRY(uint32_t)next;
649 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
650 /**< Index to next device flow handle. */
652 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
653 void *drv_flow; /**< pointer to driver flow object. */
654 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
655 uint32_t mark:1; /**< Metadate rxq mark flag. */
656 uint32_t fate_action:3; /**< Fate action type. */
658 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
659 uint32_t rix_jump; /**< Index to the jump action resource. */
660 uint32_t rix_port_id_action;
661 /**< Index to port ID action resource. */
663 /**< Generic value indicates the fate action. */
664 uint32_t rix_default_fate;
665 /**< Indicates default miss fate action. */
667 /**< Indicates shared RSS fate action. */
669 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
670 struct mlx5_flow_handle_dv dvh;
675 * Size for Verbs device flow handle structure only. Do not use the DV only
676 * structure in Verbs. No DV flows attributes will be accessed.
677 * Macro offsetof() could also be used here.
679 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
680 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
681 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
683 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
687 * Max number of actions per DV flow.
688 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
689 * in rdma-core file providers/mlx5/verbs.c.
691 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
693 /** Device flow structure only for DV flow creation. */
694 struct mlx5_flow_dv_workspace {
695 uint32_t group; /**< The group index. */
696 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
697 int actions_n; /**< number of actions. */
698 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
699 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
700 /**< Pointer to encap/decap resource in cache. */
701 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
702 /**< Pointer to push VLAN action resource in cache. */
703 struct mlx5_flow_dv_tag_resource *tag_resource;
704 /**< pointer to the tag action. */
705 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
706 /**< Pointer to port ID action resource. */
707 struct mlx5_flow_dv_jump_tbl_resource *jump;
708 /**< Pointer to the jump action resource. */
709 struct mlx5_flow_dv_match_params value;
710 /**< Holds the value that the packet is compared to. */
711 struct mlx5_flow_dv_sample_resource *sample_res;
712 /**< Pointer to the sample action resource. */
713 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
714 /**< Pointer to the destination array resource. */
717 #ifdef HAVE_INFINIBAND_VERBS_H
719 * Maximal Verbs flow specifications & actions size.
720 * Some elements are mutually exclusive, but enough space should be allocated.
721 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
722 * 2. One tunnel header (exception: GRE + MPLS),
723 * SPEC length: GRE == tunnel.
724 * Actions: 1. 1 Mark OR Flag.
725 * 2. 1 Drop (if any).
726 * 3. No limitation for counters, but it makes no sense to support too
727 * many counters in a single device flow.
729 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
730 #define MLX5_VERBS_MAX_SPEC_SIZE \
732 (2 * (sizeof(struct ibv_flow_spec_eth) + \
733 sizeof(struct ibv_flow_spec_ipv6) + \
734 sizeof(struct ibv_flow_spec_tcp_udp)) + \
735 sizeof(struct ibv_flow_spec_gre) + \
736 sizeof(struct ibv_flow_spec_mpls)) \
739 #define MLX5_VERBS_MAX_SPEC_SIZE \
741 (2 * (sizeof(struct ibv_flow_spec_eth) + \
742 sizeof(struct ibv_flow_spec_ipv6) + \
743 sizeof(struct ibv_flow_spec_tcp_udp)) + \
744 sizeof(struct ibv_flow_spec_tunnel)) \
748 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
749 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
750 #define MLX5_VERBS_MAX_ACT_SIZE \
752 sizeof(struct ibv_flow_spec_action_tag) + \
753 sizeof(struct ibv_flow_spec_action_drop) + \
754 sizeof(struct ibv_flow_spec_counter_action) * 4 \
757 #define MLX5_VERBS_MAX_ACT_SIZE \
759 sizeof(struct ibv_flow_spec_action_tag) + \
760 sizeof(struct ibv_flow_spec_action_drop) \
764 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
765 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
767 /** Device flow structure only for Verbs flow creation. */
768 struct mlx5_flow_verbs_workspace {
769 unsigned int size; /**< Size of the attribute. */
770 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
771 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
772 /**< Specifications & actions buffer of verbs flow. */
774 #endif /* HAVE_INFINIBAND_VERBS_H */
776 #define MLX5_SCALE_FLOW_GROUP_BIT 0
777 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
779 /** Maximal number of device sub-flows supported. */
780 #define MLX5_NUM_MAX_DEV_FLOWS 32
782 /** Device flow structure. */
785 struct rte_flow *flow; /**< Pointer to the main flow. */
786 uint32_t flow_idx; /**< The memory pool index to the main flow. */
787 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
789 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
790 bool external; /**< true if the flow is created external to PMD. */
791 uint8_t ingress:1; /**< 1 if the flow is ingress. */
792 uint8_t skip_scale:2;
794 * Each Bit be set to 1 if Skip the scale the flow group with factor.
795 * If bit0 be set to 1, then skip the scale the original flow group;
796 * If bit1 be set to 1, then skip the scale the jump flow group if
797 * having jump action.
798 * 00: Enable scale in a flow, default value.
799 * 01: Skip scale the flow group with factor, enable scale the group
801 * 10: Enable scale the group with factor, skip scale the group of
803 * 11: Skip scale the table with factor both for flow group and jump
807 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
808 struct mlx5_flow_dv_workspace dv;
810 #ifdef HAVE_INFINIBAND_VERBS_H
811 struct mlx5_flow_verbs_workspace verbs;
814 struct mlx5_flow_handle *handle;
815 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
816 const struct mlx5_flow_tunnel *tunnel;
819 /* Flow meter state. */
820 #define MLX5_FLOW_METER_DISABLE 0
821 #define MLX5_FLOW_METER_ENABLE 1
823 #define MLX5_MAN_WIDTH 8
824 /* Modify this value if enum rte_mtr_color changes. */
825 #define RTE_MTR_DROPPED RTE_COLORS
827 /* Meter policer statistics */
828 struct mlx5_flow_policer_stats {
829 uint32_t cnt[RTE_COLORS + 1];
830 /**< Color counter, extra for drop. */
832 /**< Statistics mask for the colors. */
835 /* Meter table structure. */
836 struct mlx5_meter_domain_info {
837 struct mlx5_flow_tbl_resource *tbl;
839 struct mlx5_flow_tbl_resource *sfx_tbl;
840 /**< Meter suffix table. */
842 /**< Meter color not match default criteria. */
844 /**< Meter color match criteria. */
846 /**< Meter match action. */
847 void *policer_rules[RTE_MTR_DROPPED + 1];
848 /**< Meter policer for the match. */
851 /* Meter table set for TX RX FDB. */
852 struct mlx5_meter_domains_infos {
854 /**< Table user count. */
855 struct mlx5_meter_domain_info egress;
856 /**< TX meter table. */
857 struct mlx5_meter_domain_info ingress;
858 /**< RX meter table. */
859 struct mlx5_meter_domain_info transfer;
860 /**< FDB meter table. */
862 /**< Drop action as not matched. */
863 void *count_actns[RTE_MTR_DROPPED + 1];
864 /**< Counters for match and unmatched statistics. */
865 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
866 /**< Flow meter parameter. */
868 /**< Flow meter parameter size. */
870 /**< Flow meter action. */
873 /* Meter parameter structure. */
874 struct mlx5_flow_meter {
875 TAILQ_ENTRY(mlx5_flow_meter) next;
876 /**< Pointer to the next flow meter structure. */
877 uint32_t idx; /* Index to meter object. */
880 struct mlx5_flow_meter_profile *profile;
881 /**< Meter profile parameters. */
883 rte_spinlock_t sl; /**< Meter action spinlock. */
885 /** Policer actions (per meter output color). */
886 enum rte_mtr_policer_action action[RTE_COLORS];
888 /** Set of stats counters to be enabled.
889 * @see enum rte_mtr_stats_type
893 /**< Rule applies to ingress traffic. */
896 /**< Rule applies to egress traffic. */
899 * Instead of simply matching the properties of traffic as it would
900 * appear on a given DPDK port ID, enabling this attribute transfers
901 * a flow rule to the lowest possible level of any device endpoints
902 * found in the pattern.
904 * When supported, this effectively enables an application to
905 * re-route traffic not necessarily intended for it (e.g. coming
906 * from or addressed to different physical ports, VFs or
907 * applications) at the device level.
909 * It complements the behavior of some pattern items such as
910 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
912 * When transferring flow rules, ingress and egress attributes keep
913 * their original meaning, as if processing traffic emitted or
914 * received by the application.
917 struct mlx5_meter_domains_infos *mfts;
918 /**< Flow table created for this meter. */
919 struct mlx5_flow_policer_stats policer_stats;
920 /**< Meter policer statistics. */
923 uint32_t active_state:1;
926 /**< Meter shared or not. */
929 /* RFC2697 parameter structure. */
930 struct mlx5_flow_meter_srtcm_rfc2697_prm {
931 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
932 uint32_t cbs_exponent:5;
933 uint32_t cbs_mantissa:8;
934 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
935 uint32_t cir_exponent:5;
936 uint32_t cir_mantissa:8;
937 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
938 uint32_t ebs_exponent:5;
939 uint32_t ebs_mantissa:8;
942 /* Flow meter profile structure. */
943 struct mlx5_flow_meter_profile {
944 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
945 /**< Pointer to the next flow meter structure. */
946 uint32_t meter_profile_id; /**< Profile id. */
947 struct rte_mtr_meter_profile profile; /**< Profile detail. */
949 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
950 /**< srtcm_rfc2697 struct. */
952 uint32_t ref_cnt; /**< Use count. */
955 #define MLX5_MAX_TUNNELS 256
956 #define MLX5_TNL_MISS_RULE_PRIORITY 3
957 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
960 * When tunnel offload is active, all JUMP group ids are converted
961 * using the same method. That conversion is applied both to tunnel and
962 * regular rule types.
963 * Group ids used in tunnel rules are relative to it's tunnel (!).
964 * Application can create number of steer rules, using the same
965 * tunnel, with different group id in each rule.
966 * Each tunnel stores its groups internally in PMD tunnel object.
967 * Groups used in regular rules do not belong to any tunnel and are stored
971 struct mlx5_flow_tunnel {
972 LIST_ENTRY(mlx5_flow_tunnel) chain;
973 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
974 uint32_t tunnel_id; /** unique tunnel ID */
976 struct rte_flow_action action;
977 struct rte_flow_item item;
978 struct mlx5_hlist *groups; /** tunnel groups */
981 /** PMD tunnel related context */
982 struct mlx5_flow_tunnel_hub {
984 * Access to the list MUST be MT protected
986 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
987 /* protect access to the tunnels list */
989 struct mlx5_hlist *groups; /** non tunnel groups */
992 /* convert jump group to flow table ID in tunnel rules */
993 struct tunnel_tbl_entry {
994 struct mlx5_hlist_entry hash;
1000 static inline uint32_t
1001 tunnel_id_to_flow_tbl(uint32_t id)
1003 return id | (1u << 16);
1006 static inline uint32_t
1007 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
1009 return flow_tbl & ~(1u << 16);
1012 union tunnel_tbl_key {
1020 static inline struct mlx5_flow_tunnel_hub *
1021 mlx5_tunnel_hub(struct rte_eth_dev *dev)
1023 struct mlx5_priv *priv = dev->data->dev_private;
1024 return priv->sh->tunnel_hub;
1028 is_tunnel_offload_active(struct rte_eth_dev *dev)
1030 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1031 struct mlx5_priv *priv = dev->data->dev_private;
1032 return !!priv->config.dv_miss_info;
1040 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
1041 __rte_unused const struct rte_flow_attr *attr,
1042 __rte_unused const struct rte_flow_item items[],
1043 __rte_unused const struct rte_flow_action actions[])
1045 return (items[0].type == (typeof(items[0].type))
1046 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1050 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1051 __rte_unused const struct rte_flow_attr *attr,
1052 __rte_unused const struct rte_flow_item items[],
1053 __rte_unused const struct rte_flow_action actions[])
1055 return (actions[0].type == (typeof(actions[0].type))
1056 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1059 static inline const struct mlx5_flow_tunnel *
1060 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1062 return actions[0].conf;
1065 static inline const struct mlx5_flow_tunnel *
1066 flow_items_to_tunnel(const struct rte_flow_item items[])
1068 return items[0].spec;
1071 /* Flow structure. */
1073 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1074 uint32_t dev_handles;
1075 /**< Device flow handles that are part of the flow. */
1076 uint32_t drv_type:2; /**< Driver type. */
1078 uint32_t meter:16; /**< Holds flow meter id. */
1079 uint32_t rix_mreg_copy;
1080 /**< Index to metadata register copy table resource. */
1081 uint32_t counter; /**< Holds flow counter. */
1082 uint32_t tunnel_id; /**< Tunnel id */
1083 uint32_t age; /**< Holds ASO age bit index. */
1084 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1088 * Define list of valid combinations of RX Hash fields
1089 * (see enum ibv_rx_hash_fields).
1091 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1092 #define MLX5_RSS_HASH_IPV4_TCP \
1093 (MLX5_RSS_HASH_IPV4 | \
1094 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1095 #define MLX5_RSS_HASH_IPV4_UDP \
1096 (MLX5_RSS_HASH_IPV4 | \
1097 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1098 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1099 #define MLX5_RSS_HASH_IPV6_TCP \
1100 (MLX5_RSS_HASH_IPV6 | \
1101 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1102 #define MLX5_RSS_HASH_IPV6_UDP \
1103 (MLX5_RSS_HASH_IPV6 | \
1104 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1105 #define MLX5_RSS_HASH_NONE 0ULL
1107 /* array of valid combinations of RX Hash fields for RSS */
1108 static const uint64_t mlx5_rss_hash_fields[] = {
1110 MLX5_RSS_HASH_IPV4_TCP,
1111 MLX5_RSS_HASH_IPV4_UDP,
1113 MLX5_RSS_HASH_IPV6_TCP,
1114 MLX5_RSS_HASH_IPV6_UDP,
1118 /* Shared RSS action structure */
1119 struct mlx5_shared_action_rss {
1120 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1121 uint32_t refcnt; /**< Atomically accessed refcnt. */
1122 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1123 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1124 struct mlx5_ind_table_obj *ind_tbl;
1125 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1126 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1127 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1128 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
1129 /**< Hash RX queue indexes for tunneled RSS */
1130 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1133 struct rte_flow_shared_action {
1137 /* Thread specific flow workspace intermediate data. */
1138 struct mlx5_flow_workspace {
1139 /* If creating another flow in same thread, push new as stack. */
1140 struct mlx5_flow_workspace *prev;
1141 struct mlx5_flow_workspace *next;
1142 uint32_t inuse; /* can't create new flow with current. */
1143 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1144 struct mlx5_flow_rss_desc rss_desc;
1145 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1146 uint32_t flow_idx; /* Intermediate device flow index. */
1149 struct mlx5_flow_split_info {
1151 /**< True if flow is created by request external to PMD. */
1152 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1153 uint32_t flow_idx; /**< This memory pool index to the flow. */
1154 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1155 uint64_t prefix_layers; /**< Prefix subflow layers. */
1158 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1159 const struct rte_flow_attr *attr,
1160 const struct rte_flow_item items[],
1161 const struct rte_flow_action actions[],
1164 struct rte_flow_error *error);
1165 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1166 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1167 const struct rte_flow_item items[],
1168 const struct rte_flow_action actions[], struct rte_flow_error *error);
1169 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1170 struct mlx5_flow *dev_flow,
1171 const struct rte_flow_attr *attr,
1172 const struct rte_flow_item items[],
1173 const struct rte_flow_action actions[],
1174 struct rte_flow_error *error);
1175 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1176 struct rte_flow_error *error);
1177 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1178 struct rte_flow *flow);
1179 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1180 struct rte_flow *flow);
1181 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1182 struct rte_flow *flow,
1183 const struct rte_flow_action *actions,
1185 struct rte_flow_error *error);
1186 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1187 (struct rte_eth_dev *dev,
1188 const struct mlx5_flow_meter *fm);
1189 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1190 struct mlx5_meter_domains_infos *tbls);
1191 typedef int (*mlx5_flow_create_policer_rules_t)
1192 (struct rte_eth_dev *dev,
1193 struct mlx5_flow_meter *fm,
1194 const struct rte_flow_attr *attr);
1195 typedef int (*mlx5_flow_destroy_policer_rules_t)
1196 (struct rte_eth_dev *dev,
1197 const struct mlx5_flow_meter *fm,
1198 const struct rte_flow_attr *attr);
1199 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1200 (struct rte_eth_dev *dev);
1201 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1203 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1205 bool clear, uint64_t *pkts,
1207 typedef int (*mlx5_flow_get_aged_flows_t)
1208 (struct rte_eth_dev *dev,
1210 uint32_t nb_contexts,
1211 struct rte_flow_error *error);
1212 typedef int (*mlx5_flow_action_validate_t)
1213 (struct rte_eth_dev *dev,
1214 const struct rte_flow_shared_action_conf *conf,
1215 const struct rte_flow_action *action,
1216 struct rte_flow_error *error);
1217 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1218 (struct rte_eth_dev *dev,
1219 const struct rte_flow_shared_action_conf *conf,
1220 const struct rte_flow_action *action,
1221 struct rte_flow_error *error);
1222 typedef int (*mlx5_flow_action_destroy_t)
1223 (struct rte_eth_dev *dev,
1224 struct rte_flow_shared_action *action,
1225 struct rte_flow_error *error);
1226 typedef int (*mlx5_flow_action_update_t)
1227 (struct rte_eth_dev *dev,
1228 struct rte_flow_shared_action *action,
1229 const void *action_conf,
1230 struct rte_flow_error *error);
1231 typedef int (*mlx5_flow_action_query_t)
1232 (struct rte_eth_dev *dev,
1233 const struct rte_flow_shared_action *action,
1235 struct rte_flow_error *error);
1236 typedef int (*mlx5_flow_sync_domain_t)
1237 (struct rte_eth_dev *dev,
1241 struct mlx5_flow_driver_ops {
1242 mlx5_flow_validate_t validate;
1243 mlx5_flow_prepare_t prepare;
1244 mlx5_flow_translate_t translate;
1245 mlx5_flow_apply_t apply;
1246 mlx5_flow_remove_t remove;
1247 mlx5_flow_destroy_t destroy;
1248 mlx5_flow_query_t query;
1249 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1250 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1251 mlx5_flow_create_policer_rules_t create_policer_rules;
1252 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1253 mlx5_flow_counter_alloc_t counter_alloc;
1254 mlx5_flow_counter_free_t counter_free;
1255 mlx5_flow_counter_query_t counter_query;
1256 mlx5_flow_get_aged_flows_t get_aged_flows;
1257 mlx5_flow_action_validate_t action_validate;
1258 mlx5_flow_action_create_t action_create;
1259 mlx5_flow_action_destroy_t action_destroy;
1260 mlx5_flow_action_update_t action_update;
1261 mlx5_flow_action_query_t action_query;
1262 mlx5_flow_sync_domain_t sync_domain;
1267 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1269 struct flow_grp_info {
1270 uint64_t external:1;
1271 uint64_t transfer:1;
1272 uint64_t fdb_def_rule:1;
1273 /* force standard group translation */
1274 uint64_t std_tbl_fix:1;
1275 uint64_t skip_scale:2;
1279 tunnel_use_standard_attr_group_translate
1280 (struct rte_eth_dev *dev,
1281 const struct mlx5_flow_tunnel *tunnel,
1282 const struct rte_flow_attr *attr,
1283 const struct rte_flow_item items[],
1284 const struct rte_flow_action actions[])
1288 if (!is_tunnel_offload_active(dev))
1289 /* no tunnel offload API */
1293 * OvS will use jump to group 0 in tunnel steer rule.
1294 * If tunnel steer rule starts from group 0 (attr.group == 0)
1295 * that 0 group must be translated with standard method.
1296 * attr.group == 0 in tunnel match rule translated with tunnel
1299 verdict = !attr->group &&
1300 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1303 * non-tunnel group translation uses standard method for
1304 * root group only: attr.group == 0
1306 verdict = !attr->group;
1312 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1313 const struct mlx5_flow_tunnel *tunnel,
1314 uint32_t group, uint32_t *table,
1315 const struct flow_grp_info *flags,
1316 struct rte_flow_error *error);
1317 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1318 int tunnel, uint64_t layer_types,
1319 uint64_t hash_fields);
1320 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1321 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1322 uint32_t subpriority);
1323 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1324 const struct rte_flow_attr *attr);
1325 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1326 const struct rte_flow_attr *attr,
1327 uint32_t subpriority);
1328 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1329 enum mlx5_feature_name feature,
1331 struct rte_flow_error *error);
1332 const struct rte_flow_action *mlx5_flow_find_action
1333 (const struct rte_flow_action *actions,
1334 enum rte_flow_action_type action);
1335 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1336 const struct rte_flow_action *action,
1337 struct rte_flow_error *error);
1338 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1339 const struct rte_flow_attr *attr,
1340 struct rte_flow_error *error);
1341 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1342 const struct rte_flow_attr *attr,
1343 struct rte_flow_error *error);
1344 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1345 const struct rte_flow_attr *attr,
1346 struct rte_flow_error *error);
1347 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1348 uint64_t action_flags,
1349 const struct rte_flow_attr *attr,
1350 struct rte_flow_error *error);
1351 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1352 uint64_t action_flags,
1353 struct rte_eth_dev *dev,
1354 const struct rte_flow_attr *attr,
1355 struct rte_flow_error *error);
1356 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1357 uint64_t action_flags,
1358 struct rte_eth_dev *dev,
1359 const struct rte_flow_attr *attr,
1360 uint64_t item_flags,
1361 struct rte_flow_error *error);
1362 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1363 const struct rte_flow_attr *attr,
1364 struct rte_flow_error *error);
1365 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1366 const struct rte_flow_attr *attributes,
1367 struct rte_flow_error *error);
1368 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1369 const uint8_t *mask,
1370 const uint8_t *nic_mask,
1372 bool range_accepted,
1373 struct rte_flow_error *error);
1374 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1375 uint64_t item_flags, bool ext_vlan_sup,
1376 struct rte_flow_error *error);
1377 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1378 uint64_t item_flags,
1379 uint8_t target_protocol,
1380 struct rte_flow_error *error);
1381 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1382 uint64_t item_flags,
1383 const struct rte_flow_item *gre_item,
1384 struct rte_flow_error *error);
1385 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1386 uint64_t item_flags,
1388 uint16_t ether_type,
1389 const struct rte_flow_item_ipv4 *acc_mask,
1390 bool range_accepted,
1391 struct rte_flow_error *error);
1392 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1393 uint64_t item_flags,
1395 uint16_t ether_type,
1396 const struct rte_flow_item_ipv6 *acc_mask,
1397 struct rte_flow_error *error);
1398 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1399 const struct rte_flow_item *item,
1400 uint64_t item_flags,
1401 uint64_t prev_layer,
1402 struct rte_flow_error *error);
1403 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1404 uint64_t item_flags,
1405 uint8_t target_protocol,
1406 const struct rte_flow_item_tcp *flow_mask,
1407 struct rte_flow_error *error);
1408 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1409 uint64_t item_flags,
1410 uint8_t target_protocol,
1411 struct rte_flow_error *error);
1412 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1413 uint64_t item_flags,
1414 struct rte_eth_dev *dev,
1415 struct rte_flow_error *error);
1416 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1417 uint64_t item_flags,
1418 struct rte_flow_error *error);
1419 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1420 uint64_t item_flags,
1421 struct rte_eth_dev *dev,
1422 struct rte_flow_error *error);
1423 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1424 uint64_t item_flags,
1425 uint8_t target_protocol,
1426 struct rte_flow_error *error);
1427 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1428 uint64_t item_flags,
1429 uint8_t target_protocol,
1430 struct rte_flow_error *error);
1431 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1432 uint64_t item_flags,
1433 uint8_t target_protocol,
1434 struct rte_flow_error *error);
1435 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1436 uint64_t item_flags,
1437 struct rte_eth_dev *dev,
1438 struct rte_flow_error *error);
1439 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1441 const struct rte_flow_item *geneve_item,
1442 struct rte_eth_dev *dev,
1443 struct rte_flow_error *error);
1444 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1445 uint64_t item_flags,
1447 uint16_t ether_type,
1448 const struct rte_flow_item_ecpri *acc_mask,
1449 struct rte_flow_error *error);
1450 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1451 (struct rte_eth_dev *dev,
1452 const struct mlx5_flow_meter *fm);
1453 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1454 struct mlx5_meter_domains_infos *tbl);
1455 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1456 struct mlx5_flow_meter *fm,
1457 const struct rte_flow_attr *attr);
1458 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1459 struct mlx5_flow_meter *fm,
1460 const struct rte_flow_attr *attr);
1461 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1462 struct rte_mtr_error *error);
1463 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1464 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1465 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1466 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1468 /* Hash list callbacks for flow tables: */
1469 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1470 uint64_t key, void *entry_ctx);
1471 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1472 struct mlx5_hlist_entry *entry, uint64_t key,
1474 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1475 struct mlx5_hlist_entry *entry);
1476 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1477 uint32_t table_id, uint8_t egress, uint8_t transfer,
1478 bool external, const struct mlx5_flow_tunnel *tunnel,
1479 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error);
1481 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1482 uint64_t key, void *cb_ctx);
1483 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1484 struct mlx5_hlist_entry *entry, uint64_t key,
1486 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1487 struct mlx5_hlist_entry *entry);
1489 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1490 struct mlx5_hlist_entry *entry,
1491 uint64_t key, void *cb_ctx);
1492 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1493 uint64_t key, void *ctx);
1494 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1495 struct mlx5_hlist_entry *entry);
1497 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1498 uint64_t key, void *ctx);
1499 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1500 struct mlx5_hlist_entry *entry, uint64_t key,
1502 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1503 struct mlx5_hlist_entry *entry);
1505 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1506 struct mlx5_hlist_entry *entry,
1507 uint64_t key, void *cb_ctx);
1508 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1509 uint64_t key, void *cb_ctx);
1510 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1511 struct mlx5_hlist_entry *entry);
1513 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1514 struct mlx5_cache_entry *entry, void *ctx);
1515 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1516 struct mlx5_cache_entry *entry, void *ctx);
1517 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1518 struct mlx5_cache_entry *entry);
1520 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1521 struct mlx5_cache_entry *entry, void *cb_ctx);
1522 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1523 struct mlx5_cache_entry *entry, void *cb_ctx);
1524 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1525 struct mlx5_cache_entry *entry);
1527 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1528 struct mlx5_cache_entry *entry, void *cb_ctx);
1529 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1530 (struct mlx5_cache_list *list,
1531 struct mlx5_cache_entry *entry, void *cb_ctx);
1532 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1533 struct mlx5_cache_entry *entry);
1535 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1536 struct mlx5_cache_entry *entry, void *cb_ctx);
1537 struct mlx5_cache_entry *flow_dv_sample_create_cb
1538 (struct mlx5_cache_list *list,
1539 struct mlx5_cache_entry *entry, void *cb_ctx);
1540 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1541 struct mlx5_cache_entry *entry);
1543 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1544 struct mlx5_cache_entry *entry, void *cb_ctx);
1545 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1546 (struct mlx5_cache_list *list,
1547 struct mlx5_cache_entry *entry, void *cb_ctx);
1548 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1549 struct mlx5_cache_entry *entry);
1550 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1552 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1553 const struct rte_flow_item *item,
1554 struct rte_flow_error *error);
1556 void flow_release_workspace(void *data);
1557 int mlx5_flow_os_init_workspace_once(void);
1558 void *mlx5_flow_os_get_specific_workspace(void);
1559 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1560 void mlx5_flow_os_release_workspace(void);
1563 #endif /* RTE_PMD_MLX5_FLOW_H_ */