1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_alarm.h>
17 #include <mlx5_glue.h>
22 /* Private rte flow items. */
23 enum mlx5_rte_flow_item_type {
24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
25 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
38 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
39 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 #define MLX5_SHARED_ACTION_TYPE_OFFSET 30
45 MLX5_SHARED_ACTION_TYPE_RSS,
46 MLX5_SHARED_ACTION_TYPE_AGE,
49 /* Matches on selected register. */
50 struct mlx5_rte_flow_item_tag {
55 /* Modify selected register. */
56 struct mlx5_rte_flow_action_set_tag {
61 struct mlx5_flow_action_copy_mreg {
66 /* Matches on source queue. */
67 struct mlx5_rte_flow_item_tx_queue {
71 /* Feature name to allocate metadata register. */
72 enum mlx5_feature_name {
86 /* Default queue number. */
87 #define MLX5_RSSQ_DEFAULT_NUM 16
89 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
90 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
91 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
92 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
93 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
94 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
96 /* Pattern inner Layer bits. */
97 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
98 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
99 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
100 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
101 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
102 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
104 /* Pattern tunnel Layer bits. */
105 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
106 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
107 #define MLX5_FLOW_LAYER_GRE (1u << 14)
108 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
109 /* List of tunnel Layer bits continued below. */
111 /* General pattern items bits. */
112 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
113 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
114 #define MLX5_FLOW_ITEM_TAG (1u << 18)
115 #define MLX5_FLOW_ITEM_MARK (1u << 19)
117 /* Pattern MISC bits. */
118 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
119 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
120 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
122 /* Pattern tunnel Layer bits (continued). */
123 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
124 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
125 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
126 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
129 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
131 /* Pattern tunnel Layer bits (continued). */
132 #define MLX5_FLOW_LAYER_GTP (1u << 28)
134 /* Pattern eCPRI Layer bit. */
135 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
137 /* IPv6 Fragment Extension Header bit. */
138 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
139 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
141 /* Pattern tunnel Layer bits (continued). */
142 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
145 #define MLX5_FLOW_LAYER_OUTER_L3 \
146 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
147 #define MLX5_FLOW_LAYER_OUTER_L4 \
148 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
149 #define MLX5_FLOW_LAYER_OUTER \
150 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
151 MLX5_FLOW_LAYER_OUTER_L4)
154 #define MLX5_FLOW_LAYER_TUNNEL \
155 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
156 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
157 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
158 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
161 #define MLX5_FLOW_LAYER_INNER_L3 \
162 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
163 #define MLX5_FLOW_LAYER_INNER_L4 \
164 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
165 #define MLX5_FLOW_LAYER_INNER \
166 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
167 MLX5_FLOW_LAYER_INNER_L4)
170 #define MLX5_FLOW_LAYER_L2 \
171 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
172 #define MLX5_FLOW_LAYER_L3_IPV4 \
173 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
174 #define MLX5_FLOW_LAYER_L3_IPV6 \
175 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
176 #define MLX5_FLOW_LAYER_L3 \
177 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
178 #define MLX5_FLOW_LAYER_L4 \
179 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
182 #define MLX5_FLOW_ACTION_DROP (1u << 0)
183 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
184 #define MLX5_FLOW_ACTION_RSS (1u << 2)
185 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
186 #define MLX5_FLOW_ACTION_MARK (1u << 4)
187 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
188 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
189 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
190 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
191 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
192 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
193 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
194 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
195 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
196 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
197 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
198 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
199 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
200 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
201 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
202 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
203 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
204 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
205 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
206 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
207 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
208 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
209 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
210 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
211 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
212 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
213 #define MLX5_FLOW_ACTION_METER (1ull << 31)
214 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
215 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
216 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
217 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
218 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
219 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
220 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
222 #define MLX5_FLOW_FATE_ACTIONS \
223 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
224 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
225 MLX5_FLOW_ACTION_DEFAULT_MISS)
227 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
228 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
229 MLX5_FLOW_ACTION_JUMP)
232 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
233 MLX5_FLOW_ACTION_SET_IPV4_DST | \
234 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
235 MLX5_FLOW_ACTION_SET_IPV6_DST | \
236 MLX5_FLOW_ACTION_SET_TP_SRC | \
237 MLX5_FLOW_ACTION_SET_TP_DST | \
238 MLX5_FLOW_ACTION_SET_TTL | \
239 MLX5_FLOW_ACTION_DEC_TTL | \
240 MLX5_FLOW_ACTION_SET_MAC_SRC | \
241 MLX5_FLOW_ACTION_SET_MAC_DST | \
242 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
243 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
244 MLX5_FLOW_ACTION_INC_TCP_ACK | \
245 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
246 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
247 MLX5_FLOW_ACTION_SET_TAG | \
248 MLX5_FLOW_ACTION_MARK_EXT | \
249 MLX5_FLOW_ACTION_SET_META | \
250 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
251 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
253 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
254 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
256 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
259 #define IPPROTO_MPLS 137
262 /* UDP port number for MPLS */
263 #define MLX5_UDP_PORT_MPLS 6635
265 /* UDP port numbers for VxLAN. */
266 #define MLX5_UDP_PORT_VXLAN 4789
267 #define MLX5_UDP_PORT_VXLAN_GPE 4790
269 /* UDP port numbers for GENEVE. */
270 #define MLX5_UDP_PORT_GENEVE 6081
272 /* Priority reserved for default flows. */
273 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
276 * Number of sub priorities.
277 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
278 * matching on the NIC (firmware dependent) L4 most have the higher priority
279 * followed by L3 and ending with L2.
281 #define MLX5_PRIORITY_MAP_L2 2
282 #define MLX5_PRIORITY_MAP_L3 1
283 #define MLX5_PRIORITY_MAP_L4 0
284 #define MLX5_PRIORITY_MAP_MAX 3
286 /* Valid layer type for IPV4 RSS. */
287 #define MLX5_IPV4_LAYER_TYPES \
288 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
289 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
290 ETH_RSS_NONFRAG_IPV4_OTHER)
292 /* IBV hash source bits for IPV4. */
293 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
295 /* Valid layer type for IPV6 RSS. */
296 #define MLX5_IPV6_LAYER_TYPES \
297 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
298 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
299 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
301 /* IBV hash source bits for IPV6. */
302 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
304 /* IBV hash bits for L3 SRC. */
305 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
307 /* IBV hash bits for L3 DST. */
308 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
310 /* IBV hash bits for TCP. */
311 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
312 IBV_RX_HASH_DST_PORT_TCP)
314 /* IBV hash bits for UDP. */
315 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
316 IBV_RX_HASH_DST_PORT_UDP)
318 /* IBV hash bits for L4 SRC. */
319 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
320 IBV_RX_HASH_SRC_PORT_UDP)
322 /* IBV hash bits for L4 DST. */
323 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
324 IBV_RX_HASH_DST_PORT_UDP)
326 /* Geneve header first 16Bit */
327 #define MLX5_GENEVE_VER_MASK 0x3
328 #define MLX5_GENEVE_VER_SHIFT 14
329 #define MLX5_GENEVE_VER_VAL(a) \
330 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
331 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
332 #define MLX5_GENEVE_OPTLEN_SHIFT 7
333 #define MLX5_GENEVE_OPTLEN_VAL(a) \
334 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
335 #define MLX5_GENEVE_OAMF_MASK 0x1
336 #define MLX5_GENEVE_OAMF_SHIFT 7
337 #define MLX5_GENEVE_OAMF_VAL(a) \
338 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
339 #define MLX5_GENEVE_CRITO_MASK 0x1
340 #define MLX5_GENEVE_CRITO_SHIFT 6
341 #define MLX5_GENEVE_CRITO_VAL(a) \
342 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
343 #define MLX5_GENEVE_RSVD_MASK 0x3F
344 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
346 * The length of the Geneve options fields, expressed in four byte multiples,
347 * not including the eight byte fixed tunnel.
349 #define MLX5_GENEVE_OPT_LEN_0 14
350 #define MLX5_GENEVE_OPT_LEN_1 63
352 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
353 sizeof(struct rte_ipv4_hdr))
354 /* GTP extension header flag. */
355 #define MLX5_GTP_EXT_HEADER_FLAG 4
357 /* GTP extension header max PDU type value. */
358 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
360 /* GTP extension header PDU type shift. */
361 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
363 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
364 #define MLX5_IPV4_FRAG_OFFSET_MASK \
365 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
367 /* Specific item's fields can accept a range of values (using spec and last). */
368 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
369 #define MLX5_ITEM_RANGE_ACCEPTED true
371 /* Software header modify action numbers of a flow. */
372 #define MLX5_ACT_NUM_MDF_IPV4 1
373 #define MLX5_ACT_NUM_MDF_IPV6 4
374 #define MLX5_ACT_NUM_MDF_MAC 2
375 #define MLX5_ACT_NUM_MDF_VID 1
376 #define MLX5_ACT_NUM_MDF_PORT 2
377 #define MLX5_ACT_NUM_MDF_TTL 1
378 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
379 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
380 #define MLX5_ACT_NUM_MDF_TCPACK 1
381 #define MLX5_ACT_NUM_SET_REG 1
382 #define MLX5_ACT_NUM_SET_TAG 1
383 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
384 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
385 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
386 #define MLX5_ACT_NUM_SET_DSCP 1
388 enum mlx5_flow_drv_type {
391 MLX5_FLOW_TYPE_VERBS,
395 /* Fate action type. */
396 enum mlx5_flow_fate_type {
397 MLX5_FLOW_FATE_NONE, /* Egress flow. */
398 MLX5_FLOW_FATE_QUEUE,
400 MLX5_FLOW_FATE_PORT_ID,
402 MLX5_FLOW_FATE_DEFAULT_MISS,
403 MLX5_FLOW_FATE_SHARED_RSS,
407 /* Matcher PRM representation */
408 struct mlx5_flow_dv_match_params {
410 /**< Size of match value. Do NOT split size and key! */
411 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
412 /**< Matcher value. This value is used as the mask or as a key. */
415 /* Matcher structure. */
416 struct mlx5_flow_dv_matcher {
417 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
418 struct mlx5_flow_tbl_resource *tbl;
419 /**< Pointer to the table(group) the matcher associated with. */
420 void *matcher_object; /**< Pointer to DV matcher */
421 uint16_t crc; /**< CRC of key. */
422 uint16_t priority; /**< Priority of matcher. */
423 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
426 #define MLX5_ENCAP_MAX_LEN 132
428 /* Encap/decap resource structure. */
429 struct mlx5_flow_dv_encap_decap_resource {
430 struct mlx5_hlist_entry entry;
431 /* Pointer to next element. */
432 uint32_t refcnt; /**< Reference counter. */
434 /**< Encap/decap action object. */
435 uint8_t buf[MLX5_ENCAP_MAX_LEN];
437 uint8_t reformat_type;
439 uint64_t flags; /**< Flags for RDMA API. */
440 uint32_t idx; /**< Index for the index memory pool. */
443 /* Tag resource structure. */
444 struct mlx5_flow_dv_tag_resource {
445 struct mlx5_hlist_entry entry;
446 /**< hash list entry for tag resource, tag value as the key. */
448 /**< Tag action object. */
449 uint32_t refcnt; /**< Reference counter. */
450 uint32_t idx; /**< Index for the index memory pool. */
451 uint32_t tag_id; /**< Tag ID. */
455 * Number of modification commands.
456 * The maximal actions amount in FW is some constant, and it is 16 in the
457 * latest releases. In some old releases, it will be limited to 8.
458 * Since there is no interface to query the capacity, the maximal value should
459 * be used to allow PMD to create the flow. The validation will be done in the
460 * lower driver layer or FW. A failure will be returned if exceeds the maximal
461 * supported actions number on the root table.
462 * On non-root tables, there is no limitation, but 32 is enough right now.
464 #define MLX5_MAX_MODIFY_NUM 32
465 #define MLX5_ROOT_TBL_MODIFY_NUM 16
467 /* Modify resource structure */
468 struct mlx5_flow_dv_modify_hdr_resource {
469 struct mlx5_hlist_entry entry;
470 void *action; /**< Modify header action object. */
471 /* Key area for hash list matching: */
472 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
473 uint32_t actions_num; /**< Number of modification actions. */
474 uint64_t flags; /**< Flags for RDMA API. */
475 struct mlx5_modification_cmd actions[];
476 /**< Modification actions. */
479 /* Modify resource key of the hash organization. */
480 union mlx5_flow_modify_hdr_key {
482 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
483 uint32_t actions_num:5; /**< Number of modification actions. */
484 uint32_t group:19; /**< Flow group id. */
485 uint32_t cksum; /**< Actions check sum. */
487 uint64_t v64; /**< full 64bits value of key */
490 /* Jump action resource structure. */
491 struct mlx5_flow_dv_jump_tbl_resource {
492 void *action; /**< Pointer to the rdma core action. */
495 /* Port ID resource structure. */
496 struct mlx5_flow_dv_port_id_action_resource {
497 struct mlx5_cache_entry entry;
498 void *action; /**< Action object. */
499 uint32_t port_id; /**< Port ID value. */
500 uint32_t idx; /**< Indexed pool memory index. */
503 /* Push VLAN action resource structure */
504 struct mlx5_flow_dv_push_vlan_action_resource {
505 struct mlx5_cache_entry entry; /* Cache entry. */
506 void *action; /**< Action object. */
507 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
508 rte_be32_t vlan_tag; /**< VLAN tag value. */
509 uint32_t idx; /**< Indexed pool memory index. */
512 /* Metadata register copy table entry. */
513 struct mlx5_flow_mreg_copy_resource {
515 * Hash list entry for copy table.
516 * - Key is 32/64-bit MARK action ID.
517 * - MUST be the first entry.
519 struct mlx5_hlist_entry hlist_ent;
520 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
521 /* List entry for device flows. */
523 uint32_t rix_flow; /* Built flow for copy. */
527 /* Table tunnel parameter. */
528 struct mlx5_flow_tbl_tunnel_prm {
529 const struct mlx5_flow_tunnel *tunnel;
534 /* Table data structure of the hash organization. */
535 struct mlx5_flow_tbl_data_entry {
536 struct mlx5_hlist_entry entry;
537 /**< hash list entry, 64-bits key inside. */
538 struct mlx5_flow_tbl_resource tbl;
539 /**< flow table resource. */
540 struct mlx5_cache_list matchers;
541 /**< matchers' header associated with the flow table. */
542 struct mlx5_flow_dv_jump_tbl_resource jump;
543 /**< jump resource, at most one for each table created. */
544 uint32_t idx; /**< index for the indexed mempool. */
545 /**< tunnel offload */
546 const struct mlx5_flow_tunnel *tunnel;
549 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
550 uint32_t is_egress:1; /**< Egress table. */
551 uint32_t is_transfer:1; /**< Transfer table. */
552 uint32_t dummy:1; /**< DR table. */
553 uint32_t reserve:27; /**< Reserved to future using. */
554 uint32_t table_id; /**< Table ID. */
557 /* Sub rdma-core actions list. */
558 struct mlx5_flow_sub_actions_list {
559 uint32_t actions_num; /**< Number of sample actions. */
560 uint64_t action_flags;
561 void *dr_queue_action;
564 void *dr_port_id_action;
565 void *dr_encap_action;
568 /* Sample sub-actions resource list. */
569 struct mlx5_flow_sub_actions_idx {
570 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
571 uint32_t rix_tag; /**< Index to the tag action. */
573 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
574 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
577 /* Sample action resource structure. */
578 struct mlx5_flow_dv_sample_resource {
579 struct mlx5_cache_entry entry; /**< Cache entry. */
581 void *verbs_action; /**< Verbs sample action object. */
582 void **sub_actions; /**< Sample sub-action array. */
584 struct rte_eth_dev *dev; /**< Device registers the action. */
585 uint32_t idx; /** Sample object index. */
586 uint8_t ft_type; /** Flow Table Type */
587 uint32_t ft_id; /** Flow Table Level */
588 uint32_t ratio; /** Sample Ratio */
589 uint64_t set_action; /** Restore reg_c0 value */
590 void *normal_path_tbl; /** Flow Table pointer */
591 void *default_miss; /** default_miss dr_action. */
592 struct mlx5_flow_sub_actions_idx sample_idx;
593 /**< Action index resources. */
594 struct mlx5_flow_sub_actions_list sample_act;
595 /**< Action resources. */
598 #define MLX5_MAX_DEST_NUM 2
600 /* Destination array action resource structure. */
601 struct mlx5_flow_dv_dest_array_resource {
602 struct mlx5_cache_entry entry; /**< Cache entry. */
603 uint32_t idx; /** Destination array action object index. */
604 uint8_t ft_type; /** Flow Table Type */
605 uint8_t num_of_dest; /**< Number of destination actions. */
606 struct rte_eth_dev *dev; /**< Device registers the action. */
607 void *action; /**< Pointer to the rdma core action. */
608 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
609 /**< Action index resources. */
610 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
611 /**< Action resources. */
614 /* PMD flow priority for tunnel */
615 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
616 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
619 /** Device flow handle structure for DV mode only. */
620 struct mlx5_flow_handle_dv {
622 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
623 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
624 /**< Pointer to modify header resource in cache. */
625 uint32_t rix_encap_decap;
626 /**< Index to encap/decap resource in cache. */
627 uint32_t rix_push_vlan;
628 /**< Index to push VLAN action resource in cache. */
630 /**< Index to the tag action. */
632 /**< Index to sample action resource in cache. */
633 uint32_t rix_dest_array;
634 /**< Index to destination array resource in cache. */
637 /** Device flow handle structure: used both for creating & destroying. */
638 struct mlx5_flow_handle {
639 SILIST_ENTRY(uint32_t)next;
640 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
641 /**< Index to next device flow handle. */
643 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
644 void *drv_flow; /**< pointer to driver flow object. */
645 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
646 uint32_t mark:1; /**< Metadate rxq mark flag. */
647 uint32_t fate_action:3; /**< Fate action type. */
649 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
650 uint32_t rix_jump; /**< Index to the jump action resource. */
651 uint32_t rix_port_id_action;
652 /**< Index to port ID action resource. */
654 /**< Generic value indicates the fate action. */
655 uint32_t rix_default_fate;
656 /**< Indicates default miss fate action. */
658 /**< Indicates shared RSS fate action. */
660 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
661 struct mlx5_flow_handle_dv dvh;
666 * Size for Verbs device flow handle structure only. Do not use the DV only
667 * structure in Verbs. No DV flows attributes will be accessed.
668 * Macro offsetof() could also be used here.
670 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
671 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
672 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
674 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
678 * Max number of actions per DV flow.
679 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
680 * in rdma-core file providers/mlx5/verbs.c.
682 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
684 /** Device flow structure only for DV flow creation. */
685 struct mlx5_flow_dv_workspace {
686 uint32_t group; /**< The group index. */
687 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
688 int actions_n; /**< number of actions. */
689 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
690 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
691 /**< Pointer to encap/decap resource in cache. */
692 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
693 /**< Pointer to push VLAN action resource in cache. */
694 struct mlx5_flow_dv_tag_resource *tag_resource;
695 /**< pointer to the tag action. */
696 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
697 /**< Pointer to port ID action resource. */
698 struct mlx5_flow_dv_jump_tbl_resource *jump;
699 /**< Pointer to the jump action resource. */
700 struct mlx5_flow_dv_match_params value;
701 /**< Holds the value that the packet is compared to. */
702 struct mlx5_flow_dv_sample_resource *sample_res;
703 /**< Pointer to the sample action resource. */
704 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
705 /**< Pointer to the destination array resource. */
708 #ifdef HAVE_INFINIBAND_VERBS_H
710 * Maximal Verbs flow specifications & actions size.
711 * Some elements are mutually exclusive, but enough space should be allocated.
712 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
713 * 2. One tunnel header (exception: GRE + MPLS),
714 * SPEC length: GRE == tunnel.
715 * Actions: 1. 1 Mark OR Flag.
716 * 2. 1 Drop (if any).
717 * 3. No limitation for counters, but it makes no sense to support too
718 * many counters in a single device flow.
720 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
721 #define MLX5_VERBS_MAX_SPEC_SIZE \
723 (2 * (sizeof(struct ibv_flow_spec_eth) + \
724 sizeof(struct ibv_flow_spec_ipv6) + \
725 sizeof(struct ibv_flow_spec_tcp_udp)) + \
726 sizeof(struct ibv_flow_spec_gre) + \
727 sizeof(struct ibv_flow_spec_mpls)) \
730 #define MLX5_VERBS_MAX_SPEC_SIZE \
732 (2 * (sizeof(struct ibv_flow_spec_eth) + \
733 sizeof(struct ibv_flow_spec_ipv6) + \
734 sizeof(struct ibv_flow_spec_tcp_udp)) + \
735 sizeof(struct ibv_flow_spec_tunnel)) \
739 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
740 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
741 #define MLX5_VERBS_MAX_ACT_SIZE \
743 sizeof(struct ibv_flow_spec_action_tag) + \
744 sizeof(struct ibv_flow_spec_action_drop) + \
745 sizeof(struct ibv_flow_spec_counter_action) * 4 \
748 #define MLX5_VERBS_MAX_ACT_SIZE \
750 sizeof(struct ibv_flow_spec_action_tag) + \
751 sizeof(struct ibv_flow_spec_action_drop) \
755 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
756 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
758 /** Device flow structure only for Verbs flow creation. */
759 struct mlx5_flow_verbs_workspace {
760 unsigned int size; /**< Size of the attribute. */
761 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
762 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
763 /**< Specifications & actions buffer of verbs flow. */
765 #endif /* HAVE_INFINIBAND_VERBS_H */
767 /** Maximal number of device sub-flows supported. */
768 #define MLX5_NUM_MAX_DEV_FLOWS 32
770 /** Device flow structure. */
773 struct rte_flow *flow; /**< Pointer to the main flow. */
774 uint32_t flow_idx; /**< The memory pool index to the main flow. */
775 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
777 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
778 bool external; /**< true if the flow is created external to PMD. */
779 uint8_t ingress:1; /**< 1 if the flow is ingress. */
780 uint8_t skip_scale:1;
781 /**< 1 if skip the scale the table with factor. */
783 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
784 struct mlx5_flow_dv_workspace dv;
786 #ifdef HAVE_INFINIBAND_VERBS_H
787 struct mlx5_flow_verbs_workspace verbs;
790 struct mlx5_flow_handle *handle;
791 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
792 const struct mlx5_flow_tunnel *tunnel;
795 /* Flow meter state. */
796 #define MLX5_FLOW_METER_DISABLE 0
797 #define MLX5_FLOW_METER_ENABLE 1
799 #define MLX5_MAN_WIDTH 8
800 /* Modify this value if enum rte_mtr_color changes. */
801 #define RTE_MTR_DROPPED RTE_COLORS
803 /* Meter policer statistics */
804 struct mlx5_flow_policer_stats {
805 uint32_t cnt[RTE_COLORS + 1];
806 /**< Color counter, extra for drop. */
808 /**< Statistics mask for the colors. */
811 /* Meter table structure. */
812 struct mlx5_meter_domain_info {
813 struct mlx5_flow_tbl_resource *tbl;
815 struct mlx5_flow_tbl_resource *sfx_tbl;
816 /**< Meter suffix table. */
818 /**< Meter color not match default criteria. */
820 /**< Meter color match criteria. */
822 /**< Meter match action. */
823 void *policer_rules[RTE_MTR_DROPPED + 1];
824 /**< Meter policer for the match. */
827 /* Meter table set for TX RX FDB. */
828 struct mlx5_meter_domains_infos {
830 /**< Table user count. */
831 struct mlx5_meter_domain_info egress;
832 /**< TX meter table. */
833 struct mlx5_meter_domain_info ingress;
834 /**< RX meter table. */
835 struct mlx5_meter_domain_info transfer;
836 /**< FDB meter table. */
838 /**< Drop action as not matched. */
839 void *count_actns[RTE_MTR_DROPPED + 1];
840 /**< Counters for match and unmatched statistics. */
841 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
842 /**< Flow meter parameter. */
844 /**< Flow meter parameter size. */
846 /**< Flow meter action. */
849 /* Meter parameter structure. */
850 struct mlx5_flow_meter {
851 TAILQ_ENTRY(mlx5_flow_meter) next;
852 /**< Pointer to the next flow meter structure. */
853 uint32_t idx; /* Index to meter object. */
856 struct mlx5_flow_meter_profile *profile;
857 /**< Meter profile parameters. */
859 rte_spinlock_t sl; /**< Meter action spinlock. */
861 /** Policer actions (per meter output color). */
862 enum rte_mtr_policer_action action[RTE_COLORS];
864 /** Set of stats counters to be enabled.
865 * @see enum rte_mtr_stats_type
869 /**< Rule applies to ingress traffic. */
872 /**< Rule applies to egress traffic. */
875 * Instead of simply matching the properties of traffic as it would
876 * appear on a given DPDK port ID, enabling this attribute transfers
877 * a flow rule to the lowest possible level of any device endpoints
878 * found in the pattern.
880 * When supported, this effectively enables an application to
881 * re-route traffic not necessarily intended for it (e.g. coming
882 * from or addressed to different physical ports, VFs or
883 * applications) at the device level.
885 * It complements the behavior of some pattern items such as
886 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
888 * When transferring flow rules, ingress and egress attributes keep
889 * their original meaning, as if processing traffic emitted or
890 * received by the application.
893 struct mlx5_meter_domains_infos *mfts;
894 /**< Flow table created for this meter. */
895 struct mlx5_flow_policer_stats policer_stats;
896 /**< Meter policer statistics. */
899 uint32_t active_state:1;
902 /**< Meter shared or not. */
905 /* RFC2697 parameter structure. */
906 struct mlx5_flow_meter_srtcm_rfc2697_prm {
907 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
908 uint32_t cbs_exponent:5;
909 uint32_t cbs_mantissa:8;
910 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
911 uint32_t cir_exponent:5;
912 uint32_t cir_mantissa:8;
913 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
914 uint32_t ebs_exponent:5;
915 uint32_t ebs_mantissa:8;
918 /* Flow meter profile structure. */
919 struct mlx5_flow_meter_profile {
920 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
921 /**< Pointer to the next flow meter structure. */
922 uint32_t meter_profile_id; /**< Profile id. */
923 struct rte_mtr_meter_profile profile; /**< Profile detail. */
925 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
926 /**< srtcm_rfc2697 struct. */
928 uint32_t ref_cnt; /**< Use count. */
931 #define MLX5_MAX_TUNNELS 256
932 #define MLX5_TNL_MISS_RULE_PRIORITY 3
933 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
936 * When tunnel offload is active, all JUMP group ids are converted
937 * using the same method. That conversion is applied both to tunnel and
938 * regular rule types.
939 * Group ids used in tunnel rules are relative to it's tunnel (!).
940 * Application can create number of steer rules, using the same
941 * tunnel, with different group id in each rule.
942 * Each tunnel stores its groups internally in PMD tunnel object.
943 * Groups used in regular rules do not belong to any tunnel and are stored
947 struct mlx5_flow_tunnel {
948 LIST_ENTRY(mlx5_flow_tunnel) chain;
949 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
950 uint32_t tunnel_id; /** unique tunnel ID */
952 struct rte_flow_action action;
953 struct rte_flow_item item;
954 struct mlx5_hlist *groups; /** tunnel groups */
957 /** PMD tunnel related context */
958 struct mlx5_flow_tunnel_hub {
960 * Access to the list MUST be MT protected
962 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
963 /* protect access to the tunnels list */
965 struct mlx5_hlist *groups; /** non tunnel groups */
968 /* convert jump group to flow table ID in tunnel rules */
969 struct tunnel_tbl_entry {
970 struct mlx5_hlist_entry hash;
976 static inline uint32_t
977 tunnel_id_to_flow_tbl(uint32_t id)
979 return id | (1u << 16);
982 static inline uint32_t
983 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
985 return flow_tbl & ~(1u << 16);
988 union tunnel_tbl_key {
996 static inline struct mlx5_flow_tunnel_hub *
997 mlx5_tunnel_hub(struct rte_eth_dev *dev)
999 struct mlx5_priv *priv = dev->data->dev_private;
1000 return priv->sh->tunnel_hub;
1004 is_tunnel_offload_active(struct rte_eth_dev *dev)
1006 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1007 struct mlx5_priv *priv = dev->data->dev_private;
1008 return !!priv->config.dv_miss_info;
1016 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
1017 __rte_unused const struct rte_flow_attr *attr,
1018 __rte_unused const struct rte_flow_item items[],
1019 __rte_unused const struct rte_flow_action actions[])
1021 return (items[0].type == (typeof(items[0].type))
1022 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1026 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1027 __rte_unused const struct rte_flow_attr *attr,
1028 __rte_unused const struct rte_flow_item items[],
1029 __rte_unused const struct rte_flow_action actions[])
1031 return (actions[0].type == (typeof(actions[0].type))
1032 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1035 static inline const struct mlx5_flow_tunnel *
1036 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1038 return actions[0].conf;
1041 static inline const struct mlx5_flow_tunnel *
1042 flow_items_to_tunnel(const struct rte_flow_item items[])
1044 return items[0].spec;
1047 /* Flow structure. */
1049 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1050 uint32_t dev_handles;
1051 /**< Device flow handles that are part of the flow. */
1052 uint32_t drv_type:2; /**< Driver type. */
1054 uint32_t meter:16; /**< Holds flow meter id. */
1055 uint32_t rix_mreg_copy;
1056 /**< Index to metadata register copy table resource. */
1057 uint32_t counter; /**< Holds flow counter. */
1058 uint32_t tunnel_id; /**< Tunnel id */
1059 uint32_t age; /**< Holds ASO age bit index. */
1063 * Define list of valid combinations of RX Hash fields
1064 * (see enum ibv_rx_hash_fields).
1066 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1067 #define MLX5_RSS_HASH_IPV4_TCP \
1068 (MLX5_RSS_HASH_IPV4 | \
1069 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1070 #define MLX5_RSS_HASH_IPV4_UDP \
1071 (MLX5_RSS_HASH_IPV4 | \
1072 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1073 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1074 #define MLX5_RSS_HASH_IPV6_TCP \
1075 (MLX5_RSS_HASH_IPV6 | \
1076 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1077 #define MLX5_RSS_HASH_IPV6_UDP \
1078 (MLX5_RSS_HASH_IPV6 | \
1079 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1080 #define MLX5_RSS_HASH_NONE 0ULL
1082 /* array of valid combinations of RX Hash fields for RSS */
1083 static const uint64_t mlx5_rss_hash_fields[] = {
1085 MLX5_RSS_HASH_IPV4_TCP,
1086 MLX5_RSS_HASH_IPV4_UDP,
1088 MLX5_RSS_HASH_IPV6_TCP,
1089 MLX5_RSS_HASH_IPV6_UDP,
1093 /* Shared RSS action structure */
1094 struct mlx5_shared_action_rss {
1095 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1096 uint32_t refcnt; /**< Atomically accessed refcnt. */
1097 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1098 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1099 struct mlx5_ind_table_obj *ind_tbl;
1100 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1101 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1102 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1103 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
1104 /**< Hash RX queue indexes for tunneled RSS */
1105 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1108 struct rte_flow_shared_action {
1112 /* Thread specific flow workspace intermediate data. */
1113 struct mlx5_flow_workspace {
1114 /* If creating another flow in same thread, push new as stack. */
1115 struct mlx5_flow_workspace *prev;
1116 struct mlx5_flow_workspace *next;
1117 uint32_t inuse; /* can't create new flow with current. */
1118 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1119 struct mlx5_flow_rss_desc rss_desc;
1120 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1121 uint32_t flow_idx; /* Intermediate device flow index. */
1124 struct mlx5_flow_split_info {
1126 /**< True if flow is created by request external to PMD. */
1127 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1128 uint32_t flow_idx; /**< This memory pool index to the flow. */
1129 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1130 uint64_t prefix_layers; /**< Prefix subflow layers. */
1133 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1134 const struct rte_flow_attr *attr,
1135 const struct rte_flow_item items[],
1136 const struct rte_flow_action actions[],
1139 struct rte_flow_error *error);
1140 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1141 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1142 const struct rte_flow_item items[],
1143 const struct rte_flow_action actions[], struct rte_flow_error *error);
1144 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1145 struct mlx5_flow *dev_flow,
1146 const struct rte_flow_attr *attr,
1147 const struct rte_flow_item items[],
1148 const struct rte_flow_action actions[],
1149 struct rte_flow_error *error);
1150 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1151 struct rte_flow_error *error);
1152 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1153 struct rte_flow *flow);
1154 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1155 struct rte_flow *flow);
1156 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1157 struct rte_flow *flow,
1158 const struct rte_flow_action *actions,
1160 struct rte_flow_error *error);
1161 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1162 (struct rte_eth_dev *dev,
1163 const struct mlx5_flow_meter *fm);
1164 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1165 struct mlx5_meter_domains_infos *tbls);
1166 typedef int (*mlx5_flow_create_policer_rules_t)
1167 (struct rte_eth_dev *dev,
1168 struct mlx5_flow_meter *fm,
1169 const struct rte_flow_attr *attr);
1170 typedef int (*mlx5_flow_destroy_policer_rules_t)
1171 (struct rte_eth_dev *dev,
1172 const struct mlx5_flow_meter *fm,
1173 const struct rte_flow_attr *attr);
1174 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1175 (struct rte_eth_dev *dev);
1176 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1178 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1180 bool clear, uint64_t *pkts,
1182 typedef int (*mlx5_flow_get_aged_flows_t)
1183 (struct rte_eth_dev *dev,
1185 uint32_t nb_contexts,
1186 struct rte_flow_error *error);
1187 typedef int (*mlx5_flow_action_validate_t)
1188 (struct rte_eth_dev *dev,
1189 const struct rte_flow_shared_action_conf *conf,
1190 const struct rte_flow_action *action,
1191 struct rte_flow_error *error);
1192 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1193 (struct rte_eth_dev *dev,
1194 const struct rte_flow_shared_action_conf *conf,
1195 const struct rte_flow_action *action,
1196 struct rte_flow_error *error);
1197 typedef int (*mlx5_flow_action_destroy_t)
1198 (struct rte_eth_dev *dev,
1199 struct rte_flow_shared_action *action,
1200 struct rte_flow_error *error);
1201 typedef int (*mlx5_flow_action_update_t)
1202 (struct rte_eth_dev *dev,
1203 struct rte_flow_shared_action *action,
1204 const void *action_conf,
1205 struct rte_flow_error *error);
1206 typedef int (*mlx5_flow_action_query_t)
1207 (struct rte_eth_dev *dev,
1208 const struct rte_flow_shared_action *action,
1210 struct rte_flow_error *error);
1211 typedef int (*mlx5_flow_sync_domain_t)
1212 (struct rte_eth_dev *dev,
1216 struct mlx5_flow_driver_ops {
1217 mlx5_flow_validate_t validate;
1218 mlx5_flow_prepare_t prepare;
1219 mlx5_flow_translate_t translate;
1220 mlx5_flow_apply_t apply;
1221 mlx5_flow_remove_t remove;
1222 mlx5_flow_destroy_t destroy;
1223 mlx5_flow_query_t query;
1224 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1225 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1226 mlx5_flow_create_policer_rules_t create_policer_rules;
1227 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1228 mlx5_flow_counter_alloc_t counter_alloc;
1229 mlx5_flow_counter_free_t counter_free;
1230 mlx5_flow_counter_query_t counter_query;
1231 mlx5_flow_get_aged_flows_t get_aged_flows;
1232 mlx5_flow_action_validate_t action_validate;
1233 mlx5_flow_action_create_t action_create;
1234 mlx5_flow_action_destroy_t action_destroy;
1235 mlx5_flow_action_update_t action_update;
1236 mlx5_flow_action_query_t action_query;
1237 mlx5_flow_sync_domain_t sync_domain;
1242 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1244 struct flow_grp_info {
1245 uint64_t external:1;
1246 uint64_t transfer:1;
1247 uint64_t fdb_def_rule:1;
1248 /* force standard group translation */
1249 uint64_t std_tbl_fix:1;
1250 uint64_t skip_scale:1;
1254 tunnel_use_standard_attr_group_translate
1255 (struct rte_eth_dev *dev,
1256 const struct mlx5_flow_tunnel *tunnel,
1257 const struct rte_flow_attr *attr,
1258 const struct rte_flow_item items[],
1259 const struct rte_flow_action actions[])
1263 if (!is_tunnel_offload_active(dev))
1264 /* no tunnel offload API */
1268 * OvS will use jump to group 0 in tunnel steer rule.
1269 * If tunnel steer rule starts from group 0 (attr.group == 0)
1270 * that 0 group must be translated with standard method.
1271 * attr.group == 0 in tunnel match rule translated with tunnel
1274 verdict = !attr->group &&
1275 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1278 * non-tunnel group translation uses standard method for
1279 * root group only: attr.group == 0
1281 verdict = !attr->group;
1287 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1288 const struct mlx5_flow_tunnel *tunnel,
1289 uint32_t group, uint32_t *table,
1290 const struct flow_grp_info *flags,
1291 struct rte_flow_error *error);
1292 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1293 int tunnel, uint64_t layer_types,
1294 uint64_t hash_fields);
1295 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1296 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1297 uint32_t subpriority);
1298 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1299 enum mlx5_feature_name feature,
1301 struct rte_flow_error *error);
1302 const struct rte_flow_action *mlx5_flow_find_action
1303 (const struct rte_flow_action *actions,
1304 enum rte_flow_action_type action);
1305 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1306 const struct rte_flow_action *action,
1307 struct rte_flow_error *error);
1308 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1309 const struct rte_flow_attr *attr,
1310 struct rte_flow_error *error);
1311 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1312 const struct rte_flow_attr *attr,
1313 struct rte_flow_error *error);
1314 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1315 const struct rte_flow_attr *attr,
1316 struct rte_flow_error *error);
1317 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1318 uint64_t action_flags,
1319 const struct rte_flow_attr *attr,
1320 struct rte_flow_error *error);
1321 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1322 uint64_t action_flags,
1323 struct rte_eth_dev *dev,
1324 const struct rte_flow_attr *attr,
1325 struct rte_flow_error *error);
1326 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1327 uint64_t action_flags,
1328 struct rte_eth_dev *dev,
1329 const struct rte_flow_attr *attr,
1330 uint64_t item_flags,
1331 struct rte_flow_error *error);
1332 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1333 const struct rte_flow_attr *attr,
1334 struct rte_flow_error *error);
1335 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1336 const struct rte_flow_attr *attributes,
1337 struct rte_flow_error *error);
1338 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1339 const uint8_t *mask,
1340 const uint8_t *nic_mask,
1342 bool range_accepted,
1343 struct rte_flow_error *error);
1344 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1345 uint64_t item_flags, bool ext_vlan_sup,
1346 struct rte_flow_error *error);
1347 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1348 uint64_t item_flags,
1349 uint8_t target_protocol,
1350 struct rte_flow_error *error);
1351 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1352 uint64_t item_flags,
1353 const struct rte_flow_item *gre_item,
1354 struct rte_flow_error *error);
1355 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1356 uint64_t item_flags,
1358 uint16_t ether_type,
1359 const struct rte_flow_item_ipv4 *acc_mask,
1360 bool range_accepted,
1361 struct rte_flow_error *error);
1362 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1363 uint64_t item_flags,
1365 uint16_t ether_type,
1366 const struct rte_flow_item_ipv6 *acc_mask,
1367 struct rte_flow_error *error);
1368 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1369 const struct rte_flow_item *item,
1370 uint64_t item_flags,
1371 uint64_t prev_layer,
1372 struct rte_flow_error *error);
1373 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1374 uint64_t item_flags,
1375 uint8_t target_protocol,
1376 const struct rte_flow_item_tcp *flow_mask,
1377 struct rte_flow_error *error);
1378 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1379 uint64_t item_flags,
1380 uint8_t target_protocol,
1381 struct rte_flow_error *error);
1382 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1383 uint64_t item_flags,
1384 struct rte_eth_dev *dev,
1385 struct rte_flow_error *error);
1386 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1387 uint64_t item_flags,
1388 struct rte_flow_error *error);
1389 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1390 uint64_t item_flags,
1391 struct rte_eth_dev *dev,
1392 struct rte_flow_error *error);
1393 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1394 uint64_t item_flags,
1395 uint8_t target_protocol,
1396 struct rte_flow_error *error);
1397 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1398 uint64_t item_flags,
1399 uint8_t target_protocol,
1400 struct rte_flow_error *error);
1401 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1402 uint64_t item_flags,
1403 uint8_t target_protocol,
1404 struct rte_flow_error *error);
1405 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1406 uint64_t item_flags,
1407 struct rte_eth_dev *dev,
1408 struct rte_flow_error *error);
1409 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1410 uint64_t item_flags,
1412 uint16_t ether_type,
1413 const struct rte_flow_item_ecpri *acc_mask,
1414 struct rte_flow_error *error);
1415 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1416 (struct rte_eth_dev *dev,
1417 const struct mlx5_flow_meter *fm);
1418 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1419 struct mlx5_meter_domains_infos *tbl);
1420 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1421 struct mlx5_flow_meter *fm,
1422 const struct rte_flow_attr *attr);
1423 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1424 struct mlx5_flow_meter *fm,
1425 const struct rte_flow_attr *attr);
1426 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1427 struct rte_mtr_error *error);
1428 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1429 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1430 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1431 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1433 /* Hash list callbacks for flow tables: */
1434 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1435 uint64_t key, void *entry_ctx);
1436 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1437 struct mlx5_hlist_entry *entry, uint64_t key,
1439 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1440 struct mlx5_hlist_entry *entry);
1441 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1442 uint32_t table_id, uint8_t egress, uint8_t transfer,
1443 bool external, const struct mlx5_flow_tunnel *tunnel,
1444 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error);
1446 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1447 uint64_t key, void *cb_ctx);
1448 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1449 struct mlx5_hlist_entry *entry, uint64_t key,
1451 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1452 struct mlx5_hlist_entry *entry);
1454 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1455 struct mlx5_hlist_entry *entry,
1456 uint64_t key, void *cb_ctx);
1457 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1458 uint64_t key, void *ctx);
1459 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1460 struct mlx5_hlist_entry *entry);
1462 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1463 uint64_t key, void *ctx);
1464 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1465 struct mlx5_hlist_entry *entry, uint64_t key,
1467 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1468 struct mlx5_hlist_entry *entry);
1470 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1471 struct mlx5_hlist_entry *entry,
1472 uint64_t key, void *cb_ctx);
1473 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1474 uint64_t key, void *cb_ctx);
1475 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1476 struct mlx5_hlist_entry *entry);
1478 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1479 struct mlx5_cache_entry *entry, void *ctx);
1480 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1481 struct mlx5_cache_entry *entry, void *ctx);
1482 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1483 struct mlx5_cache_entry *entry);
1485 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1486 struct mlx5_cache_entry *entry, void *cb_ctx);
1487 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1488 struct mlx5_cache_entry *entry, void *cb_ctx);
1489 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1490 struct mlx5_cache_entry *entry);
1492 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1493 struct mlx5_cache_entry *entry, void *cb_ctx);
1494 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1495 (struct mlx5_cache_list *list,
1496 struct mlx5_cache_entry *entry, void *cb_ctx);
1497 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1498 struct mlx5_cache_entry *entry);
1500 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1501 struct mlx5_cache_entry *entry, void *cb_ctx);
1502 struct mlx5_cache_entry *flow_dv_sample_create_cb
1503 (struct mlx5_cache_list *list,
1504 struct mlx5_cache_entry *entry, void *cb_ctx);
1505 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1506 struct mlx5_cache_entry *entry);
1508 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1509 struct mlx5_cache_entry *entry, void *cb_ctx);
1510 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1511 (struct mlx5_cache_list *list,
1512 struct mlx5_cache_entry *entry, void *cb_ctx);
1513 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1514 struct mlx5_cache_entry *entry);
1515 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1518 void flow_release_workspace(void *data);
1519 int mlx5_flow_os_init_workspace_once(void);
1520 void *mlx5_flow_os_get_specific_workspace(void);
1521 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1522 void mlx5_flow_os_release_workspace(void);
1524 #endif /* RTE_PMD_MLX5_FLOW_H_ */