1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_atomic.h>
15 #include <rte_alarm.h>
18 #include <mlx5_glue.h>
23 /* Private rte flow items. */
24 enum mlx5_rte_flow_item_type {
25 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
26 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
27 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
28 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 /* Matches on selected register. */
41 struct mlx5_rte_flow_item_tag {
46 /* Modify selected register. */
47 struct mlx5_rte_flow_action_set_tag {
52 struct mlx5_flow_action_copy_mreg {
57 /* Matches on source queue. */
58 struct mlx5_rte_flow_item_tx_queue {
62 /* Feature name to allocate metadata register. */
63 enum mlx5_feature_name {
76 /* Pattern outer Layer bits. */
77 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
78 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
79 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
80 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
81 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
82 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
84 /* Pattern inner Layer bits. */
85 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
86 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
87 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
88 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
89 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
90 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
92 /* Pattern tunnel Layer bits. */
93 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
94 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
95 #define MLX5_FLOW_LAYER_GRE (1u << 14)
96 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
97 /* List of tunnel Layer bits continued below. */
99 /* General pattern items bits. */
100 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
101 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
102 #define MLX5_FLOW_ITEM_TAG (1u << 18)
103 #define MLX5_FLOW_ITEM_MARK (1u << 19)
105 /* Pattern MISC bits. */
106 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
107 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
108 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
110 /* Pattern tunnel Layer bits (continued). */
111 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
112 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
113 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
114 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
117 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
119 /* Pattern tunnel Layer bits (continued). */
120 #define MLX5_FLOW_LAYER_GTP (1u << 28)
122 /* Pattern eCPRI Layer bit. */
123 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
125 /* IPv6 Fragment Extension Header bit. */
126 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
127 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
130 #define MLX5_FLOW_LAYER_OUTER_L3 \
131 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
132 #define MLX5_FLOW_LAYER_OUTER_L4 \
133 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
134 #define MLX5_FLOW_LAYER_OUTER \
135 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
136 MLX5_FLOW_LAYER_OUTER_L4)
139 #define MLX5_FLOW_LAYER_TUNNEL \
140 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
141 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
142 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
143 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
146 #define MLX5_FLOW_LAYER_INNER_L3 \
147 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
148 #define MLX5_FLOW_LAYER_INNER_L4 \
149 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
150 #define MLX5_FLOW_LAYER_INNER \
151 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
152 MLX5_FLOW_LAYER_INNER_L4)
155 #define MLX5_FLOW_LAYER_L2 \
156 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
157 #define MLX5_FLOW_LAYER_L3_IPV4 \
158 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
159 #define MLX5_FLOW_LAYER_L3_IPV6 \
160 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
161 #define MLX5_FLOW_LAYER_L3 \
162 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
163 #define MLX5_FLOW_LAYER_L4 \
164 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
167 #define MLX5_FLOW_ACTION_DROP (1u << 0)
168 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
169 #define MLX5_FLOW_ACTION_RSS (1u << 2)
170 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
171 #define MLX5_FLOW_ACTION_MARK (1u << 4)
172 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
173 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
174 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
175 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
176 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
177 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
178 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
179 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
180 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
181 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
182 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
183 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
184 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
185 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
186 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
187 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
188 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
189 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
190 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
191 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
192 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
193 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
194 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
195 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
196 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
197 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
198 #define MLX5_FLOW_ACTION_METER (1ull << 31)
199 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
200 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
201 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
202 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
203 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
205 #define MLX5_FLOW_FATE_ACTIONS \
206 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
207 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
208 MLX5_FLOW_ACTION_DEFAULT_MISS)
210 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
211 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
212 MLX5_FLOW_ACTION_JUMP)
215 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
216 MLX5_FLOW_ACTION_SET_IPV4_DST | \
217 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
218 MLX5_FLOW_ACTION_SET_IPV6_DST | \
219 MLX5_FLOW_ACTION_SET_TP_SRC | \
220 MLX5_FLOW_ACTION_SET_TP_DST | \
221 MLX5_FLOW_ACTION_SET_TTL | \
222 MLX5_FLOW_ACTION_DEC_TTL | \
223 MLX5_FLOW_ACTION_SET_MAC_SRC | \
224 MLX5_FLOW_ACTION_SET_MAC_DST | \
225 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
226 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
227 MLX5_FLOW_ACTION_INC_TCP_ACK | \
228 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
229 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
230 MLX5_FLOW_ACTION_SET_TAG | \
231 MLX5_FLOW_ACTION_MARK_EXT | \
232 MLX5_FLOW_ACTION_SET_META | \
233 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
234 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
236 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
237 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
239 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
242 #define IPPROTO_MPLS 137
245 /* UDP port number for MPLS */
246 #define MLX5_UDP_PORT_MPLS 6635
248 /* UDP port numbers for VxLAN. */
249 #define MLX5_UDP_PORT_VXLAN 4789
250 #define MLX5_UDP_PORT_VXLAN_GPE 4790
252 /* UDP port numbers for GENEVE. */
253 #define MLX5_UDP_PORT_GENEVE 6081
255 /* Priority reserved for default flows. */
256 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
259 * Number of sub priorities.
260 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
261 * matching on the NIC (firmware dependent) L4 most have the higher priority
262 * followed by L3 and ending with L2.
264 #define MLX5_PRIORITY_MAP_L2 2
265 #define MLX5_PRIORITY_MAP_L3 1
266 #define MLX5_PRIORITY_MAP_L4 0
267 #define MLX5_PRIORITY_MAP_MAX 3
269 /* Valid layer type for IPV4 RSS. */
270 #define MLX5_IPV4_LAYER_TYPES \
271 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
272 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
273 ETH_RSS_NONFRAG_IPV4_OTHER)
275 /* IBV hash source bits for IPV4. */
276 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
278 /* Valid layer type for IPV6 RSS. */
279 #define MLX5_IPV6_LAYER_TYPES \
280 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
281 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
282 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
284 /* IBV hash source bits for IPV6. */
285 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
287 /* IBV hash bits for L3 SRC. */
288 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
290 /* IBV hash bits for L3 DST. */
291 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
293 /* IBV hash bits for TCP. */
294 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
295 IBV_RX_HASH_DST_PORT_TCP)
297 /* IBV hash bits for UDP. */
298 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
299 IBV_RX_HASH_DST_PORT_UDP)
301 /* IBV hash bits for L4 SRC. */
302 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
303 IBV_RX_HASH_SRC_PORT_UDP)
305 /* IBV hash bits for L4 DST. */
306 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
307 IBV_RX_HASH_DST_PORT_UDP)
309 /* Geneve header first 16Bit */
310 #define MLX5_GENEVE_VER_MASK 0x3
311 #define MLX5_GENEVE_VER_SHIFT 14
312 #define MLX5_GENEVE_VER_VAL(a) \
313 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
314 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
315 #define MLX5_GENEVE_OPTLEN_SHIFT 7
316 #define MLX5_GENEVE_OPTLEN_VAL(a) \
317 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
318 #define MLX5_GENEVE_OAMF_MASK 0x1
319 #define MLX5_GENEVE_OAMF_SHIFT 7
320 #define MLX5_GENEVE_OAMF_VAL(a) \
321 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
322 #define MLX5_GENEVE_CRITO_MASK 0x1
323 #define MLX5_GENEVE_CRITO_SHIFT 6
324 #define MLX5_GENEVE_CRITO_VAL(a) \
325 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
326 #define MLX5_GENEVE_RSVD_MASK 0x3F
327 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
329 * The length of the Geneve options fields, expressed in four byte multiples,
330 * not including the eight byte fixed tunnel.
332 #define MLX5_GENEVE_OPT_LEN_0 14
333 #define MLX5_GENEVE_OPT_LEN_1 63
335 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
336 sizeof(struct rte_flow_item_ipv4))
338 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
339 #define MLX5_IPV4_FRAG_OFFSET_MASK \
340 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
342 /* Specific item's fields can accept a range of values (using spec and last). */
343 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
344 #define MLX5_ITEM_RANGE_ACCEPTED true
346 /* Software header modify action numbers of a flow. */
347 #define MLX5_ACT_NUM_MDF_IPV4 1
348 #define MLX5_ACT_NUM_MDF_IPV6 4
349 #define MLX5_ACT_NUM_MDF_MAC 2
350 #define MLX5_ACT_NUM_MDF_VID 1
351 #define MLX5_ACT_NUM_MDF_PORT 2
352 #define MLX5_ACT_NUM_MDF_TTL 1
353 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
354 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
355 #define MLX5_ACT_NUM_MDF_TCPACK 1
356 #define MLX5_ACT_NUM_SET_REG 1
357 #define MLX5_ACT_NUM_SET_TAG 1
358 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
359 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
360 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
361 #define MLX5_ACT_NUM_SET_DSCP 1
363 enum mlx5_flow_drv_type {
366 MLX5_FLOW_TYPE_VERBS,
370 /* Fate action type. */
371 enum mlx5_flow_fate_type {
372 MLX5_FLOW_FATE_NONE, /* Egress flow. */
373 MLX5_FLOW_FATE_QUEUE,
375 MLX5_FLOW_FATE_PORT_ID,
377 MLX5_FLOW_FATE_DEFAULT_MISS,
381 /* Matcher PRM representation */
382 struct mlx5_flow_dv_match_params {
384 /**< Size of match value. Do NOT split size and key! */
385 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
386 /**< Matcher value. This value is used as the mask or as a key. */
389 /* Matcher structure. */
390 struct mlx5_flow_dv_matcher {
391 LIST_ENTRY(mlx5_flow_dv_matcher) next;
392 /**< Pointer to the next element. */
393 struct mlx5_flow_tbl_resource *tbl;
394 /**< Pointer to the table(group) the matcher associated with. */
395 rte_atomic32_t refcnt; /**< Reference counter. */
396 void *matcher_object; /**< Pointer to DV matcher */
397 uint16_t crc; /**< CRC of key. */
398 uint16_t priority; /**< Priority of matcher. */
399 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
402 #define MLX5_ENCAP_MAX_LEN 132
404 /* Encap/decap resource key of the hash organization. */
405 union mlx5_flow_encap_decap_key {
407 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
408 uint32_t refmt_type:8; /**< Header reformat type. */
409 uint32_t buf_size:8; /**< Encap buf size. */
410 uint32_t table_level:8; /**< Root table or not. */
411 uint32_t cksum; /**< Encap buf check sum. */
413 uint64_t v64; /**< full 64bits value of key */
416 /* Encap/decap resource structure. */
417 struct mlx5_flow_dv_encap_decap_resource {
418 struct mlx5_hlist_entry entry;
419 /* Pointer to next element. */
420 rte_atomic32_t refcnt; /**< Reference counter. */
422 /**< Encap/decap action object. */
423 uint8_t buf[MLX5_ENCAP_MAX_LEN];
425 uint8_t reformat_type;
427 uint64_t flags; /**< Flags for RDMA API. */
428 uint32_t idx; /**< Index for the index memory pool. */
431 /* Tag resource structure. */
432 struct mlx5_flow_dv_tag_resource {
433 struct mlx5_hlist_entry entry;
434 /**< hash list entry for tag resource, tag value as the key. */
436 /**< Tag action object. */
437 rte_atomic32_t refcnt; /**< Reference counter. */
438 uint32_t idx; /**< Index for the index memory pool. */
442 * Number of modification commands.
443 * The maximal actions amount in FW is some constant, and it is 16 in the
444 * latest releases. In some old releases, it will be limited to 8.
445 * Since there is no interface to query the capacity, the maximal value should
446 * be used to allow PMD to create the flow. The validation will be done in the
447 * lower driver layer or FW. A failure will be returned if exceeds the maximal
448 * supported actions number on the root table.
449 * On non-root tables, there is no limitation, but 32 is enough right now.
451 #define MLX5_MAX_MODIFY_NUM 32
452 #define MLX5_ROOT_TBL_MODIFY_NUM 16
454 /* Modify resource structure */
455 struct mlx5_flow_dv_modify_hdr_resource {
456 struct mlx5_hlist_entry entry;
457 /* Pointer to next element. */
458 rte_atomic32_t refcnt; /**< Reference counter. */
460 /**< Modify header action object. */
461 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
462 uint32_t actions_num; /**< Number of modification actions. */
463 uint64_t flags; /**< Flags for RDMA API. */
464 struct mlx5_modification_cmd actions[];
465 /**< Modification actions. */
468 /* Modify resource key of the hash organization. */
469 union mlx5_flow_modify_hdr_key {
471 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
472 uint32_t actions_num:5; /**< Number of modification actions. */
473 uint32_t group:19; /**< Flow group id. */
474 uint32_t cksum; /**< Actions check sum. */
476 uint64_t v64; /**< full 64bits value of key */
479 /* Jump action resource structure. */
480 struct mlx5_flow_dv_jump_tbl_resource {
481 rte_atomic32_t refcnt; /**< Reference counter. */
482 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
483 void *action; /**< Pointer to the rdma core action. */
486 /* Port ID resource structure. */
487 struct mlx5_flow_dv_port_id_action_resource {
488 ILIST_ENTRY(uint32_t)next;
489 /* Pointer to next element. */
490 rte_atomic32_t refcnt; /**< Reference counter. */
492 /**< Action object. */
493 uint32_t port_id; /**< Port ID value. */
496 /* Push VLAN action resource structure */
497 struct mlx5_flow_dv_push_vlan_action_resource {
498 ILIST_ENTRY(uint32_t)next;
499 /* Pointer to next element. */
500 rte_atomic32_t refcnt; /**< Reference counter. */
501 void *action; /**< Action object. */
502 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
503 rte_be32_t vlan_tag; /**< VLAN tag value. */
506 /* Metadata register copy table entry. */
507 struct mlx5_flow_mreg_copy_resource {
509 * Hash list entry for copy table.
510 * - Key is 32/64-bit MARK action ID.
511 * - MUST be the first entry.
513 struct mlx5_hlist_entry hlist_ent;
514 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
515 /* List entry for device flows. */
516 uint32_t refcnt; /* Reference counter. */
517 uint32_t appcnt; /* Apply/Remove counter. */
519 uint32_t rix_flow; /* Built flow for copy. */
522 /* Table data structure of the hash organization. */
523 struct mlx5_flow_tbl_data_entry {
524 struct mlx5_hlist_entry entry;
525 /**< hash list entry, 64-bits key inside. */
526 struct mlx5_flow_tbl_resource tbl;
527 /**< flow table resource. */
528 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
529 /**< matchers' header associated with the flow table. */
530 struct mlx5_flow_dv_jump_tbl_resource jump;
531 /**< jump resource, at most one for each table created. */
532 uint32_t idx; /**< index for the indexed mempool. */
535 /* Sub rdma-core actions list. */
536 struct mlx5_flow_sub_actions_list {
537 uint32_t actions_num; /**< Number of sample actions. */
538 uint64_t action_flags;
539 void *dr_queue_action;
542 void *dr_port_id_action;
543 void *dr_encap_action;
546 /* Sample sub-actions resource list. */
547 struct mlx5_flow_sub_actions_idx {
548 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
549 uint32_t rix_tag; /**< Index to the tag action. */
551 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
552 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
555 /* Sample action resource structure. */
556 struct mlx5_flow_dv_sample_resource {
557 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
558 uint32_t refcnt; /**< Reference counter. */
559 void *verbs_action; /**< Verbs sample action object. */
560 uint8_t ft_type; /** Flow Table Type */
561 uint32_t ft_id; /** Flow Table Level */
562 uint32_t ratio; /** Sample Ratio */
563 uint64_t set_action; /** Restore reg_c0 value */
564 void *normal_path_tbl; /** Flow Table pointer */
565 void *default_miss; /** default_miss dr_action. */
566 struct mlx5_flow_sub_actions_idx sample_idx;
567 /**< Action index resources. */
568 struct mlx5_flow_sub_actions_list sample_act;
569 /**< Action resources. */
572 #define MLX5_MAX_DEST_NUM 2
574 /* Destination array action resource structure. */
575 struct mlx5_flow_dv_dest_array_resource {
576 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
577 uint32_t refcnt; /**< Reference counter. */
578 uint8_t ft_type; /** Flow Table Type */
579 uint8_t num_of_dest; /**< Number of destination actions. */
580 void *action; /**< Pointer to the rdma core action. */
581 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
582 /**< Action index resources. */
583 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
584 /**< Action resources. */
587 /* Verbs specification header. */
588 struct ibv_spec_header {
589 enum ibv_flow_spec_type type;
593 /* RSS description. */
594 struct mlx5_flow_rss_desc {
596 uint32_t queue_num; /**< Number of entries in @p queue. */
597 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
598 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
599 uint16_t queue[]; /**< Destination queues to redirect traffic to. */
602 /* PMD flow priority for tunnel */
603 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
604 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
607 /** Device flow handle structure for DV mode only. */
608 struct mlx5_flow_handle_dv {
610 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
611 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
612 /**< Pointer to modify header resource in cache. */
613 uint32_t rix_encap_decap;
614 /**< Index to encap/decap resource in cache. */
615 uint32_t rix_push_vlan;
616 /**< Index to push VLAN action resource in cache. */
618 /**< Index to the tag action. */
620 /**< Index to sample action resource in cache. */
621 uint32_t rix_dest_array;
622 /**< Index to destination array resource in cache. */
625 /** Device flow handle structure: used both for creating & destroying. */
626 struct mlx5_flow_handle {
627 SILIST_ENTRY(uint32_t)next;
628 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
629 /**< Index to next device flow handle. */
631 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
632 void *drv_flow; /**< pointer to driver flow object. */
633 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
634 uint32_t mark:1; /**< Metadate rxq mark flag. */
635 uint32_t fate_action:3; /**< Fate action type. */
637 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
638 uint32_t rix_jump; /**< Index to the jump action resource. */
639 uint32_t rix_port_id_action;
640 /**< Index to port ID action resource. */
642 /**< Generic value indicates the fate action. */
643 uint32_t rix_default_fate;
644 /**< Indicates default miss fate action. */
646 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
647 struct mlx5_flow_handle_dv dvh;
652 * Size for Verbs device flow handle structure only. Do not use the DV only
653 * structure in Verbs. No DV flows attributes will be accessed.
654 * Macro offsetof() could also be used here.
656 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
657 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
658 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
660 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
664 * Max number of actions per DV flow.
665 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
666 * in rdma-core file providers/mlx5/verbs.c.
668 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
670 /** Device flow structure only for DV flow creation. */
671 struct mlx5_flow_dv_workspace {
672 uint32_t group; /**< The group index. */
673 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
674 int actions_n; /**< number of actions. */
675 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
676 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
677 /**< Pointer to encap/decap resource in cache. */
678 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
679 /**< Pointer to push VLAN action resource in cache. */
680 struct mlx5_flow_dv_tag_resource *tag_resource;
681 /**< pointer to the tag action. */
682 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
683 /**< Pointer to port ID action resource. */
684 struct mlx5_flow_dv_jump_tbl_resource *jump;
685 /**< Pointer to the jump action resource. */
686 struct mlx5_flow_dv_match_params value;
687 /**< Holds the value that the packet is compared to. */
688 struct mlx5_flow_dv_sample_resource *sample_res;
689 /**< Pointer to the sample action resource. */
690 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
691 /**< Pointer to the destination array resource. */
695 * Maximal Verbs flow specifications & actions size.
696 * Some elements are mutually exclusive, but enough space should be allocated.
697 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
698 * 2. One tunnel header (exception: GRE + MPLS),
699 * SPEC length: GRE == tunnel.
700 * Actions: 1. 1 Mark OR Flag.
701 * 2. 1 Drop (if any).
702 * 3. No limitation for counters, but it makes no sense to support too
703 * many counters in a single device flow.
705 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
706 #define MLX5_VERBS_MAX_SPEC_SIZE \
708 (2 * (sizeof(struct ibv_flow_spec_eth) + \
709 sizeof(struct ibv_flow_spec_ipv6) + \
710 sizeof(struct ibv_flow_spec_tcp_udp)) + \
711 sizeof(struct ibv_flow_spec_gre) + \
712 sizeof(struct ibv_flow_spec_mpls)) \
715 #define MLX5_VERBS_MAX_SPEC_SIZE \
717 (2 * (sizeof(struct ibv_flow_spec_eth) + \
718 sizeof(struct ibv_flow_spec_ipv6) + \
719 sizeof(struct ibv_flow_spec_tcp_udp)) + \
720 sizeof(struct ibv_flow_spec_tunnel)) \
724 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
725 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
726 #define MLX5_VERBS_MAX_ACT_SIZE \
728 sizeof(struct ibv_flow_spec_action_tag) + \
729 sizeof(struct ibv_flow_spec_action_drop) + \
730 sizeof(struct ibv_flow_spec_counter_action) * 4 \
733 #define MLX5_VERBS_MAX_ACT_SIZE \
735 sizeof(struct ibv_flow_spec_action_tag) + \
736 sizeof(struct ibv_flow_spec_action_drop) \
740 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
741 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
743 /** Device flow structure only for Verbs flow creation. */
744 struct mlx5_flow_verbs_workspace {
745 unsigned int size; /**< Size of the attribute. */
746 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
747 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
748 /**< Specifications & actions buffer of verbs flow. */
751 /** Maximal number of device sub-flows supported. */
752 #define MLX5_NUM_MAX_DEV_FLOWS 32
754 /** Device flow structure. */
756 struct rte_flow *flow; /**< Pointer to the main flow. */
757 uint32_t flow_idx; /**< The memory pool index to the main flow. */
758 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
760 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
761 bool external; /**< true if the flow is created external to PMD. */
762 uint8_t ingress; /**< 1 if the flow is ingress. */
764 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
765 struct mlx5_flow_dv_workspace dv;
767 struct mlx5_flow_verbs_workspace verbs;
769 struct mlx5_flow_handle *handle;
770 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
773 /* Flow meter state. */
774 #define MLX5_FLOW_METER_DISABLE 0
775 #define MLX5_FLOW_METER_ENABLE 1
777 #define MLX5_MAN_WIDTH 8
778 /* Modify this value if enum rte_mtr_color changes. */
779 #define RTE_MTR_DROPPED RTE_COLORS
781 /* Meter policer statistics */
782 struct mlx5_flow_policer_stats {
783 uint32_t cnt[RTE_COLORS + 1];
784 /**< Color counter, extra for drop. */
786 /**< Statistics mask for the colors. */
789 /* Meter table structure. */
790 struct mlx5_meter_domain_info {
791 struct mlx5_flow_tbl_resource *tbl;
793 struct mlx5_flow_tbl_resource *sfx_tbl;
794 /**< Meter suffix table. */
796 /**< Meter color not match default criteria. */
798 /**< Meter color match criteria. */
800 /**< Meter match action. */
801 void *policer_rules[RTE_MTR_DROPPED + 1];
802 /**< Meter policer for the match. */
805 /* Meter table set for TX RX FDB. */
806 struct mlx5_meter_domains_infos {
808 /**< Table user count. */
809 struct mlx5_meter_domain_info egress;
810 /**< TX meter table. */
811 struct mlx5_meter_domain_info ingress;
812 /**< RX meter table. */
813 struct mlx5_meter_domain_info transfer;
814 /**< FDB meter table. */
816 /**< Drop action as not matched. */
817 void *count_actns[RTE_MTR_DROPPED + 1];
818 /**< Counters for match and unmatched statistics. */
819 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
820 /**< Flow meter parameter. */
822 /**< Flow meter parameter size. */
824 /**< Flow meter action. */
827 /* Meter parameter structure. */
828 struct mlx5_flow_meter {
829 TAILQ_ENTRY(mlx5_flow_meter) next;
830 /**< Pointer to the next flow meter structure. */
831 uint32_t idx; /* Index to meter object. */
834 struct mlx5_flow_meter_profile *profile;
835 /**< Meter profile parameters. */
837 /** Policer actions (per meter output color). */
838 enum rte_mtr_policer_action action[RTE_COLORS];
840 /** Set of stats counters to be enabled.
841 * @see enum rte_mtr_stats_type
845 /**< Rule applies to ingress traffic. */
848 /**< Rule applies to egress traffic. */
851 * Instead of simply matching the properties of traffic as it would
852 * appear on a given DPDK port ID, enabling this attribute transfers
853 * a flow rule to the lowest possible level of any device endpoints
854 * found in the pattern.
856 * When supported, this effectively enables an application to
857 * re-route traffic not necessarily intended for it (e.g. coming
858 * from or addressed to different physical ports, VFs or
859 * applications) at the device level.
861 * It complements the behavior of some pattern items such as
862 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
864 * When transferring flow rules, ingress and egress attributes keep
865 * their original meaning, as if processing traffic emitted or
866 * received by the application.
869 struct mlx5_meter_domains_infos *mfts;
870 /**< Flow table created for this meter. */
871 struct mlx5_flow_policer_stats policer_stats;
872 /**< Meter policer statistics. */
875 uint32_t active_state:1;
878 /**< Meter shared or not. */
881 /* RFC2697 parameter structure. */
882 struct mlx5_flow_meter_srtcm_rfc2697_prm {
883 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
884 uint32_t cbs_exponent:5;
885 uint32_t cbs_mantissa:8;
886 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
887 uint32_t cir_exponent:5;
888 uint32_t cir_mantissa:8;
889 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
890 uint32_t ebs_exponent:5;
891 uint32_t ebs_mantissa:8;
894 /* Flow meter profile structure. */
895 struct mlx5_flow_meter_profile {
896 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
897 /**< Pointer to the next flow meter structure. */
898 uint32_t meter_profile_id; /**< Profile id. */
899 struct rte_mtr_meter_profile profile; /**< Profile detail. */
901 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
902 /**< srtcm_rfc2697 struct. */
904 uint32_t ref_cnt; /**< Use count. */
907 /* Fdir flow structure */
908 struct mlx5_fdir_flow {
909 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */
910 struct mlx5_fdir *fdir; /* Pointer to fdir. */
911 uint32_t rix_flow; /* Index to flow. */
914 #define HAIRPIN_FLOW_ID_BITS 28
916 /* Flow structure. */
918 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
919 uint32_t dev_handles;
920 /**< Device flow handles that are part of the flow. */
921 uint32_t drv_type:2; /**< Driver type. */
922 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */
923 uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS;
924 /**< The flow id used for hairpin. */
925 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
926 uint32_t rix_mreg_copy;
927 /**< Index to metadata register copy table resource. */
928 uint32_t counter; /**< Holds flow counter. */
929 uint16_t meter; /**< Holds flow meter id. */
932 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
933 const struct rte_flow_attr *attr,
934 const struct rte_flow_item items[],
935 const struct rte_flow_action actions[],
938 struct rte_flow_error *error);
939 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
940 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
941 const struct rte_flow_item items[],
942 const struct rte_flow_action actions[], struct rte_flow_error *error);
943 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
944 struct mlx5_flow *dev_flow,
945 const struct rte_flow_attr *attr,
946 const struct rte_flow_item items[],
947 const struct rte_flow_action actions[],
948 struct rte_flow_error *error);
949 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
950 struct rte_flow_error *error);
951 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
952 struct rte_flow *flow);
953 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
954 struct rte_flow *flow);
955 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
956 struct rte_flow *flow,
957 const struct rte_flow_action *actions,
959 struct rte_flow_error *error);
960 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
961 (struct rte_eth_dev *dev,
962 const struct mlx5_flow_meter *fm);
963 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
964 struct mlx5_meter_domains_infos *tbls);
965 typedef int (*mlx5_flow_create_policer_rules_t)
966 (struct rte_eth_dev *dev,
967 struct mlx5_flow_meter *fm,
968 const struct rte_flow_attr *attr);
969 typedef int (*mlx5_flow_destroy_policer_rules_t)
970 (struct rte_eth_dev *dev,
971 const struct mlx5_flow_meter *fm,
972 const struct rte_flow_attr *attr);
973 typedef uint32_t (*mlx5_flow_counter_alloc_t)
974 (struct rte_eth_dev *dev);
975 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
977 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
979 bool clear, uint64_t *pkts,
981 typedef int (*mlx5_flow_get_aged_flows_t)
982 (struct rte_eth_dev *dev,
984 uint32_t nb_contexts,
985 struct rte_flow_error *error);
986 struct mlx5_flow_driver_ops {
987 mlx5_flow_validate_t validate;
988 mlx5_flow_prepare_t prepare;
989 mlx5_flow_translate_t translate;
990 mlx5_flow_apply_t apply;
991 mlx5_flow_remove_t remove;
992 mlx5_flow_destroy_t destroy;
993 mlx5_flow_query_t query;
994 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
995 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
996 mlx5_flow_create_policer_rules_t create_policer_rules;
997 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
998 mlx5_flow_counter_alloc_t counter_alloc;
999 mlx5_flow_counter_free_t counter_free;
1000 mlx5_flow_counter_query_t counter_query;
1001 mlx5_flow_get_aged_flows_t get_aged_flows;
1006 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id);
1007 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
1008 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
1009 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
1011 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
1012 bool external, uint32_t group, bool fdb_def_rule,
1013 uint32_t *table, struct rte_flow_error *error);
1014 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1015 int tunnel, uint64_t layer_types,
1016 uint64_t hash_fields);
1017 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1018 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1019 uint32_t subpriority);
1020 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1021 enum mlx5_feature_name feature,
1023 struct rte_flow_error *error);
1024 const struct rte_flow_action *mlx5_flow_find_action
1025 (const struct rte_flow_action *actions,
1026 enum rte_flow_action_type action);
1027 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1028 const struct rte_flow_attr *attr,
1029 struct rte_flow_error *error);
1030 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1031 const struct rte_flow_attr *attr,
1032 struct rte_flow_error *error);
1033 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1034 const struct rte_flow_attr *attr,
1035 struct rte_flow_error *error);
1036 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1037 uint64_t action_flags,
1038 const struct rte_flow_attr *attr,
1039 struct rte_flow_error *error);
1040 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1041 uint64_t action_flags,
1042 struct rte_eth_dev *dev,
1043 const struct rte_flow_attr *attr,
1044 struct rte_flow_error *error);
1045 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1046 uint64_t action_flags,
1047 struct rte_eth_dev *dev,
1048 const struct rte_flow_attr *attr,
1049 uint64_t item_flags,
1050 struct rte_flow_error *error);
1051 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1052 const struct rte_flow_attr *attr,
1053 struct rte_flow_error *error);
1054 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1055 const struct rte_flow_attr *attributes,
1056 struct rte_flow_error *error);
1057 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1058 const uint8_t *mask,
1059 const uint8_t *nic_mask,
1061 bool range_accepted,
1062 struct rte_flow_error *error);
1063 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1064 uint64_t item_flags,
1065 struct rte_flow_error *error);
1066 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1067 uint64_t item_flags,
1068 uint8_t target_protocol,
1069 struct rte_flow_error *error);
1070 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1071 uint64_t item_flags,
1072 const struct rte_flow_item *gre_item,
1073 struct rte_flow_error *error);
1074 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1075 uint64_t item_flags,
1077 uint16_t ether_type,
1078 const struct rte_flow_item_ipv4 *acc_mask,
1079 bool range_accepted,
1080 struct rte_flow_error *error);
1081 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1082 uint64_t item_flags,
1084 uint16_t ether_type,
1085 const struct rte_flow_item_ipv6 *acc_mask,
1086 struct rte_flow_error *error);
1087 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1088 const struct rte_flow_item *item,
1089 uint64_t item_flags,
1090 uint64_t prev_layer,
1091 struct rte_flow_error *error);
1092 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1093 uint64_t item_flags,
1094 uint8_t target_protocol,
1095 const struct rte_flow_item_tcp *flow_mask,
1096 struct rte_flow_error *error);
1097 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1098 uint64_t item_flags,
1099 uint8_t target_protocol,
1100 struct rte_flow_error *error);
1101 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1102 uint64_t item_flags,
1103 struct rte_eth_dev *dev,
1104 struct rte_flow_error *error);
1105 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1106 uint64_t item_flags,
1107 struct rte_flow_error *error);
1108 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1109 uint64_t item_flags,
1110 struct rte_eth_dev *dev,
1111 struct rte_flow_error *error);
1112 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1113 uint64_t item_flags,
1114 uint8_t target_protocol,
1115 struct rte_flow_error *error);
1116 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1117 uint64_t item_flags,
1118 uint8_t target_protocol,
1119 struct rte_flow_error *error);
1120 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1121 uint64_t item_flags,
1122 uint8_t target_protocol,
1123 struct rte_flow_error *error);
1124 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1125 uint64_t item_flags,
1126 struct rte_eth_dev *dev,
1127 struct rte_flow_error *error);
1128 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1129 uint64_t item_flags,
1131 uint16_t ether_type,
1132 const struct rte_flow_item_ecpri *acc_mask,
1133 struct rte_flow_error *error);
1134 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1135 (struct rte_eth_dev *dev,
1136 const struct mlx5_flow_meter *fm);
1137 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1138 struct mlx5_meter_domains_infos *tbl);
1139 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1140 struct mlx5_flow_meter *fm,
1141 const struct rte_flow_attr *attr);
1142 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1143 struct mlx5_flow_meter *fm,
1144 const struct rte_flow_attr *attr);
1145 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1146 struct rte_mtr_error *error);
1147 #endif /* RTE_PMD_MLX5_FLOW_H_ */