1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* Private rte flow items. */
22 enum mlx5_rte_flow_item_type {
23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
24 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
30 /* Private (internal) rte flow actions. */
31 enum mlx5_rte_flow_action_type {
32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
34 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
38 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
41 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
44 MLX5_INDIRECT_ACTION_TYPE_RSS,
45 MLX5_INDIRECT_ACTION_TYPE_AGE,
48 /* Matches on selected register. */
49 struct mlx5_rte_flow_item_tag {
54 /* Modify selected register. */
55 struct mlx5_rte_flow_action_set_tag {
62 struct mlx5_flow_action_copy_mreg {
67 /* Matches on source queue. */
68 struct mlx5_rte_flow_item_tx_queue {
72 /* Feature name to allocate metadata register. */
73 enum mlx5_feature_name {
87 /* Default queue number. */
88 #define MLX5_RSSQ_DEFAULT_NUM 16
90 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
91 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
92 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
93 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
94 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
95 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
97 /* Pattern inner Layer bits. */
98 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
99 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
100 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
101 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
102 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
103 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
105 /* Pattern tunnel Layer bits. */
106 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
107 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
108 #define MLX5_FLOW_LAYER_GRE (1u << 14)
109 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
110 /* List of tunnel Layer bits continued below. */
112 /* General pattern items bits. */
113 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
114 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
115 #define MLX5_FLOW_ITEM_TAG (1u << 18)
116 #define MLX5_FLOW_ITEM_MARK (1u << 19)
118 /* Pattern MISC bits. */
119 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
120 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
121 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
123 /* Pattern tunnel Layer bits (continued). */
124 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
125 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
126 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
127 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
130 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
132 /* Pattern tunnel Layer bits (continued). */
133 #define MLX5_FLOW_LAYER_GTP (1u << 28)
135 /* Pattern eCPRI Layer bit. */
136 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
138 /* IPv6 Fragment Extension Header bit. */
139 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
140 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
142 /* Pattern tunnel Layer bits (continued). */
143 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
144 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
147 #define MLX5_FLOW_LAYER_OUTER_L3 \
148 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
149 #define MLX5_FLOW_LAYER_OUTER_L4 \
150 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
151 #define MLX5_FLOW_LAYER_OUTER \
152 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
153 MLX5_FLOW_LAYER_OUTER_L4)
156 #define MLX5_FLOW_LAYER_TUNNEL \
157 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
158 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
159 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
160 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
163 #define MLX5_FLOW_LAYER_INNER_L3 \
164 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
165 #define MLX5_FLOW_LAYER_INNER_L4 \
166 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
167 #define MLX5_FLOW_LAYER_INNER \
168 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
169 MLX5_FLOW_LAYER_INNER_L4)
172 #define MLX5_FLOW_LAYER_L2 \
173 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
174 #define MLX5_FLOW_LAYER_L3_IPV4 \
175 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
176 #define MLX5_FLOW_LAYER_L3_IPV6 \
177 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
178 #define MLX5_FLOW_LAYER_L3 \
179 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
180 #define MLX5_FLOW_LAYER_L4 \
181 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
184 #define MLX5_FLOW_ACTION_DROP (1u << 0)
185 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
186 #define MLX5_FLOW_ACTION_RSS (1u << 2)
187 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
188 #define MLX5_FLOW_ACTION_MARK (1u << 4)
189 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
190 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
191 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
192 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
193 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
194 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
195 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
196 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
197 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
198 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
199 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
200 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
201 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
202 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
203 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
204 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
205 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
206 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
207 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
208 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
209 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
210 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
211 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
212 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
213 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
214 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
215 #define MLX5_FLOW_ACTION_METER (1ull << 31)
216 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
217 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
218 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
219 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
220 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
221 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
222 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
223 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
225 #define MLX5_FLOW_FATE_ACTIONS \
226 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
227 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
228 MLX5_FLOW_ACTION_DEFAULT_MISS)
230 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
231 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
232 MLX5_FLOW_ACTION_JUMP)
235 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
236 MLX5_FLOW_ACTION_SET_IPV4_DST | \
237 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
238 MLX5_FLOW_ACTION_SET_IPV6_DST | \
239 MLX5_FLOW_ACTION_SET_TP_SRC | \
240 MLX5_FLOW_ACTION_SET_TP_DST | \
241 MLX5_FLOW_ACTION_SET_TTL | \
242 MLX5_FLOW_ACTION_DEC_TTL | \
243 MLX5_FLOW_ACTION_SET_MAC_SRC | \
244 MLX5_FLOW_ACTION_SET_MAC_DST | \
245 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
246 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
247 MLX5_FLOW_ACTION_INC_TCP_ACK | \
248 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
249 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
250 MLX5_FLOW_ACTION_SET_TAG | \
251 MLX5_FLOW_ACTION_MARK_EXT | \
252 MLX5_FLOW_ACTION_SET_META | \
253 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
254 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
255 MLX5_FLOW_ACTION_MODIFY_FIELD)
257 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
258 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
260 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
263 #define IPPROTO_MPLS 137
266 /* UDP port number for MPLS */
267 #define MLX5_UDP_PORT_MPLS 6635
269 /* UDP port numbers for VxLAN. */
270 #define MLX5_UDP_PORT_VXLAN 4789
271 #define MLX5_UDP_PORT_VXLAN_GPE 4790
273 /* UDP port numbers for GENEVE. */
274 #define MLX5_UDP_PORT_GENEVE 6081
276 /* Lowest priority indicator. */
277 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
280 * Max priority for ingress\egress flow groups
281 * greater than 0 and for any transfer flow group.
282 * From user configation: 0 - 21843.
284 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
287 * Number of sub priorities.
288 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
289 * matching on the NIC (firmware dependent) L4 most have the higher priority
290 * followed by L3 and ending with L2.
292 #define MLX5_PRIORITY_MAP_L2 2
293 #define MLX5_PRIORITY_MAP_L3 1
294 #define MLX5_PRIORITY_MAP_L4 0
295 #define MLX5_PRIORITY_MAP_MAX 3
297 /* Valid layer type for IPV4 RSS. */
298 #define MLX5_IPV4_LAYER_TYPES \
299 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
300 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
301 ETH_RSS_NONFRAG_IPV4_OTHER)
303 /* IBV hash source bits for IPV4. */
304 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
306 /* Valid layer type for IPV6 RSS. */
307 #define MLX5_IPV6_LAYER_TYPES \
308 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
309 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
310 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
312 /* IBV hash source bits for IPV6. */
313 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
315 /* IBV hash bits for L3 SRC. */
316 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
318 /* IBV hash bits for L3 DST. */
319 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
321 /* IBV hash bits for TCP. */
322 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
323 IBV_RX_HASH_DST_PORT_TCP)
325 /* IBV hash bits for UDP. */
326 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
327 IBV_RX_HASH_DST_PORT_UDP)
329 /* IBV hash bits for L4 SRC. */
330 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
331 IBV_RX_HASH_SRC_PORT_UDP)
333 /* IBV hash bits for L4 DST. */
334 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
335 IBV_RX_HASH_DST_PORT_UDP)
337 /* Geneve header first 16Bit */
338 #define MLX5_GENEVE_VER_MASK 0x3
339 #define MLX5_GENEVE_VER_SHIFT 14
340 #define MLX5_GENEVE_VER_VAL(a) \
341 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
342 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
343 #define MLX5_GENEVE_OPTLEN_SHIFT 8
344 #define MLX5_GENEVE_OPTLEN_VAL(a) \
345 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
346 #define MLX5_GENEVE_OAMF_MASK 0x1
347 #define MLX5_GENEVE_OAMF_SHIFT 7
348 #define MLX5_GENEVE_OAMF_VAL(a) \
349 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
350 #define MLX5_GENEVE_CRITO_MASK 0x1
351 #define MLX5_GENEVE_CRITO_SHIFT 6
352 #define MLX5_GENEVE_CRITO_VAL(a) \
353 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
354 #define MLX5_GENEVE_RSVD_MASK 0x3F
355 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
357 * The length of the Geneve options fields, expressed in four byte multiples,
358 * not including the eight byte fixed tunnel.
360 #define MLX5_GENEVE_OPT_LEN_0 14
361 #define MLX5_GENEVE_OPT_LEN_1 63
363 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
364 sizeof(struct rte_ipv4_hdr))
365 /* GTP extension header flag. */
366 #define MLX5_GTP_EXT_HEADER_FLAG 4
368 /* GTP extension header max PDU type value. */
369 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15
371 /* GTP extension header PDU type shift. */
372 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
374 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
375 #define MLX5_IPV4_FRAG_OFFSET_MASK \
376 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
378 /* Specific item's fields can accept a range of values (using spec and last). */
379 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
380 #define MLX5_ITEM_RANGE_ACCEPTED true
382 /* Software header modify action numbers of a flow. */
383 #define MLX5_ACT_NUM_MDF_IPV4 1
384 #define MLX5_ACT_NUM_MDF_IPV6 4
385 #define MLX5_ACT_NUM_MDF_MAC 2
386 #define MLX5_ACT_NUM_MDF_VID 1
387 #define MLX5_ACT_NUM_MDF_PORT 2
388 #define MLX5_ACT_NUM_MDF_TTL 1
389 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
390 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
391 #define MLX5_ACT_NUM_MDF_TCPACK 1
392 #define MLX5_ACT_NUM_SET_REG 1
393 #define MLX5_ACT_NUM_SET_TAG 1
394 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
395 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
396 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
397 #define MLX5_ACT_NUM_SET_DSCP 1
399 /* Maximum number of fields to modify in MODIFY_FIELD */
400 #define MLX5_ACT_MAX_MOD_FIELDS 5
402 enum mlx5_flow_drv_type {
405 MLX5_FLOW_TYPE_VERBS,
409 /* Fate action type. */
410 enum mlx5_flow_fate_type {
411 MLX5_FLOW_FATE_NONE, /* Egress flow. */
412 MLX5_FLOW_FATE_QUEUE,
414 MLX5_FLOW_FATE_PORT_ID,
416 MLX5_FLOW_FATE_DEFAULT_MISS,
417 MLX5_FLOW_FATE_SHARED_RSS,
421 /* Matcher PRM representation */
422 struct mlx5_flow_dv_match_params {
424 /**< Size of match value. Do NOT split size and key! */
425 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
426 /**< Matcher value. This value is used as the mask or as a key. */
429 /* Matcher structure. */
430 struct mlx5_flow_dv_matcher {
431 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
432 struct mlx5_flow_tbl_resource *tbl;
433 /**< Pointer to the table(group) the matcher associated with. */
434 void *matcher_object; /**< Pointer to DV matcher */
435 uint16_t crc; /**< CRC of key. */
436 uint16_t priority; /**< Priority of matcher. */
437 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
440 #define MLX5_ENCAP_MAX_LEN 132
442 /* Encap/decap resource structure. */
443 struct mlx5_flow_dv_encap_decap_resource {
444 struct mlx5_hlist_entry entry;
445 /* Pointer to next element. */
446 uint32_t refcnt; /**< Reference counter. */
448 /**< Encap/decap action object. */
449 uint8_t buf[MLX5_ENCAP_MAX_LEN];
451 uint8_t reformat_type;
453 uint64_t flags; /**< Flags for RDMA API. */
454 uint32_t idx; /**< Index for the index memory pool. */
457 /* Tag resource structure. */
458 struct mlx5_flow_dv_tag_resource {
459 struct mlx5_hlist_entry entry;
460 /**< hash list entry for tag resource, tag value as the key. */
462 /**< Tag action object. */
463 uint32_t refcnt; /**< Reference counter. */
464 uint32_t idx; /**< Index for the index memory pool. */
465 uint32_t tag_id; /**< Tag ID. */
469 * Number of modification commands.
470 * The maximal actions amount in FW is some constant, and it is 16 in the
471 * latest releases. In some old releases, it will be limited to 8.
472 * Since there is no interface to query the capacity, the maximal value should
473 * be used to allow PMD to create the flow. The validation will be done in the
474 * lower driver layer or FW. A failure will be returned if exceeds the maximal
475 * supported actions number on the root table.
476 * On non-root tables, there is no limitation, but 32 is enough right now.
478 #define MLX5_MAX_MODIFY_NUM 32
479 #define MLX5_ROOT_TBL_MODIFY_NUM 16
481 /* Modify resource structure */
482 struct mlx5_flow_dv_modify_hdr_resource {
483 struct mlx5_hlist_entry entry;
484 void *action; /**< Modify header action object. */
485 /* Key area for hash list matching: */
486 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
487 uint32_t actions_num; /**< Number of modification actions. */
488 uint64_t flags; /**< Flags for RDMA API. */
489 struct mlx5_modification_cmd actions[];
490 /**< Modification actions. */
493 /* Modify resource key of the hash organization. */
494 union mlx5_flow_modify_hdr_key {
496 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
497 uint32_t actions_num:5; /**< Number of modification actions. */
498 uint32_t group:19; /**< Flow group id. */
499 uint32_t cksum; /**< Actions check sum. */
501 uint64_t v64; /**< full 64bits value of key */
504 /* Jump action resource structure. */
505 struct mlx5_flow_dv_jump_tbl_resource {
506 void *action; /**< Pointer to the rdma core action. */
509 /* Port ID resource structure. */
510 struct mlx5_flow_dv_port_id_action_resource {
511 struct mlx5_cache_entry entry;
512 void *action; /**< Action object. */
513 uint32_t port_id; /**< Port ID value. */
514 uint32_t idx; /**< Indexed pool memory index. */
517 /* Push VLAN action resource structure */
518 struct mlx5_flow_dv_push_vlan_action_resource {
519 struct mlx5_cache_entry entry; /* Cache entry. */
520 void *action; /**< Action object. */
521 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
522 rte_be32_t vlan_tag; /**< VLAN tag value. */
523 uint32_t idx; /**< Indexed pool memory index. */
526 /* Metadata register copy table entry. */
527 struct mlx5_flow_mreg_copy_resource {
529 * Hash list entry for copy table.
530 * - Key is 32/64-bit MARK action ID.
531 * - MUST be the first entry.
533 struct mlx5_hlist_entry hlist_ent;
534 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
535 /* List entry for device flows. */
537 uint32_t rix_flow; /* Built flow for copy. */
541 /* Table tunnel parameter. */
542 struct mlx5_flow_tbl_tunnel_prm {
543 const struct mlx5_flow_tunnel *tunnel;
548 /* Table data structure of the hash organization. */
549 struct mlx5_flow_tbl_data_entry {
550 struct mlx5_hlist_entry entry;
551 /**< hash list entry, 64-bits key inside. */
552 struct mlx5_flow_tbl_resource tbl;
553 /**< flow table resource. */
554 struct mlx5_cache_list matchers;
555 /**< matchers' header associated with the flow table. */
556 struct mlx5_flow_dv_jump_tbl_resource jump;
557 /**< jump resource, at most one for each table created. */
558 uint32_t idx; /**< index for the indexed mempool. */
559 /**< tunnel offload */
560 const struct mlx5_flow_tunnel *tunnel;
563 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */
564 uint32_t is_egress:1; /**< Egress table. */
565 uint32_t is_transfer:1; /**< Transfer table. */
566 uint32_t dummy:1; /**< DR table. */
567 uint32_t id:22; /**< Table ID. */
568 uint32_t reserve:5; /**< Reserved to future using. */
569 uint32_t level; /**< Table level. */
572 /* Sub rdma-core actions list. */
573 struct mlx5_flow_sub_actions_list {
574 uint32_t actions_num; /**< Number of sample actions. */
575 uint64_t action_flags;
576 void *dr_queue_action;
579 void *dr_port_id_action;
580 void *dr_encap_action;
581 void *dr_jump_action;
584 /* Sample sub-actions resource list. */
585 struct mlx5_flow_sub_actions_idx {
586 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
587 uint32_t rix_tag; /**< Index to the tag action. */
588 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
589 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
590 uint32_t rix_jump; /**< Index to the jump action resource. */
593 /* Sample action resource structure. */
594 struct mlx5_flow_dv_sample_resource {
595 struct mlx5_cache_entry entry; /**< Cache entry. */
597 void *verbs_action; /**< Verbs sample action object. */
598 void **sub_actions; /**< Sample sub-action array. */
600 struct rte_eth_dev *dev; /**< Device registers the action. */
601 uint32_t idx; /** Sample object index. */
602 uint8_t ft_type; /** Flow Table Type */
603 uint32_t ft_id; /** Flow Table Level */
604 uint32_t ratio; /** Sample Ratio */
605 uint64_t set_action; /** Restore reg_c0 value */
606 void *normal_path_tbl; /** Flow Table pointer */
607 struct mlx5_flow_sub_actions_idx sample_idx;
608 /**< Action index resources. */
609 struct mlx5_flow_sub_actions_list sample_act;
610 /**< Action resources. */
613 #define MLX5_MAX_DEST_NUM 2
615 /* Destination array action resource structure. */
616 struct mlx5_flow_dv_dest_array_resource {
617 struct mlx5_cache_entry entry; /**< Cache entry. */
618 uint32_t idx; /** Destination array action object index. */
619 uint8_t ft_type; /** Flow Table Type */
620 uint8_t num_of_dest; /**< Number of destination actions. */
621 struct rte_eth_dev *dev; /**< Device registers the action. */
622 void *action; /**< Pointer to the rdma core action. */
623 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
624 /**< Action index resources. */
625 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
626 /**< Action resources. */
629 /* PMD flow priority for tunnel */
630 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
631 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
634 /** Device flow handle structure for DV mode only. */
635 struct mlx5_flow_handle_dv {
637 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
638 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
639 /**< Pointer to modify header resource in cache. */
640 uint32_t rix_encap_decap;
641 /**< Index to encap/decap resource in cache. */
642 uint32_t rix_push_vlan;
643 /**< Index to push VLAN action resource in cache. */
645 /**< Index to the tag action. */
647 /**< Index to sample action resource in cache. */
648 uint32_t rix_dest_array;
649 /**< Index to destination array resource in cache. */
652 /** Device flow handle structure: used both for creating & destroying. */
653 struct mlx5_flow_handle {
654 SILIST_ENTRY(uint32_t)next;
655 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
656 /**< Index to next device flow handle. */
658 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
659 void *drv_flow; /**< pointer to driver flow object. */
660 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
661 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */
662 uint32_t mark:1; /**< Metadate rxq mark flag. */
663 uint32_t fate_action:3; /**< Fate action type. */
665 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
666 uint32_t rix_jump; /**< Index to the jump action resource. */
667 uint32_t rix_port_id_action;
668 /**< Index to port ID action resource. */
670 /**< Generic value indicates the fate action. */
671 uint32_t rix_default_fate;
672 /**< Indicates default miss fate action. */
674 /**< Indicates shared RSS fate action. */
676 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
677 struct mlx5_flow_handle_dv dvh;
682 * Size for Verbs device flow handle structure only. Do not use the DV only
683 * structure in Verbs. No DV flows attributes will be accessed.
684 * Macro offsetof() could also be used here.
686 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
687 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
688 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
690 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
693 /** Device flow structure only for DV flow creation. */
694 struct mlx5_flow_dv_workspace {
695 uint32_t group; /**< The group index. */
696 uint32_t table_id; /**< Flow table identifier. */
697 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
698 int actions_n; /**< number of actions. */
699 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
700 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
701 /**< Pointer to encap/decap resource in cache. */
702 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
703 /**< Pointer to push VLAN action resource in cache. */
704 struct mlx5_flow_dv_tag_resource *tag_resource;
705 /**< pointer to the tag action. */
706 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
707 /**< Pointer to port ID action resource. */
708 struct mlx5_flow_dv_jump_tbl_resource *jump;
709 /**< Pointer to the jump action resource. */
710 struct mlx5_flow_dv_match_params value;
711 /**< Holds the value that the packet is compared to. */
712 struct mlx5_flow_dv_sample_resource *sample_res;
713 /**< Pointer to the sample action resource. */
714 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
715 /**< Pointer to the destination array resource. */
718 #ifdef HAVE_INFINIBAND_VERBS_H
720 * Maximal Verbs flow specifications & actions size.
721 * Some elements are mutually exclusive, but enough space should be allocated.
722 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
723 * 2. One tunnel header (exception: GRE + MPLS),
724 * SPEC length: GRE == tunnel.
725 * Actions: 1. 1 Mark OR Flag.
726 * 2. 1 Drop (if any).
727 * 3. No limitation for counters, but it makes no sense to support too
728 * many counters in a single device flow.
730 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
731 #define MLX5_VERBS_MAX_SPEC_SIZE \
733 (2 * (sizeof(struct ibv_flow_spec_eth) + \
734 sizeof(struct ibv_flow_spec_ipv6) + \
735 sizeof(struct ibv_flow_spec_tcp_udp)) + \
736 sizeof(struct ibv_flow_spec_gre) + \
737 sizeof(struct ibv_flow_spec_mpls)) \
740 #define MLX5_VERBS_MAX_SPEC_SIZE \
742 (2 * (sizeof(struct ibv_flow_spec_eth) + \
743 sizeof(struct ibv_flow_spec_ipv6) + \
744 sizeof(struct ibv_flow_spec_tcp_udp)) + \
745 sizeof(struct ibv_flow_spec_tunnel)) \
749 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
750 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
751 #define MLX5_VERBS_MAX_ACT_SIZE \
753 sizeof(struct ibv_flow_spec_action_tag) + \
754 sizeof(struct ibv_flow_spec_action_drop) + \
755 sizeof(struct ibv_flow_spec_counter_action) * 4 \
758 #define MLX5_VERBS_MAX_ACT_SIZE \
760 sizeof(struct ibv_flow_spec_action_tag) + \
761 sizeof(struct ibv_flow_spec_action_drop) \
765 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
766 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
768 /** Device flow structure only for Verbs flow creation. */
769 struct mlx5_flow_verbs_workspace {
770 unsigned int size; /**< Size of the attribute. */
771 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
772 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
773 /**< Specifications & actions buffer of verbs flow. */
775 #endif /* HAVE_INFINIBAND_VERBS_H */
777 #define MLX5_SCALE_FLOW_GROUP_BIT 0
778 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
780 /** Maximal number of device sub-flows supported. */
781 #define MLX5_NUM_MAX_DEV_FLOWS 32
783 /** Device flow structure. */
786 struct rte_flow *flow; /**< Pointer to the main flow. */
787 uint32_t flow_idx; /**< The memory pool index to the main flow. */
788 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
790 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
791 bool external; /**< true if the flow is created external to PMD. */
792 uint8_t ingress:1; /**< 1 if the flow is ingress. */
793 uint8_t skip_scale:2;
795 * Each Bit be set to 1 if Skip the scale the flow group with factor.
796 * If bit0 be set to 1, then skip the scale the original flow group;
797 * If bit1 be set to 1, then skip the scale the jump flow group if
798 * having jump action.
799 * 00: Enable scale in a flow, default value.
800 * 01: Skip scale the flow group with factor, enable scale the group
802 * 10: Enable scale the group with factor, skip scale the group of
804 * 11: Skip scale the table with factor both for flow group and jump
808 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
809 struct mlx5_flow_dv_workspace dv;
811 #ifdef HAVE_INFINIBAND_VERBS_H
812 struct mlx5_flow_verbs_workspace verbs;
815 struct mlx5_flow_handle *handle;
816 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
817 const struct mlx5_flow_tunnel *tunnel;
820 /* Flow meter state. */
821 #define MLX5_FLOW_METER_DISABLE 0
822 #define MLX5_FLOW_METER_ENABLE 1
824 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
825 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
827 #define MLX5_MAN_WIDTH 8
828 /* Legacy Meter parameter structure. */
829 struct mlx5_legacy_flow_meter {
830 struct mlx5_flow_meter_info fm;
831 /* Must be the first in struct. */
832 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
833 /**< Pointer to the next flow meter structure. */
836 uint32_t idx; /* Index to meter object. */
839 #define MLX5_MAX_TUNNELS 256
840 #define MLX5_TNL_MISS_RULE_PRIORITY 3
841 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
844 * When tunnel offload is active, all JUMP group ids are converted
845 * using the same method. That conversion is applied both to tunnel and
846 * regular rule types.
847 * Group ids used in tunnel rules are relative to it's tunnel (!).
848 * Application can create number of steer rules, using the same
849 * tunnel, with different group id in each rule.
850 * Each tunnel stores its groups internally in PMD tunnel object.
851 * Groups used in regular rules do not belong to any tunnel and are stored
855 struct mlx5_flow_tunnel {
856 LIST_ENTRY(mlx5_flow_tunnel) chain;
857 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
858 uint32_t tunnel_id; /** unique tunnel ID */
860 struct rte_flow_action action;
861 struct rte_flow_item item;
862 struct mlx5_hlist *groups; /** tunnel groups */
865 /** PMD tunnel related context */
866 struct mlx5_flow_tunnel_hub {
868 * Access to the list MUST be MT protected
870 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
871 /* protect access to the tunnels list */
873 struct mlx5_hlist *groups; /** non tunnel groups */
876 /* convert jump group to flow table ID in tunnel rules */
877 struct tunnel_tbl_entry {
878 struct mlx5_hlist_entry hash;
884 static inline uint32_t
885 tunnel_id_to_flow_tbl(uint32_t id)
887 return id | (1u << 16);
890 static inline uint32_t
891 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
893 return flow_tbl & ~(1u << 16);
896 union tunnel_tbl_key {
904 static inline struct mlx5_flow_tunnel_hub *
905 mlx5_tunnel_hub(struct rte_eth_dev *dev)
907 struct mlx5_priv *priv = dev->data->dev_private;
908 return priv->sh->tunnel_hub;
912 is_tunnel_offload_active(struct rte_eth_dev *dev)
914 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
915 struct mlx5_priv *priv = dev->data->dev_private;
916 return !!priv->config.dv_miss_info;
924 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
925 __rte_unused const struct rte_flow_attr *attr,
926 __rte_unused const struct rte_flow_item items[],
927 __rte_unused const struct rte_flow_action actions[])
929 return (items[0].type == (typeof(items[0].type))
930 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
934 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
935 __rte_unused const struct rte_flow_attr *attr,
936 __rte_unused const struct rte_flow_item items[],
937 __rte_unused const struct rte_flow_action actions[])
939 return (actions[0].type == (typeof(actions[0].type))
940 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
943 static inline const struct mlx5_flow_tunnel *
944 flow_actions_to_tunnel(const struct rte_flow_action actions[])
946 return actions[0].conf;
949 static inline const struct mlx5_flow_tunnel *
950 flow_items_to_tunnel(const struct rte_flow_item items[])
952 return items[0].spec;
955 /* Flow structure. */
957 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
958 uint32_t dev_handles;
959 /**< Device flow handles that are part of the flow. */
960 uint32_t drv_type:2; /**< Driver type. */
962 uint32_t meter:24; /**< Holds flow meter id. */
963 uint32_t rix_mreg_copy;
964 /**< Index to metadata register copy table resource. */
965 uint32_t counter; /**< Holds flow counter. */
966 uint32_t tunnel_id; /**< Tunnel id */
967 uint32_t age; /**< Holds ASO age bit index. */
968 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
972 * Define list of valid combinations of RX Hash fields
973 * (see enum ibv_rx_hash_fields).
975 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
976 #define MLX5_RSS_HASH_IPV4_TCP \
977 (MLX5_RSS_HASH_IPV4 | \
978 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
979 #define MLX5_RSS_HASH_IPV4_UDP \
980 (MLX5_RSS_HASH_IPV4 | \
981 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
982 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
983 #define MLX5_RSS_HASH_IPV6_TCP \
984 (MLX5_RSS_HASH_IPV6 | \
985 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
986 #define MLX5_RSS_HASH_IPV6_UDP \
987 (MLX5_RSS_HASH_IPV6 | \
988 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
989 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
990 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
991 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
992 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
993 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
994 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
995 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
996 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
997 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
998 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
999 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1000 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1001 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1002 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1003 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1004 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1005 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1006 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1007 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1008 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1009 #define MLX5_RSS_HASH_NONE 0ULL
1011 /* array of valid combinations of RX Hash fields for RSS */
1012 static const uint64_t mlx5_rss_hash_fields[] = {
1014 MLX5_RSS_HASH_IPV4_TCP,
1015 MLX5_RSS_HASH_IPV4_UDP,
1017 MLX5_RSS_HASH_IPV6_TCP,
1018 MLX5_RSS_HASH_IPV6_UDP,
1022 /* Shared RSS action structure */
1023 struct mlx5_shared_action_rss {
1024 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1025 uint32_t refcnt; /**< Atomically accessed refcnt. */
1026 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1027 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1028 struct mlx5_ind_table_obj *ind_tbl;
1029 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1030 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1031 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1032 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1035 struct rte_flow_action_handle {
1039 /* Thread specific flow workspace intermediate data. */
1040 struct mlx5_flow_workspace {
1041 /* If creating another flow in same thread, push new as stack. */
1042 struct mlx5_flow_workspace *prev;
1043 struct mlx5_flow_workspace *next;
1044 uint32_t inuse; /* can't create new flow with current. */
1045 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1046 struct mlx5_flow_rss_desc rss_desc;
1047 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1048 uint32_t flow_idx; /* Intermediate device flow index. */
1049 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1052 struct mlx5_flow_split_info {
1054 /**< True if flow is created by request external to PMD. */
1055 uint8_t skip_scale; /**< Skip the scale the table with factor. */
1056 uint32_t flow_idx; /**< This memory pool index to the flow. */
1057 uint32_t prefix_mark; /**< Prefix subflow mark flag. */
1058 uint64_t prefix_layers; /**< Prefix subflow layers. */
1059 uint32_t table_id; /**< Flow table identifier. */
1062 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1063 const struct rte_flow_attr *attr,
1064 const struct rte_flow_item items[],
1065 const struct rte_flow_action actions[],
1068 struct rte_flow_error *error);
1069 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1070 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1071 const struct rte_flow_item items[],
1072 const struct rte_flow_action actions[], struct rte_flow_error *error);
1073 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1074 struct mlx5_flow *dev_flow,
1075 const struct rte_flow_attr *attr,
1076 const struct rte_flow_item items[],
1077 const struct rte_flow_action actions[],
1078 struct rte_flow_error *error);
1079 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1080 struct rte_flow_error *error);
1081 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1082 struct rte_flow *flow);
1083 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1084 struct rte_flow *flow);
1085 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1086 struct rte_flow *flow,
1087 const struct rte_flow_action *actions,
1089 struct rte_flow_error *error);
1090 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1091 (struct rte_eth_dev *dev);
1092 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1093 struct mlx5_meter_domains_infos *tbls);
1094 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1095 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1096 (struct rte_eth_dev *dev);
1097 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1099 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1100 (struct rte_eth_dev *dev);
1101 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1103 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1105 bool clear, uint64_t *pkts,
1107 typedef int (*mlx5_flow_get_aged_flows_t)
1108 (struct rte_eth_dev *dev,
1110 uint32_t nb_contexts,
1111 struct rte_flow_error *error);
1112 typedef int (*mlx5_flow_action_validate_t)
1113 (struct rte_eth_dev *dev,
1114 const struct rte_flow_indir_action_conf *conf,
1115 const struct rte_flow_action *action,
1116 struct rte_flow_error *error);
1117 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1118 (struct rte_eth_dev *dev,
1119 const struct rte_flow_indir_action_conf *conf,
1120 const struct rte_flow_action *action,
1121 struct rte_flow_error *error);
1122 typedef int (*mlx5_flow_action_destroy_t)
1123 (struct rte_eth_dev *dev,
1124 struct rte_flow_action_handle *action,
1125 struct rte_flow_error *error);
1126 typedef int (*mlx5_flow_action_update_t)
1127 (struct rte_eth_dev *dev,
1128 struct rte_flow_action_handle *action,
1130 struct rte_flow_error *error);
1131 typedef int (*mlx5_flow_action_query_t)
1132 (struct rte_eth_dev *dev,
1133 const struct rte_flow_action_handle *action,
1135 struct rte_flow_error *error);
1136 typedef int (*mlx5_flow_sync_domain_t)
1137 (struct rte_eth_dev *dev,
1140 typedef int (*mlx5_flow_validate_mtr_acts_t)
1141 (struct rte_eth_dev *dev,
1142 const struct rte_flow_action *actions[RTE_COLORS],
1143 struct rte_flow_attr *attr,
1145 uint8_t *domain_bitmap,
1146 bool *is_def_policy,
1147 struct rte_mtr_error *error);
1148 typedef int (*mlx5_flow_create_mtr_acts_t)
1149 (struct rte_eth_dev *dev,
1150 struct mlx5_flow_meter_policy *mtr_policy,
1151 const struct rte_flow_action *actions[RTE_COLORS],
1152 struct rte_mtr_error *error);
1153 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1154 (struct rte_eth_dev *dev,
1155 struct mlx5_flow_meter_policy *mtr_policy);
1156 typedef int (*mlx5_flow_create_policy_rules_t)
1157 (struct rte_eth_dev *dev,
1158 struct mlx5_flow_meter_policy *mtr_policy);
1159 typedef void (*mlx5_flow_destroy_policy_rules_t)
1160 (struct rte_eth_dev *dev,
1161 struct mlx5_flow_meter_policy *mtr_policy);
1162 typedef int (*mlx5_flow_create_def_policy_t)
1163 (struct rte_eth_dev *dev);
1164 typedef void (*mlx5_flow_destroy_def_policy_t)
1165 (struct rte_eth_dev *dev);
1167 struct mlx5_flow_driver_ops {
1168 mlx5_flow_validate_t validate;
1169 mlx5_flow_prepare_t prepare;
1170 mlx5_flow_translate_t translate;
1171 mlx5_flow_apply_t apply;
1172 mlx5_flow_remove_t remove;
1173 mlx5_flow_destroy_t destroy;
1174 mlx5_flow_query_t query;
1175 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1176 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1177 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1178 mlx5_flow_mtr_alloc_t create_meter;
1179 mlx5_flow_mtr_free_t free_meter;
1180 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1181 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1182 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1183 mlx5_flow_create_policy_rules_t create_policy_rules;
1184 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1185 mlx5_flow_create_def_policy_t create_def_policy;
1186 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1187 mlx5_flow_counter_alloc_t counter_alloc;
1188 mlx5_flow_counter_free_t counter_free;
1189 mlx5_flow_counter_query_t counter_query;
1190 mlx5_flow_get_aged_flows_t get_aged_flows;
1191 mlx5_flow_action_validate_t action_validate;
1192 mlx5_flow_action_create_t action_create;
1193 mlx5_flow_action_destroy_t action_destroy;
1194 mlx5_flow_action_update_t action_update;
1195 mlx5_flow_action_query_t action_query;
1196 mlx5_flow_sync_domain_t sync_domain;
1201 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1203 struct flow_grp_info {
1204 uint64_t external:1;
1205 uint64_t transfer:1;
1206 uint64_t fdb_def_rule:1;
1207 /* force standard group translation */
1208 uint64_t std_tbl_fix:1;
1209 uint64_t skip_scale:2;
1213 tunnel_use_standard_attr_group_translate
1214 (struct rte_eth_dev *dev,
1215 const struct mlx5_flow_tunnel *tunnel,
1216 const struct rte_flow_attr *attr,
1217 const struct rte_flow_item items[],
1218 const struct rte_flow_action actions[])
1222 if (!is_tunnel_offload_active(dev))
1223 /* no tunnel offload API */
1227 * OvS will use jump to group 0 in tunnel steer rule.
1228 * If tunnel steer rule starts from group 0 (attr.group == 0)
1229 * that 0 group must be translated with standard method.
1230 * attr.group == 0 in tunnel match rule translated with tunnel
1233 verdict = !attr->group &&
1234 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1237 * non-tunnel group translation uses standard method for
1238 * root group only: attr.group == 0
1240 verdict = !attr->group;
1247 * Get DV flow aso meter by index.
1250 * Pointer to the Ethernet device structure.
1252 * mlx5 flow aso meter index in the container.
1254 * mlx5 flow aso meter pool in the container,
1257 * Pointer to the aso meter, NULL otherwise.
1259 static inline struct mlx5_aso_mtr *
1260 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1262 struct mlx5_aso_mtr_pool *pool;
1263 struct mlx5_aso_mtr_pools_mng *pools_mng =
1264 &priv->sh->mtrmng->pools_mng;
1266 /* Decrease to original index. */
1268 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1269 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1270 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1273 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1274 const struct mlx5_flow_tunnel *tunnel,
1275 uint32_t group, uint32_t *table,
1276 const struct flow_grp_info *flags,
1277 struct rte_flow_error *error);
1278 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1279 int tunnel, uint64_t layer_types,
1280 uint64_t hash_fields);
1281 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1282 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1283 uint32_t subpriority);
1284 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1285 const struct rte_flow_attr *attr);
1286 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1287 const struct rte_flow_attr *attr,
1288 uint32_t subpriority);
1289 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1290 enum mlx5_feature_name feature,
1292 struct rte_flow_error *error);
1293 const struct rte_flow_action *mlx5_flow_find_action
1294 (const struct rte_flow_action *actions,
1295 enum rte_flow_action_type action);
1296 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1297 const struct rte_flow_action *action,
1298 struct rte_flow_error *error);
1299 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1300 const struct rte_flow_attr *attr,
1301 struct rte_flow_error *error);
1302 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1303 const struct rte_flow_attr *attr,
1304 struct rte_flow_error *error);
1305 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1306 const struct rte_flow_attr *attr,
1307 struct rte_flow_error *error);
1308 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1309 uint64_t action_flags,
1310 const struct rte_flow_attr *attr,
1311 struct rte_flow_error *error);
1312 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1313 uint64_t action_flags,
1314 struct rte_eth_dev *dev,
1315 const struct rte_flow_attr *attr,
1316 struct rte_flow_error *error);
1317 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1318 uint64_t action_flags,
1319 struct rte_eth_dev *dev,
1320 const struct rte_flow_attr *attr,
1321 uint64_t item_flags,
1322 struct rte_flow_error *error);
1323 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1324 const struct rte_flow_attr *attr,
1325 struct rte_flow_error *error);
1326 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1327 const struct rte_flow_attr *attributes,
1328 struct rte_flow_error *error);
1329 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1330 const uint8_t *mask,
1331 const uint8_t *nic_mask,
1333 bool range_accepted,
1334 struct rte_flow_error *error);
1335 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1336 uint64_t item_flags, bool ext_vlan_sup,
1337 struct rte_flow_error *error);
1338 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1339 uint64_t item_flags,
1340 uint8_t target_protocol,
1341 struct rte_flow_error *error);
1342 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1343 uint64_t item_flags,
1344 const struct rte_flow_item *gre_item,
1345 struct rte_flow_error *error);
1346 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1347 uint64_t item_flags,
1349 uint16_t ether_type,
1350 const struct rte_flow_item_ipv4 *acc_mask,
1351 bool range_accepted,
1352 struct rte_flow_error *error);
1353 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1354 uint64_t item_flags,
1356 uint16_t ether_type,
1357 const struct rte_flow_item_ipv6 *acc_mask,
1358 struct rte_flow_error *error);
1359 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1360 const struct rte_flow_item *item,
1361 uint64_t item_flags,
1362 uint64_t prev_layer,
1363 struct rte_flow_error *error);
1364 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1365 uint64_t item_flags,
1366 uint8_t target_protocol,
1367 const struct rte_flow_item_tcp *flow_mask,
1368 struct rte_flow_error *error);
1369 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1370 uint64_t item_flags,
1371 uint8_t target_protocol,
1372 struct rte_flow_error *error);
1373 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1374 uint64_t item_flags,
1375 struct rte_eth_dev *dev,
1376 struct rte_flow_error *error);
1377 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1378 uint64_t item_flags,
1379 struct rte_flow_error *error);
1380 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1381 uint64_t item_flags,
1382 struct rte_eth_dev *dev,
1383 struct rte_flow_error *error);
1384 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1385 uint64_t item_flags,
1386 uint8_t target_protocol,
1387 struct rte_flow_error *error);
1388 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1389 uint64_t item_flags,
1390 uint8_t target_protocol,
1391 struct rte_flow_error *error);
1392 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1393 uint64_t item_flags,
1394 uint8_t target_protocol,
1395 struct rte_flow_error *error);
1396 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1397 uint64_t item_flags,
1398 struct rte_eth_dev *dev,
1399 struct rte_flow_error *error);
1400 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1402 const struct rte_flow_item *geneve_item,
1403 struct rte_eth_dev *dev,
1404 struct rte_flow_error *error);
1405 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1406 uint64_t item_flags,
1408 uint16_t ether_type,
1409 const struct rte_flow_item_ecpri *acc_mask,
1410 struct rte_flow_error *error);
1411 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1412 (struct rte_eth_dev *dev);
1413 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1414 struct mlx5_meter_domains_infos *tbl);
1415 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1416 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1417 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1418 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1419 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1421 /* Hash list callbacks for flow tables: */
1422 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1423 uint64_t key, void *entry_ctx);
1424 int flow_dv_tbl_match_cb(struct mlx5_hlist *list,
1425 struct mlx5_hlist_entry *entry, uint64_t key,
1427 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1428 struct mlx5_hlist_entry *entry);
1429 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1430 uint32_t table_level, uint8_t egress, uint8_t transfer,
1431 bool external, const struct mlx5_flow_tunnel *tunnel,
1432 uint32_t group_id, uint8_t dummy,
1433 uint32_t table_id, struct rte_flow_error *error);
1435 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1436 uint64_t key, void *cb_ctx);
1437 int flow_dv_tag_match_cb(struct mlx5_hlist *list,
1438 struct mlx5_hlist_entry *entry, uint64_t key,
1440 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1441 struct mlx5_hlist_entry *entry);
1443 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1444 struct mlx5_hlist_entry *entry,
1445 uint64_t key, void *cb_ctx);
1446 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1447 uint64_t key, void *ctx);
1448 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1449 struct mlx5_hlist_entry *entry);
1451 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1452 uint64_t key, void *ctx);
1453 int flow_dv_mreg_match_cb(struct mlx5_hlist *list,
1454 struct mlx5_hlist_entry *entry, uint64_t key,
1456 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1457 struct mlx5_hlist_entry *entry);
1459 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1460 struct mlx5_hlist_entry *entry,
1461 uint64_t key, void *cb_ctx);
1462 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1463 uint64_t key, void *cb_ctx);
1464 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1465 struct mlx5_hlist_entry *entry);
1467 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1468 struct mlx5_cache_entry *entry, void *ctx);
1469 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1470 struct mlx5_cache_entry *entry, void *ctx);
1471 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1472 struct mlx5_cache_entry *entry);
1474 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1475 struct mlx5_cache_entry *entry, void *cb_ctx);
1476 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1477 struct mlx5_cache_entry *entry, void *cb_ctx);
1478 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1479 struct mlx5_cache_entry *entry);
1481 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1482 struct mlx5_cache_entry *entry, void *cb_ctx);
1483 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1484 (struct mlx5_cache_list *list,
1485 struct mlx5_cache_entry *entry, void *cb_ctx);
1486 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1487 struct mlx5_cache_entry *entry);
1489 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1490 struct mlx5_cache_entry *entry, void *cb_ctx);
1491 struct mlx5_cache_entry *flow_dv_sample_create_cb
1492 (struct mlx5_cache_list *list,
1493 struct mlx5_cache_entry *entry, void *cb_ctx);
1494 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1495 struct mlx5_cache_entry *entry);
1497 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1498 struct mlx5_cache_entry *entry, void *cb_ctx);
1499 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1500 (struct mlx5_cache_list *list,
1501 struct mlx5_cache_entry *entry, void *cb_ctx);
1502 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1503 struct mlx5_cache_entry *entry);
1504 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
1506 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
1507 const struct rte_flow_item *item,
1508 struct rte_flow_error *error);
1509 void flow_release_workspace(void *data);
1510 int mlx5_flow_os_init_workspace_once(void);
1511 void *mlx5_flow_os_get_specific_workspace(void);
1512 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
1513 void mlx5_flow_os_release_workspace(void);
1514 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
1515 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
1516 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
1517 const struct rte_flow_action *actions[RTE_COLORS],
1518 struct rte_flow_attr *attr,
1520 uint8_t *domain_bitmap,
1521 bool *is_def_policy,
1522 struct rte_mtr_error *error);
1523 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
1524 struct mlx5_flow_meter_policy *mtr_policy);
1525 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
1526 struct mlx5_flow_meter_policy *mtr_policy,
1527 const struct rte_flow_action *actions[RTE_COLORS],
1528 struct rte_mtr_error *error);
1529 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
1530 struct mlx5_flow_meter_policy *mtr_policy);
1531 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
1532 struct mlx5_flow_meter_policy *mtr_policy);
1533 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
1534 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
1535 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
1536 struct mlx5_flow_handle *dev_handle);
1537 #endif /* RTE_PMD_MLX5_FLOW_H_ */