1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Pattern outer Layer bits. */
31 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
32 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
33 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
34 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
35 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
36 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
38 /* Pattern inner Layer bits. */
39 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
40 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
41 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
42 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
43 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
44 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
46 /* Pattern tunnel Layer bits. */
47 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
48 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
49 #define MLX5_FLOW_LAYER_GRE (1u << 14)
50 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
52 /* General pattern items bits. */
53 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
54 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
56 /* Pattern MISC bits. */
57 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
58 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
59 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)
61 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
62 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
65 #define MLX5_FLOW_LAYER_OUTER_L3 \
66 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
67 #define MLX5_FLOW_LAYER_OUTER_L4 \
68 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
69 #define MLX5_FLOW_LAYER_OUTER \
70 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
71 MLX5_FLOW_LAYER_OUTER_L4)
74 #define MLX5_FLOW_LAYER_TUNNEL \
75 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
76 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS | \
77 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP)
80 #define MLX5_FLOW_LAYER_INNER_L3 \
81 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
82 #define MLX5_FLOW_LAYER_INNER_L4 \
83 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
84 #define MLX5_FLOW_LAYER_INNER \
85 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
86 MLX5_FLOW_LAYER_INNER_L4)
89 #define MLX5_FLOW_LAYER_L2 \
90 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
91 #define MLX5_FLOW_LAYER_L3_IPV4 \
92 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
93 #define MLX5_FLOW_LAYER_L3_IPV6 \
94 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
95 #define MLX5_FLOW_LAYER_L3 \
96 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
97 #define MLX5_FLOW_LAYER_L4 \
98 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
101 #define MLX5_FLOW_ACTION_DROP (1u << 0)
102 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
103 #define MLX5_FLOW_ACTION_RSS (1u << 2)
104 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
105 #define MLX5_FLOW_ACTION_MARK (1u << 4)
106 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
107 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
108 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
109 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
110 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
111 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
112 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
113 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
114 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
115 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
116 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
117 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
118 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
119 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
120 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
121 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
122 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
123 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
124 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
125 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
126 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
127 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
128 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
129 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
130 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
131 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
132 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
134 #define MLX5_FLOW_FATE_ACTIONS \
135 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
136 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
138 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
139 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
140 MLX5_FLOW_ACTION_JUMP)
142 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
143 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
144 MLX5_FLOW_ACTION_RAW_ENCAP)
146 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
147 MLX5_FLOW_ACTION_NVGRE_DECAP | \
148 MLX5_FLOW_ACTION_RAW_DECAP)
150 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
151 MLX5_FLOW_ACTION_SET_IPV4_DST | \
152 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
153 MLX5_FLOW_ACTION_SET_IPV6_DST | \
154 MLX5_FLOW_ACTION_SET_TP_SRC | \
155 MLX5_FLOW_ACTION_SET_TP_DST | \
156 MLX5_FLOW_ACTION_SET_TTL | \
157 MLX5_FLOW_ACTION_DEC_TTL | \
158 MLX5_FLOW_ACTION_SET_MAC_SRC | \
159 MLX5_FLOW_ACTION_SET_MAC_DST | \
160 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
161 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
162 MLX5_FLOW_ACTION_INC_TCP_ACK | \
163 MLX5_FLOW_ACTION_DEC_TCP_ACK)
166 #define IPPROTO_MPLS 137
169 /* UDP port number for MPLS */
170 #define MLX5_UDP_PORT_MPLS 6635
172 /* UDP port numbers for VxLAN. */
173 #define MLX5_UDP_PORT_VXLAN 4789
174 #define MLX5_UDP_PORT_VXLAN_GPE 4790
176 /* Priority reserved for default flows. */
177 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
180 * Number of sub priorities.
181 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
182 * matching on the NIC (firmware dependent) L4 most have the higher priority
183 * followed by L3 and ending with L2.
185 #define MLX5_PRIORITY_MAP_L2 2
186 #define MLX5_PRIORITY_MAP_L3 1
187 #define MLX5_PRIORITY_MAP_L4 0
188 #define MLX5_PRIORITY_MAP_MAX 3
190 /* Valid layer type for IPV4 RSS. */
191 #define MLX5_IPV4_LAYER_TYPES \
192 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
193 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
194 ETH_RSS_NONFRAG_IPV4_OTHER)
196 /* IBV hash source bits for IPV4. */
197 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
199 /* Valid layer type for IPV6 RSS. */
200 #define MLX5_IPV6_LAYER_TYPES \
201 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
202 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
203 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
205 /* IBV hash source bits for IPV6. */
206 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
208 enum mlx5_flow_drv_type {
211 MLX5_FLOW_TYPE_VERBS,
215 /* Matcher PRM representation */
216 struct mlx5_flow_dv_match_params {
218 /**< Size of match value. Do NOT split size and key! */
219 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
220 /**< Matcher value. This value is used as the mask or as a key. */
223 /* Matcher structure. */
224 struct mlx5_flow_dv_matcher {
225 LIST_ENTRY(mlx5_flow_dv_matcher) next;
226 /* Pointer to the next element. */
227 rte_atomic32_t refcnt; /**< Reference counter. */
228 void *matcher_object; /**< Pointer to DV matcher */
229 uint16_t crc; /**< CRC of key. */
230 uint16_t priority; /**< Priority of matcher. */
231 uint8_t egress; /**< Egress matcher. */
232 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
233 uint32_t group; /**< The matcher group. */
234 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
237 #define MLX5_ENCAP_MAX_LEN 132
239 /* Encap/decap resource structure. */
240 struct mlx5_flow_dv_encap_decap_resource {
241 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
242 /* Pointer to next element. */
243 rte_atomic32_t refcnt; /**< Reference counter. */
245 /**< Verbs encap/decap action object. */
246 uint8_t buf[MLX5_ENCAP_MAX_LEN];
248 uint8_t reformat_type;
250 uint64_t flags; /**< Flags for RDMA API. */
253 /* Tag resource structure. */
254 struct mlx5_flow_dv_tag_resource {
255 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
256 /* Pointer to next element. */
257 rte_atomic32_t refcnt; /**< Reference counter. */
259 /**< Verbs tag action object. */
260 uint32_t tag; /**< the tag value. */
263 /* Number of modification commands. */
264 #define MLX5_MODIFY_NUM 8
266 /* Modify resource structure */
267 struct mlx5_flow_dv_modify_hdr_resource {
268 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
269 /* Pointer to next element. */
270 rte_atomic32_t refcnt; /**< Reference counter. */
271 struct ibv_flow_action *verbs_action;
272 /**< Verbs modify header action object. */
273 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
274 uint32_t actions_num; /**< Number of modification actions. */
275 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
276 /**< Modification actions. */
277 uint64_t flags; /**< Flags for RDMA API. */
280 /* Jump action resource structure. */
281 struct mlx5_flow_dv_jump_tbl_resource {
282 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
283 /* Pointer to next element. */
284 rte_atomic32_t refcnt; /**< Reference counter. */
285 void *action; /**< Pointer to the rdma core action. */
286 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
287 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
290 /* Port ID resource structure. */
291 struct mlx5_flow_dv_port_id_action_resource {
292 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
293 /* Pointer to next element. */
294 rte_atomic32_t refcnt; /**< Reference counter. */
296 /**< Verbs tag action object. */
297 uint32_t port_id; /**< Port ID value. */
301 * Max number of actions per DV flow.
302 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
303 * In rdma-core file providers/mlx5/verbs.c
305 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
307 /* DV flows structure. */
308 struct mlx5_flow_dv {
309 uint64_t hash_fields; /**< Fields that participate in the hash. */
310 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
312 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
313 struct mlx5_flow_dv_match_params value;
314 /**< Holds the value that the packet is compared to. */
315 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
316 /**< Pointer to encap/decap resource in cache. */
317 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
318 /**< Pointer to modify header resource in cache. */
319 struct ibv_flow *flow; /**< Installed flow. */
320 struct mlx5_flow_dv_jump_tbl_resource *jump;
321 /**< Pointer to the jump action resource. */
322 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
323 /**< Pointer to port ID action resource. */
324 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
325 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
328 int actions_n; /**< number of actions. */
331 /* Verbs specification header. */
332 struct ibv_spec_header {
333 enum ibv_flow_spec_type type;
337 /** Handles information leading to a drop fate. */
338 struct mlx5_flow_verbs {
339 LIST_ENTRY(mlx5_flow_verbs) next;
340 unsigned int size; /**< Size of the attribute. */
342 struct ibv_flow_attr *attr;
343 /**< Pointer to the Specification buffer. */
344 uint8_t *specs; /**< Pointer to the specifications. */
346 struct ibv_flow *flow; /**< Verbs flow pointer. */
347 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
348 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
351 /** Device flow structure. */
353 LIST_ENTRY(mlx5_flow) next;
354 struct rte_flow *flow; /**< Pointer to the main flow. */
356 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
358 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
359 struct mlx5_flow_dv dv;
361 struct mlx5_flow_verbs verbs;
365 /* Flow structure. */
367 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
368 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
369 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
370 struct mlx5_flow_dv_tag_resource *tag_resource;
371 /**< pointer to the tag action. */
372 struct rte_flow_action_rss rss;/**< RSS context. */
373 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
374 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
375 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
376 /**< Device flows that are part of the flow. */
378 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
379 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
380 uint8_t ingress; /**< 1 if the flow is ingress. */
381 uint32_t group; /**< The group index. */
382 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
385 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
386 const struct rte_flow_attr *attr,
387 const struct rte_flow_item items[],
388 const struct rte_flow_action actions[],
389 struct rte_flow_error *error);
390 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
391 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
392 const struct rte_flow_action actions[], struct rte_flow_error *error);
393 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
394 struct mlx5_flow *dev_flow,
395 const struct rte_flow_attr *attr,
396 const struct rte_flow_item items[],
397 const struct rte_flow_action actions[],
398 struct rte_flow_error *error);
399 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
400 struct rte_flow_error *error);
401 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
402 struct rte_flow *flow);
403 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
404 struct rte_flow *flow);
405 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
406 struct rte_flow *flow,
407 const struct rte_flow_action *actions,
409 struct rte_flow_error *error);
410 struct mlx5_flow_driver_ops {
411 mlx5_flow_validate_t validate;
412 mlx5_flow_prepare_t prepare;
413 mlx5_flow_translate_t translate;
414 mlx5_flow_apply_t apply;
415 mlx5_flow_remove_t remove;
416 mlx5_flow_destroy_t destroy;
417 mlx5_flow_query_t query;
420 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
421 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
422 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
423 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
427 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
428 uint64_t layer_types,
429 uint64_t hash_fields);
430 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
431 uint32_t subpriority);
432 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
433 const struct rte_flow_attr *attr,
434 struct rte_flow_error *error);
435 int mlx5_flow_validate_action_drop(uint64_t action_flags,
436 const struct rte_flow_attr *attr,
437 struct rte_flow_error *error);
438 int mlx5_flow_validate_action_flag(uint64_t action_flags,
439 const struct rte_flow_attr *attr,
440 struct rte_flow_error *error);
441 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
442 uint64_t action_flags,
443 const struct rte_flow_attr *attr,
444 struct rte_flow_error *error);
445 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
446 uint64_t action_flags,
447 struct rte_eth_dev *dev,
448 const struct rte_flow_attr *attr,
449 struct rte_flow_error *error);
450 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
451 uint64_t action_flags,
452 struct rte_eth_dev *dev,
453 const struct rte_flow_attr *attr,
455 struct rte_flow_error *error);
456 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
457 const struct rte_flow_attr *attributes,
458 struct rte_flow_error *error);
459 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
461 const uint8_t *nic_mask,
463 struct rte_flow_error *error);
464 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
466 struct rte_flow_error *error);
467 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
469 uint8_t target_protocol,
470 struct rte_flow_error *error);
471 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
473 const struct rte_flow_item *gre_item,
474 struct rte_flow_error *error);
475 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
477 const struct rte_flow_item_ipv4 *acc_mask,
478 struct rte_flow_error *error);
479 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
481 const struct rte_flow_item_ipv6 *acc_mask,
482 struct rte_flow_error *error);
483 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
484 const struct rte_flow_item *item,
487 struct rte_flow_error *error);
488 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
490 uint8_t target_protocol,
491 const struct rte_flow_item_tcp *flow_mask,
492 struct rte_flow_error *error);
493 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
495 uint8_t target_protocol,
496 struct rte_flow_error *error);
497 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
499 struct rte_flow_error *error);
500 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
502 struct rte_flow_error *error);
503 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
505 struct rte_eth_dev *dev,
506 struct rte_flow_error *error);
507 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
509 uint8_t target_protocol,
510 struct rte_flow_error *error);
511 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
513 uint8_t target_protocol,
514 struct rte_flow_error *error);
516 #endif /* RTE_PMD_MLX5_FLOW_H_ */