1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
43 /* Private rte flow items. */
44 enum mlx5_rte_flow_item_type {
45 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
46 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
47 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
50 /* Private rte flow actions. */
51 enum mlx5_rte_flow_action_type {
52 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
53 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
56 /* Matches on selected register. */
57 struct mlx5_rte_flow_item_tag {
62 /* Modify selected register. */
63 struct mlx5_rte_flow_action_set_tag {
68 /* Matches on source queue. */
69 struct mlx5_rte_flow_item_tx_queue {
73 /* Pattern outer Layer bits. */
74 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
75 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
76 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
77 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
78 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
79 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
81 /* Pattern inner Layer bits. */
82 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
83 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
84 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
85 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
86 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
87 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
89 /* Pattern tunnel Layer bits. */
90 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
91 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
92 #define MLX5_FLOW_LAYER_GRE (1u << 14)
93 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
94 /* List of tunnel Layer bits continued below. */
96 /* General pattern items bits. */
97 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
98 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
99 #define MLX5_FLOW_ITEM_TAG (1u << 18)
101 /* Pattern MISC bits. */
102 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
103 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
104 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
106 /* Pattern tunnel Layer bits (continued). */
107 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
108 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
109 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
110 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
113 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
116 #define MLX5_FLOW_LAYER_OUTER_L3 \
117 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
118 #define MLX5_FLOW_LAYER_OUTER_L4 \
119 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
120 #define MLX5_FLOW_LAYER_OUTER \
121 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
122 MLX5_FLOW_LAYER_OUTER_L4)
124 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
125 #define MLX5_FLOW_LAYER_IPV4_LRO \
126 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
127 #define MLX5_FLOW_LAYER_IPV6_LRO \
128 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
131 #define MLX5_FLOW_LAYER_TUNNEL \
132 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
133 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
134 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
135 MLX5_FLOW_LAYER_GENEVE)
138 #define MLX5_FLOW_LAYER_INNER_L3 \
139 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
140 #define MLX5_FLOW_LAYER_INNER_L4 \
141 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
142 #define MLX5_FLOW_LAYER_INNER \
143 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
144 MLX5_FLOW_LAYER_INNER_L4)
147 #define MLX5_FLOW_LAYER_L2 \
148 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
149 #define MLX5_FLOW_LAYER_L3_IPV4 \
150 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
151 #define MLX5_FLOW_LAYER_L3_IPV6 \
152 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
153 #define MLX5_FLOW_LAYER_L3 \
154 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
155 #define MLX5_FLOW_LAYER_L4 \
156 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
159 #define MLX5_FLOW_ACTION_DROP (1u << 0)
160 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
161 #define MLX5_FLOW_ACTION_RSS (1u << 2)
162 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
163 #define MLX5_FLOW_ACTION_MARK (1u << 4)
164 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
165 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
166 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
167 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
168 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
169 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
170 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
171 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
172 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
173 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
174 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
175 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
176 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
177 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
178 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
179 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
180 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
181 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
182 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
183 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
184 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
185 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
186 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
187 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
188 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
189 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
190 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
191 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
193 #define MLX5_FLOW_FATE_ACTIONS \
194 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
195 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
197 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
198 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
199 MLX5_FLOW_ACTION_JUMP)
201 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
202 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
203 MLX5_FLOW_ACTION_RAW_ENCAP | \
204 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
206 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
207 MLX5_FLOW_ACTION_NVGRE_DECAP | \
208 MLX5_FLOW_ACTION_RAW_DECAP | \
209 MLX5_FLOW_ACTION_OF_POP_VLAN)
211 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
212 MLX5_FLOW_ACTION_SET_IPV4_DST | \
213 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
214 MLX5_FLOW_ACTION_SET_IPV6_DST | \
215 MLX5_FLOW_ACTION_SET_TP_SRC | \
216 MLX5_FLOW_ACTION_SET_TP_DST | \
217 MLX5_FLOW_ACTION_SET_TTL | \
218 MLX5_FLOW_ACTION_DEC_TTL | \
219 MLX5_FLOW_ACTION_SET_MAC_SRC | \
220 MLX5_FLOW_ACTION_SET_MAC_DST | \
221 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
222 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
223 MLX5_FLOW_ACTION_INC_TCP_ACK | \
224 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
225 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
226 MLX5_FLOW_ACTION_SET_TAG)
228 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
229 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
232 #define IPPROTO_MPLS 137
235 /* UDP port number for MPLS */
236 #define MLX5_UDP_PORT_MPLS 6635
238 /* UDP port numbers for VxLAN. */
239 #define MLX5_UDP_PORT_VXLAN 4789
240 #define MLX5_UDP_PORT_VXLAN_GPE 4790
242 /* UDP port numbers for GENEVE. */
243 #define MLX5_UDP_PORT_GENEVE 6081
245 /* Priority reserved for default flows. */
246 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
249 * Number of sub priorities.
250 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
251 * matching on the NIC (firmware dependent) L4 most have the higher priority
252 * followed by L3 and ending with L2.
254 #define MLX5_PRIORITY_MAP_L2 2
255 #define MLX5_PRIORITY_MAP_L3 1
256 #define MLX5_PRIORITY_MAP_L4 0
257 #define MLX5_PRIORITY_MAP_MAX 3
259 /* Valid layer type for IPV4 RSS. */
260 #define MLX5_IPV4_LAYER_TYPES \
261 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
262 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
263 ETH_RSS_NONFRAG_IPV4_OTHER)
265 /* IBV hash source bits for IPV4. */
266 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
268 /* Valid layer type for IPV6 RSS. */
269 #define MLX5_IPV6_LAYER_TYPES \
270 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
271 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
272 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
274 /* IBV hash source bits for IPV6. */
275 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
278 /* Geneve header first 16Bit */
279 #define MLX5_GENEVE_VER_MASK 0x3
280 #define MLX5_GENEVE_VER_SHIFT 14
281 #define MLX5_GENEVE_VER_VAL(a) \
282 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
283 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
284 #define MLX5_GENEVE_OPTLEN_SHIFT 7
285 #define MLX5_GENEVE_OPTLEN_VAL(a) \
286 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
287 #define MLX5_GENEVE_OAMF_MASK 0x1
288 #define MLX5_GENEVE_OAMF_SHIFT 7
289 #define MLX5_GENEVE_OAMF_VAL(a) \
290 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
291 #define MLX5_GENEVE_CRITO_MASK 0x1
292 #define MLX5_GENEVE_CRITO_SHIFT 6
293 #define MLX5_GENEVE_CRITO_VAL(a) \
294 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
295 #define MLX5_GENEVE_RSVD_MASK 0x3F
296 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
298 * The length of the Geneve options fields, expressed in four byte multiples,
299 * not including the eight byte fixed tunnel.
301 #define MLX5_GENEVE_OPT_LEN_0 14
302 #define MLX5_GENEVE_OPT_LEN_1 63
304 enum mlx5_flow_drv_type {
307 MLX5_FLOW_TYPE_VERBS,
311 /* Matcher PRM representation */
312 struct mlx5_flow_dv_match_params {
314 /**< Size of match value. Do NOT split size and key! */
315 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
316 /**< Matcher value. This value is used as the mask or as a key. */
319 /* Matcher structure. */
320 struct mlx5_flow_dv_matcher {
321 LIST_ENTRY(mlx5_flow_dv_matcher) next;
322 /* Pointer to the next element. */
323 rte_atomic32_t refcnt; /**< Reference counter. */
324 void *matcher_object; /**< Pointer to DV matcher */
325 uint16_t crc; /**< CRC of key. */
326 uint16_t priority; /**< Priority of matcher. */
327 uint8_t egress; /**< Egress matcher. */
328 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
329 uint32_t group; /**< The matcher group. */
330 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
333 #define MLX5_ENCAP_MAX_LEN 132
335 /* Encap/decap resource structure. */
336 struct mlx5_flow_dv_encap_decap_resource {
337 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
338 /* Pointer to next element. */
339 rte_atomic32_t refcnt; /**< Reference counter. */
341 /**< Verbs encap/decap action object. */
342 uint8_t buf[MLX5_ENCAP_MAX_LEN];
344 uint8_t reformat_type;
346 uint64_t flags; /**< Flags for RDMA API. */
349 /* Tag resource structure. */
350 struct mlx5_flow_dv_tag_resource {
351 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
352 /* Pointer to next element. */
353 rte_atomic32_t refcnt; /**< Reference counter. */
355 /**< Verbs tag action object. */
356 uint32_t tag; /**< the tag value. */
359 /* Number of modification commands. */
360 #define MLX5_MODIFY_NUM 8
362 /* Modify resource structure */
363 struct mlx5_flow_dv_modify_hdr_resource {
364 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
365 /* Pointer to next element. */
366 rte_atomic32_t refcnt; /**< Reference counter. */
367 struct ibv_flow_action *verbs_action;
368 /**< Verbs modify header action object. */
369 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
370 uint32_t actions_num; /**< Number of modification actions. */
371 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
372 /**< Modification actions. */
373 uint64_t flags; /**< Flags for RDMA API. */
376 /* Jump action resource structure. */
377 struct mlx5_flow_dv_jump_tbl_resource {
378 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
379 /* Pointer to next element. */
380 rte_atomic32_t refcnt; /**< Reference counter. */
381 void *action; /**< Pointer to the rdma core action. */
382 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
383 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
386 /* Port ID resource structure. */
387 struct mlx5_flow_dv_port_id_action_resource {
388 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
389 /* Pointer to next element. */
390 rte_atomic32_t refcnt; /**< Reference counter. */
392 /**< Verbs tag action object. */
393 uint32_t port_id; /**< Port ID value. */
396 /* Push VLAN action resource structure */
397 struct mlx5_flow_dv_push_vlan_action_resource {
398 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
399 /* Pointer to next element. */
400 rte_atomic32_t refcnt; /**< Reference counter. */
401 void *action; /**< Direct verbs action object. */
402 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
403 rte_be32_t vlan_tag; /**< VLAN tag value. */
407 * Max number of actions per DV flow.
408 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
409 * In rdma-core file providers/mlx5/verbs.c
411 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
413 /* DV flows structure. */
414 struct mlx5_flow_dv {
415 uint64_t hash_fields; /**< Fields that participate in the hash. */
416 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
418 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
419 struct mlx5_flow_dv_match_params value;
420 /**< Holds the value that the packet is compared to. */
421 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
422 /**< Pointer to encap/decap resource in cache. */
423 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
424 /**< Pointer to modify header resource in cache. */
425 struct ibv_flow *flow; /**< Installed flow. */
426 struct mlx5_flow_dv_jump_tbl_resource *jump;
427 /**< Pointer to the jump action resource. */
428 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
429 /**< Pointer to port ID action resource. */
430 struct mlx5_vf_vlan vf_vlan;
431 /**< Structure for VF VLAN workaround. */
432 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
433 /**< Pointer to push VLAN action resource in cache. */
434 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
435 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
438 int actions_n; /**< number of actions. */
441 /* Verbs specification header. */
442 struct ibv_spec_header {
443 enum ibv_flow_spec_type type;
447 /** Handles information leading to a drop fate. */
448 struct mlx5_flow_verbs {
449 LIST_ENTRY(mlx5_flow_verbs) next;
450 unsigned int size; /**< Size of the attribute. */
452 struct ibv_flow_attr *attr;
453 /**< Pointer to the Specification buffer. */
454 uint8_t *specs; /**< Pointer to the specifications. */
456 struct ibv_flow *flow; /**< Verbs flow pointer. */
457 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
458 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
459 struct mlx5_vf_vlan vf_vlan;
460 /**< Structure for VF VLAN workaround. */
463 /** Device flow structure. */
465 LIST_ENTRY(mlx5_flow) next;
466 struct rte_flow *flow; /**< Pointer to the main flow. */
468 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
470 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
472 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
473 struct mlx5_flow_dv dv;
475 struct mlx5_flow_verbs verbs;
477 bool external; /**< true if the flow is created external to PMD. */
480 /* Flow structure. */
482 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
483 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
484 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
485 struct mlx5_flow_dv_tag_resource *tag_resource;
486 /**< pointer to the tag action. */
487 struct rte_flow_action_rss rss;/**< RSS context. */
488 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
489 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
490 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
491 /**< Device flows that are part of the flow. */
492 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
493 uint8_t ingress; /**< 1 if the flow is ingress. */
494 uint32_t group; /**< The group index. */
495 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
496 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
499 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
500 const struct rte_flow_attr *attr,
501 const struct rte_flow_item items[],
502 const struct rte_flow_action actions[],
504 struct rte_flow_error *error);
505 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
506 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
507 const struct rte_flow_action actions[], struct rte_flow_error *error);
508 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
509 struct mlx5_flow *dev_flow,
510 const struct rte_flow_attr *attr,
511 const struct rte_flow_item items[],
512 const struct rte_flow_action actions[],
513 struct rte_flow_error *error);
514 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
515 struct rte_flow_error *error);
516 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
517 struct rte_flow *flow);
518 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
519 struct rte_flow *flow);
520 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
521 struct rte_flow *flow,
522 const struct rte_flow_action *actions,
524 struct rte_flow_error *error);
525 struct mlx5_flow_driver_ops {
526 mlx5_flow_validate_t validate;
527 mlx5_flow_prepare_t prepare;
528 mlx5_flow_translate_t translate;
529 mlx5_flow_apply_t apply;
530 mlx5_flow_remove_t remove;
531 mlx5_flow_destroy_t destroy;
532 mlx5_flow_query_t query;
535 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
536 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
537 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
538 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
542 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
543 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
544 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
545 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
547 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
548 bool external, uint32_t group, uint32_t *table,
549 struct rte_flow_error *error);
550 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
551 uint64_t layer_types,
552 uint64_t hash_fields);
553 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
554 uint32_t subpriority);
555 const struct rte_flow_action *mlx5_flow_find_action
556 (const struct rte_flow_action *actions,
557 enum rte_flow_action_type action);
558 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
559 const struct rte_flow_attr *attr,
560 struct rte_flow_error *error);
561 int mlx5_flow_validate_action_drop(uint64_t action_flags,
562 const struct rte_flow_attr *attr,
563 struct rte_flow_error *error);
564 int mlx5_flow_validate_action_flag(uint64_t action_flags,
565 const struct rte_flow_attr *attr,
566 struct rte_flow_error *error);
567 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
568 uint64_t action_flags,
569 const struct rte_flow_attr *attr,
570 struct rte_flow_error *error);
571 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
572 uint64_t action_flags,
573 struct rte_eth_dev *dev,
574 const struct rte_flow_attr *attr,
575 struct rte_flow_error *error);
576 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
577 uint64_t action_flags,
578 struct rte_eth_dev *dev,
579 const struct rte_flow_attr *attr,
581 struct rte_flow_error *error);
582 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
583 const struct rte_flow_attr *attributes,
584 struct rte_flow_error *error);
585 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
587 const uint8_t *nic_mask,
589 struct rte_flow_error *error);
590 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
592 struct rte_flow_error *error);
593 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
595 uint8_t target_protocol,
596 struct rte_flow_error *error);
597 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
599 const struct rte_flow_item *gre_item,
600 struct rte_flow_error *error);
601 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
605 const struct rte_flow_item_ipv4 *acc_mask,
606 struct rte_flow_error *error);
607 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
611 const struct rte_flow_item_ipv6 *acc_mask,
612 struct rte_flow_error *error);
613 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
614 const struct rte_flow_item *item,
617 struct rte_flow_error *error);
618 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
620 uint8_t target_protocol,
621 const struct rte_flow_item_tcp *flow_mask,
622 struct rte_flow_error *error);
623 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
625 uint8_t target_protocol,
626 struct rte_flow_error *error);
627 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
629 struct rte_eth_dev *dev,
630 struct rte_flow_error *error);
631 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
633 struct rte_flow_error *error);
634 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
636 struct rte_eth_dev *dev,
637 struct rte_flow_error *error);
638 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
640 uint8_t target_protocol,
641 struct rte_flow_error *error);
642 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
644 uint8_t target_protocol,
645 struct rte_flow_error *error);
646 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
648 uint8_t target_protocol,
649 struct rte_flow_error *error);
650 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
652 struct rte_eth_dev *dev,
653 struct rte_flow_error *error);
654 #endif /* RTE_PMD_MLX5_FLOW_H_ */