1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
11 #include <sys/queue.h>
13 #include <rte_alarm.h>
16 #include <mlx5_glue.h>
21 /* E-Switch Manager port, used for rte_flow_item_port_id. */
22 #define MLX5_PORT_ESW_MGR UINT32_MAX
24 /* Private rte flow items. */
25 enum mlx5_rte_flow_item_type {
26 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
27 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
28 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
29 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
30 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
33 /* Private (internal) rte flow actions. */
34 enum mlx5_rte_flow_action_type {
35 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
36 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
37 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
38 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
39 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
41 MLX5_RTE_FLOW_ACTION_TYPE_AGE,
42 MLX5_RTE_FLOW_ACTION_TYPE_COUNT,
43 MLX5_RTE_FLOW_ACTION_TYPE_JUMP,
44 MLX5_RTE_FLOW_ACTION_TYPE_RSS,
47 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30
50 MLX5_INDIRECT_ACTION_TYPE_RSS,
51 MLX5_INDIRECT_ACTION_TYPE_AGE,
52 MLX5_INDIRECT_ACTION_TYPE_COUNT,
53 MLX5_INDIRECT_ACTION_TYPE_CT,
56 /* Now, the maximal ports will be supported is 256, action number is 4M. */
57 #define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100
59 #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22
60 #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)
62 /* 30-31: type, 22-29: owner port, 0-21: index. */
63 #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \
64 ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \
65 (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \
66 MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index))
68 #define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \
69 (((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \
70 MLX5_INDIRECT_ACT_CT_OWNER_MASK)
72 #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \
73 ((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))
75 /* Matches on selected register. */
76 struct mlx5_rte_flow_item_tag {
81 /* Modify selected register. */
82 struct mlx5_rte_flow_action_set_tag {
89 struct mlx5_flow_action_copy_mreg {
94 /* Matches on source queue. */
95 struct mlx5_rte_flow_item_tx_queue {
99 /* Feature name to allocate metadata register. */
100 enum mlx5_feature_name {
116 /* Default queue number. */
117 #define MLX5_RSSQ_DEFAULT_NUM 16
119 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
120 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
121 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
122 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
123 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
124 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
126 /* Pattern inner Layer bits. */
127 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
128 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
129 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
130 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
131 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
132 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
134 /* Pattern tunnel Layer bits. */
135 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
136 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
137 #define MLX5_FLOW_LAYER_GRE (1u << 14)
138 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
139 /* List of tunnel Layer bits continued below. */
141 /* General pattern items bits. */
142 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
143 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
144 #define MLX5_FLOW_ITEM_TAG (1u << 18)
145 #define MLX5_FLOW_ITEM_MARK (1u << 19)
147 /* Pattern MISC bits. */
148 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
149 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
150 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
152 /* Pattern tunnel Layer bits (continued). */
153 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
154 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
155 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
156 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
159 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
161 /* Pattern tunnel Layer bits (continued). */
162 #define MLX5_FLOW_LAYER_GTP (1u << 28)
164 /* Pattern eCPRI Layer bit. */
165 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
167 /* IPv6 Fragment Extension Header bit. */
168 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
169 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
171 /* Pattern tunnel Layer bits (continued). */
172 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
173 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
175 /* INTEGRITY item bits */
176 #define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34)
177 #define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35)
178 #define MLX5_FLOW_ITEM_INTEGRITY \
179 (MLX5_FLOW_ITEM_OUTER_INTEGRITY | MLX5_FLOW_ITEM_INNER_INTEGRITY)
181 /* Conntrack item. */
182 #define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36)
185 #define MLX5_FLOW_ITEM_OUTER_FLEX (UINT64_C(1) << 37)
186 #define MLX5_FLOW_ITEM_INNER_FLEX (UINT64_C(1) << 38)
187 #define MLX5_FLOW_ITEM_FLEX_TUNNEL (UINT64_C(1) << 39)
190 #define MLX5_FLOW_ITEM_ESP (UINT64_C(1) << 40)
193 #define MLX5_FLOW_LAYER_OUTER_L3 \
194 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
195 #define MLX5_FLOW_LAYER_OUTER_L4 \
196 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
197 #define MLX5_FLOW_LAYER_OUTER \
198 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
199 MLX5_FLOW_LAYER_OUTER_L4)
202 #define MLX5_FLOW_LAYER_TUNNEL \
203 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
204 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
205 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
206 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP | \
207 MLX5_FLOW_ITEM_FLEX_TUNNEL)
210 #define MLX5_FLOW_LAYER_INNER_L3 \
211 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
212 #define MLX5_FLOW_LAYER_INNER_L4 \
213 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
214 #define MLX5_FLOW_LAYER_INNER \
215 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
216 MLX5_FLOW_LAYER_INNER_L4)
219 #define MLX5_FLOW_LAYER_L2 \
220 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
221 #define MLX5_FLOW_LAYER_L3_IPV4 \
222 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
223 #define MLX5_FLOW_LAYER_L3_IPV6 \
224 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
225 #define MLX5_FLOW_LAYER_L3 \
226 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
227 #define MLX5_FLOW_LAYER_L4 \
228 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
231 #define MLX5_FLOW_ACTION_DROP (1u << 0)
232 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
233 #define MLX5_FLOW_ACTION_RSS (1u << 2)
234 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
235 #define MLX5_FLOW_ACTION_MARK (1u << 4)
236 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
237 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
238 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
239 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
240 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
241 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
242 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
243 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
244 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
245 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
246 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
247 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
248 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
249 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
250 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
251 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
252 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
253 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
254 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
255 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
256 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
257 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
258 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
259 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
260 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
261 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
262 #define MLX5_FLOW_ACTION_METER (1ull << 31)
263 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
264 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
265 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
266 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
267 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
268 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
269 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
270 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39)
271 #define MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY (1ull << 40)
272 #define MLX5_FLOW_ACTION_CT (1ull << 41)
274 #define MLX5_FLOW_FATE_ACTIONS \
275 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
276 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
277 MLX5_FLOW_ACTION_DEFAULT_MISS | \
278 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
280 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
281 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
282 MLX5_FLOW_ACTION_JUMP | MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
284 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
285 MLX5_FLOW_ACTION_SET_IPV4_DST | \
286 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
287 MLX5_FLOW_ACTION_SET_IPV6_DST | \
288 MLX5_FLOW_ACTION_SET_TP_SRC | \
289 MLX5_FLOW_ACTION_SET_TP_DST | \
290 MLX5_FLOW_ACTION_SET_TTL | \
291 MLX5_FLOW_ACTION_DEC_TTL | \
292 MLX5_FLOW_ACTION_SET_MAC_SRC | \
293 MLX5_FLOW_ACTION_SET_MAC_DST | \
294 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
295 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
296 MLX5_FLOW_ACTION_INC_TCP_ACK | \
297 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
298 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
299 MLX5_FLOW_ACTION_SET_TAG | \
300 MLX5_FLOW_ACTION_MARK_EXT | \
301 MLX5_FLOW_ACTION_SET_META | \
302 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
303 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \
304 MLX5_FLOW_ACTION_MODIFY_FIELD)
306 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
307 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
309 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
312 #define IPPROTO_MPLS 137
315 /* UDP port number for MPLS */
316 #define MLX5_UDP_PORT_MPLS 6635
318 /* UDP port numbers for VxLAN. */
319 #define MLX5_UDP_PORT_VXLAN 4789
320 #define MLX5_UDP_PORT_VXLAN_GPE 4790
322 /* UDP port numbers for GENEVE. */
323 #define MLX5_UDP_PORT_GENEVE 6081
325 /* Lowest priority indicator. */
326 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1)
329 * Max priority for ingress\egress flow groups
330 * greater than 0 and for any transfer flow group.
331 * From user configation: 0 - 21843.
333 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1)
336 * Number of sub priorities.
337 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
338 * matching on the NIC (firmware dependent) L4 most have the higher priority
339 * followed by L3 and ending with L2.
341 #define MLX5_PRIORITY_MAP_L2 2
342 #define MLX5_PRIORITY_MAP_L3 1
343 #define MLX5_PRIORITY_MAP_L4 0
344 #define MLX5_PRIORITY_MAP_MAX 3
346 /* Valid layer type for IPV4 RSS. */
347 #define MLX5_IPV4_LAYER_TYPES \
348 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \
349 RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
350 RTE_ETH_RSS_NONFRAG_IPV4_OTHER)
352 /* IBV hash source bits for IPV4. */
353 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
355 /* Valid layer type for IPV6 RSS. */
356 #define MLX5_IPV6_LAYER_TYPES \
357 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
358 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | \
359 RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER)
361 /* IBV hash source bits for IPV6. */
362 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
364 /* IBV hash bits for L3 SRC. */
365 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
367 /* IBV hash bits for L3 DST. */
368 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
370 /* IBV hash bits for TCP. */
371 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
372 IBV_RX_HASH_DST_PORT_TCP)
374 /* IBV hash bits for UDP. */
375 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
376 IBV_RX_HASH_DST_PORT_UDP)
378 /* IBV hash bits for L4 SRC. */
379 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
380 IBV_RX_HASH_SRC_PORT_UDP)
382 /* IBV hash bits for L4 DST. */
383 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
384 IBV_RX_HASH_DST_PORT_UDP)
386 /* Geneve header first 16Bit */
387 #define MLX5_GENEVE_VER_MASK 0x3
388 #define MLX5_GENEVE_VER_SHIFT 14
389 #define MLX5_GENEVE_VER_VAL(a) \
390 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
391 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
392 #define MLX5_GENEVE_OPTLEN_SHIFT 8
393 #define MLX5_GENEVE_OPTLEN_VAL(a) \
394 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
395 #define MLX5_GENEVE_OAMF_MASK 0x1
396 #define MLX5_GENEVE_OAMF_SHIFT 7
397 #define MLX5_GENEVE_OAMF_VAL(a) \
398 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
399 #define MLX5_GENEVE_CRITO_MASK 0x1
400 #define MLX5_GENEVE_CRITO_SHIFT 6
401 #define MLX5_GENEVE_CRITO_VAL(a) \
402 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
403 #define MLX5_GENEVE_RSVD_MASK 0x3F
404 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
406 * The length of the Geneve options fields, expressed in four byte multiples,
407 * not including the eight byte fixed tunnel.
409 #define MLX5_GENEVE_OPT_LEN_0 14
410 #define MLX5_GENEVE_OPT_LEN_1 63
412 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \
413 sizeof(struct rte_ipv4_hdr))
414 /* GTP extension header flag. */
415 #define MLX5_GTP_EXT_HEADER_FLAG 4
417 /* GTP extension header PDU type shift. */
418 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4)
420 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
421 #define MLX5_IPV4_FRAG_OFFSET_MASK \
422 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
424 /* Specific item's fields can accept a range of values (using spec and last). */
425 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
426 #define MLX5_ITEM_RANGE_ACCEPTED true
428 /* Software header modify action numbers of a flow. */
429 #define MLX5_ACT_NUM_MDF_IPV4 1
430 #define MLX5_ACT_NUM_MDF_IPV6 4
431 #define MLX5_ACT_NUM_MDF_MAC 2
432 #define MLX5_ACT_NUM_MDF_VID 1
433 #define MLX5_ACT_NUM_MDF_PORT 1
434 #define MLX5_ACT_NUM_MDF_TTL 1
435 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
436 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
437 #define MLX5_ACT_NUM_MDF_TCPACK 1
438 #define MLX5_ACT_NUM_SET_REG 1
439 #define MLX5_ACT_NUM_SET_TAG 1
440 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
441 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
442 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
443 #define MLX5_ACT_NUM_SET_DSCP 1
445 /* Maximum number of fields to modify in MODIFY_FIELD */
446 #define MLX5_ACT_MAX_MOD_FIELDS 5
448 /* Syndrome bits definition for connection tracking. */
449 #define MLX5_CT_SYNDROME_VALID (0x0 << 6)
450 #define MLX5_CT_SYNDROME_INVALID (0x1 << 6)
451 #define MLX5_CT_SYNDROME_TRAP (0x2 << 6)
452 #define MLX5_CT_SYNDROME_STATE_CHANGE (0x1 << 1)
453 #define MLX5_CT_SYNDROME_BAD_PACKET (0x1 << 0)
455 enum mlx5_flow_drv_type {
458 MLX5_FLOW_TYPE_VERBS,
463 /* Fate action type. */
464 enum mlx5_flow_fate_type {
465 MLX5_FLOW_FATE_NONE, /* Egress flow. */
466 MLX5_FLOW_FATE_QUEUE,
468 MLX5_FLOW_FATE_PORT_ID,
470 MLX5_FLOW_FATE_DEFAULT_MISS,
471 MLX5_FLOW_FATE_SHARED_RSS,
476 /* Matcher PRM representation */
477 struct mlx5_flow_dv_match_params {
479 /**< Size of match value. Do NOT split size and key! */
480 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
481 /**< Matcher value. This value is used as the mask or as a key. */
484 /* Matcher structure. */
485 struct mlx5_flow_dv_matcher {
486 struct mlx5_list_entry entry; /**< Pointer to the next element. */
487 struct mlx5_flow_tbl_resource *tbl;
488 /**< Pointer to the table(group) the matcher associated with. */
489 void *matcher_object; /**< Pointer to DV matcher */
490 uint16_t crc; /**< CRC of key. */
491 uint16_t priority; /**< Priority of matcher. */
492 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
495 #define MLX5_ENCAP_MAX_LEN 132
497 /* Encap/decap resource structure. */
498 struct mlx5_flow_dv_encap_decap_resource {
499 struct mlx5_list_entry entry;
500 /* Pointer to next element. */
501 uint32_t refcnt; /**< Reference counter. */
503 /**< Encap/decap action object. */
504 uint8_t buf[MLX5_ENCAP_MAX_LEN];
506 uint8_t reformat_type;
508 uint64_t flags; /**< Flags for RDMA API. */
509 uint32_t idx; /**< Index for the index memory pool. */
512 /* Tag resource structure. */
513 struct mlx5_flow_dv_tag_resource {
514 struct mlx5_list_entry entry;
515 /**< hash list entry for tag resource, tag value as the key. */
517 /**< Tag action object. */
518 uint32_t refcnt; /**< Reference counter. */
519 uint32_t idx; /**< Index for the index memory pool. */
520 uint32_t tag_id; /**< Tag ID. */
523 /* Modify resource structure */
524 struct mlx5_flow_dv_modify_hdr_resource {
525 struct mlx5_list_entry entry;
526 void *action; /**< Modify header action object. */
528 /* Key area for hash list matching: */
529 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
530 uint8_t actions_num; /**< Number of modification actions. */
531 bool root; /**< Whether action is in root table. */
532 struct mlx5_modification_cmd actions[];
533 /**< Modification actions. */
536 /* Modify resource key of the hash organization. */
537 union mlx5_flow_modify_hdr_key {
539 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
540 uint32_t actions_num:5; /**< Number of modification actions. */
541 uint32_t group:19; /**< Flow group id. */
542 uint32_t cksum; /**< Actions check sum. */
544 uint64_t v64; /**< full 64bits value of key */
547 /* Jump action resource structure. */
548 struct mlx5_flow_dv_jump_tbl_resource {
549 void *action; /**< Pointer to the rdma core action. */
552 /* Port ID resource structure. */
553 struct mlx5_flow_dv_port_id_action_resource {
554 struct mlx5_list_entry entry;
555 void *action; /**< Action object. */
556 uint32_t port_id; /**< Port ID value. */
557 uint32_t idx; /**< Indexed pool memory index. */
560 /* Push VLAN action resource structure */
561 struct mlx5_flow_dv_push_vlan_action_resource {
562 struct mlx5_list_entry entry; /* Cache entry. */
563 void *action; /**< Action object. */
564 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
565 rte_be32_t vlan_tag; /**< VLAN tag value. */
566 uint32_t idx; /**< Indexed pool memory index. */
569 /* Metadata register copy table entry. */
570 struct mlx5_flow_mreg_copy_resource {
572 * Hash list entry for copy table.
573 * - Key is 32/64-bit MARK action ID.
574 * - MUST be the first entry.
576 struct mlx5_list_entry hlist_ent;
577 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
578 /* List entry for device flows. */
580 uint32_t rix_flow; /* Built flow for copy. */
584 /* Table tunnel parameter. */
585 struct mlx5_flow_tbl_tunnel_prm {
586 const struct mlx5_flow_tunnel *tunnel;
591 /* Table data structure of the hash organization. */
592 struct mlx5_flow_tbl_data_entry {
593 struct mlx5_list_entry entry;
594 /**< hash list entry, 64-bits key inside. */
595 struct mlx5_flow_tbl_resource tbl;
596 /**< flow table resource. */
597 struct mlx5_list *matchers;
598 /**< matchers' header associated with the flow table. */
599 struct mlx5_flow_dv_jump_tbl_resource jump;
600 /**< jump resource, at most one for each table created. */
601 uint32_t idx; /**< index for the indexed mempool. */
602 /**< tunnel offload */
603 const struct mlx5_flow_tunnel *tunnel;
606 uint32_t tunnel_offload:1; /* Tunnel offload table or not. */
607 uint32_t is_egress:1; /**< Egress table. */
608 uint32_t is_transfer:1; /**< Transfer table. */
609 uint32_t dummy:1; /**< DR table. */
610 uint32_t id:22; /**< Table ID. */
611 uint32_t reserve:5; /**< Reserved to future using. */
612 uint32_t level; /**< Table level. */
615 /* Sub rdma-core actions list. */
616 struct mlx5_flow_sub_actions_list {
617 uint32_t actions_num; /**< Number of sample actions. */
618 uint64_t action_flags;
619 void *dr_queue_action;
622 void *dr_port_id_action;
623 void *dr_encap_action;
624 void *dr_jump_action;
627 /* Sample sub-actions resource list. */
628 struct mlx5_flow_sub_actions_idx {
629 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
630 uint32_t rix_tag; /**< Index to the tag action. */
631 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
632 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
633 uint32_t rix_jump; /**< Index to the jump action resource. */
636 /* Sample action resource structure. */
637 struct mlx5_flow_dv_sample_resource {
638 struct mlx5_list_entry entry; /**< Cache entry. */
640 void *verbs_action; /**< Verbs sample action object. */
641 void **sub_actions; /**< Sample sub-action array. */
643 struct rte_eth_dev *dev; /**< Device registers the action. */
644 uint32_t idx; /** Sample object index. */
645 uint8_t ft_type; /** Flow Table Type */
646 uint32_t ft_id; /** Flow Table Level */
647 uint32_t ratio; /** Sample Ratio */
648 uint64_t set_action; /** Restore reg_c0 value */
649 void *normal_path_tbl; /** Flow Table pointer */
650 struct mlx5_flow_sub_actions_idx sample_idx;
651 /**< Action index resources. */
652 struct mlx5_flow_sub_actions_list sample_act;
653 /**< Action resources. */
656 #define MLX5_MAX_DEST_NUM 2
658 /* Destination array action resource structure. */
659 struct mlx5_flow_dv_dest_array_resource {
660 struct mlx5_list_entry entry; /**< Cache entry. */
661 uint32_t idx; /** Destination array action object index. */
662 uint8_t ft_type; /** Flow Table Type */
663 uint8_t num_of_dest; /**< Number of destination actions. */
664 struct rte_eth_dev *dev; /**< Device registers the action. */
665 void *action; /**< Pointer to the rdma core action. */
666 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
667 /**< Action index resources. */
668 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
669 /**< Action resources. */
672 /* PMD flow priority for tunnel */
673 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
674 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
677 /** Device flow handle structure for DV mode only. */
678 struct mlx5_flow_handle_dv {
680 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
681 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
682 /**< Pointer to modify header resource in cache. */
683 uint32_t rix_encap_decap;
684 /**< Index to encap/decap resource in cache. */
685 uint32_t rix_push_vlan;
686 /**< Index to push VLAN action resource in cache. */
688 /**< Index to the tag action. */
690 /**< Index to sample action resource in cache. */
691 uint32_t rix_dest_array;
692 /**< Index to destination array resource in cache. */
695 /** Device flow handle structure: used both for creating & destroying. */
696 struct mlx5_flow_handle {
697 SILIST_ENTRY(uint32_t)next;
698 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
699 /**< Index to next device flow handle. */
701 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
702 void *drv_flow; /**< pointer to driver flow object. */
703 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */
704 uint32_t is_meter_flow_id:1; /**< Indicate if flow_id is for meter. */
705 uint32_t fate_action:3; /**< Fate action type. */
707 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
708 uint32_t rix_jump; /**< Index to the jump action resource. */
709 uint32_t rix_port_id_action;
710 /**< Index to port ID action resource. */
712 /**< Generic value indicates the fate action. */
713 uint32_t rix_default_fate;
714 /**< Indicates default miss fate action. */
716 /**< Indicates shared RSS fate action. */
718 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
719 struct mlx5_flow_handle_dv dvh;
721 uint8_t flex_item; /**< referenced Flex Item bitmask. */
725 * Size for Verbs device flow handle structure only. Do not use the DV only
726 * structure in Verbs. No DV flows attributes will be accessed.
727 * Macro offsetof() could also be used here.
729 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
730 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
731 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
733 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
736 /** Device flow structure only for DV flow creation. */
737 struct mlx5_flow_dv_workspace {
738 uint32_t group; /**< The group index. */
739 uint32_t table_id; /**< Flow table identifier. */
740 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
741 int actions_n; /**< number of actions. */
742 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
743 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
744 /**< Pointer to encap/decap resource in cache. */
745 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
746 /**< Pointer to push VLAN action resource in cache. */
747 struct mlx5_flow_dv_tag_resource *tag_resource;
748 /**< pointer to the tag action. */
749 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
750 /**< Pointer to port ID action resource. */
751 struct mlx5_flow_dv_jump_tbl_resource *jump;
752 /**< Pointer to the jump action resource. */
753 struct mlx5_flow_dv_match_params value;
754 /**< Holds the value that the packet is compared to. */
755 struct mlx5_flow_dv_sample_resource *sample_res;
756 /**< Pointer to the sample action resource. */
757 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
758 /**< Pointer to the destination array resource. */
761 #ifdef HAVE_INFINIBAND_VERBS_H
763 * Maximal Verbs flow specifications & actions size.
764 * Some elements are mutually exclusive, but enough space should be allocated.
765 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
766 * 2. One tunnel header (exception: GRE + MPLS),
767 * SPEC length: GRE == tunnel.
768 * Actions: 1. 1 Mark OR Flag.
769 * 2. 1 Drop (if any).
770 * 3. No limitation for counters, but it makes no sense to support too
771 * many counters in a single device flow.
773 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
774 #define MLX5_VERBS_MAX_SPEC_SIZE \
776 (2 * (sizeof(struct ibv_flow_spec_eth) + \
777 sizeof(struct ibv_flow_spec_ipv6) + \
778 sizeof(struct ibv_flow_spec_tcp_udp)) + \
779 sizeof(struct ibv_flow_spec_gre) + \
780 sizeof(struct ibv_flow_spec_mpls)) \
783 #define MLX5_VERBS_MAX_SPEC_SIZE \
785 (2 * (sizeof(struct ibv_flow_spec_eth) + \
786 sizeof(struct ibv_flow_spec_ipv6) + \
787 sizeof(struct ibv_flow_spec_tcp_udp)) + \
788 sizeof(struct ibv_flow_spec_tunnel)) \
792 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
793 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
794 #define MLX5_VERBS_MAX_ACT_SIZE \
796 sizeof(struct ibv_flow_spec_action_tag) + \
797 sizeof(struct ibv_flow_spec_action_drop) + \
798 sizeof(struct ibv_flow_spec_counter_action) * 4 \
801 #define MLX5_VERBS_MAX_ACT_SIZE \
803 sizeof(struct ibv_flow_spec_action_tag) + \
804 sizeof(struct ibv_flow_spec_action_drop) \
808 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
809 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
811 /** Device flow structure only for Verbs flow creation. */
812 struct mlx5_flow_verbs_workspace {
813 unsigned int size; /**< Size of the attribute. */
814 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
815 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
816 /**< Specifications & actions buffer of verbs flow. */
818 #endif /* HAVE_INFINIBAND_VERBS_H */
820 #define MLX5_SCALE_FLOW_GROUP_BIT 0
821 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1
823 /** Maximal number of device sub-flows supported. */
824 #define MLX5_NUM_MAX_DEV_FLOWS 32
827 * tunnel offload rules type
829 enum mlx5_tof_rule_type {
830 MLX5_TUNNEL_OFFLOAD_NONE = 0,
831 MLX5_TUNNEL_OFFLOAD_SET_RULE,
832 MLX5_TUNNEL_OFFLOAD_MATCH_RULE,
833 MLX5_TUNNEL_OFFLOAD_MISS_RULE,
836 /** Device flow structure. */
839 struct rte_flow *flow; /**< Pointer to the main flow. */
840 uint32_t flow_idx; /**< The memory pool index to the main flow. */
841 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
843 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
844 bool external; /**< true if the flow is created external to PMD. */
845 uint8_t ingress:1; /**< 1 if the flow is ingress. */
846 uint8_t skip_scale:2;
848 * Each Bit be set to 1 if Skip the scale the flow group with factor.
849 * If bit0 be set to 1, then skip the scale the original flow group;
850 * If bit1 be set to 1, then skip the scale the jump flow group if
851 * having jump action.
852 * 00: Enable scale in a flow, default value.
853 * 01: Skip scale the flow group with factor, enable scale the group
855 * 10: Enable scale the group with factor, skip scale the group of
857 * 11: Skip scale the table with factor both for flow group and jump
861 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
862 struct mlx5_flow_dv_workspace dv;
864 #ifdef HAVE_INFINIBAND_VERBS_H
865 struct mlx5_flow_verbs_workspace verbs;
868 struct mlx5_flow_handle *handle;
869 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
870 const struct mlx5_flow_tunnel *tunnel;
871 enum mlx5_tof_rule_type tof_type;
874 /* Flow meter state. */
875 #define MLX5_FLOW_METER_DISABLE 0
876 #define MLX5_FLOW_METER_ENABLE 1
878 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u
879 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u
881 #define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES
883 #define MLX5_MAN_WIDTH 8
884 /* Legacy Meter parameter structure. */
885 struct mlx5_legacy_flow_meter {
886 struct mlx5_flow_meter_info fm;
887 /* Must be the first in struct. */
888 TAILQ_ENTRY(mlx5_legacy_flow_meter) next;
889 /**< Pointer to the next flow meter structure. */
891 /* Index to meter object. */
894 #define MLX5_MAX_TUNNELS 256
895 #define MLX5_TNL_MISS_RULE_PRIORITY 3
896 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
899 * When tunnel offload is active, all JUMP group ids are converted
900 * using the same method. That conversion is applied both to tunnel and
901 * regular rule types.
902 * Group ids used in tunnel rules are relative to it's tunnel (!).
903 * Application can create number of steer rules, using the same
904 * tunnel, with different group id in each rule.
905 * Each tunnel stores its groups internally in PMD tunnel object.
906 * Groups used in regular rules do not belong to any tunnel and are stored
910 struct mlx5_flow_tunnel {
911 LIST_ENTRY(mlx5_flow_tunnel) chain;
912 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
913 uint32_t tunnel_id; /** unique tunnel ID */
915 struct rte_flow_action action;
916 struct rte_flow_item item;
917 struct mlx5_hlist *groups; /** tunnel groups */
920 /** PMD tunnel related context */
921 struct mlx5_flow_tunnel_hub {
923 * Access to the list MUST be MT protected
925 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
926 /* protect access to the tunnels list */
928 struct mlx5_hlist *groups; /** non tunnel groups */
931 /* convert jump group to flow table ID in tunnel rules */
932 struct tunnel_tbl_entry {
933 struct mlx5_list_entry hash;
939 static inline uint32_t
940 tunnel_id_to_flow_tbl(uint32_t id)
942 return id | (1u << 16);
945 static inline uint32_t
946 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
948 return flow_tbl & ~(1u << 16);
951 union tunnel_tbl_key {
959 static inline struct mlx5_flow_tunnel_hub *
960 mlx5_tunnel_hub(struct rte_eth_dev *dev)
962 struct mlx5_priv *priv = dev->data->dev_private;
963 return priv->sh->tunnel_hub;
967 is_tunnel_offload_active(const struct rte_eth_dev *dev)
969 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
970 const struct mlx5_priv *priv = dev->data->dev_private;
971 return !!priv->sh->config.dv_miss_info;
979 is_flow_tunnel_match_rule(enum mlx5_tof_rule_type tof_rule_type)
981 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE;
985 is_flow_tunnel_steer_rule(enum mlx5_tof_rule_type tof_rule_type)
987 return tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE;
990 static inline const struct mlx5_flow_tunnel *
991 flow_actions_to_tunnel(const struct rte_flow_action actions[])
993 return actions[0].conf;
996 static inline const struct mlx5_flow_tunnel *
997 flow_items_to_tunnel(const struct rte_flow_item items[])
999 return items[0].spec;
1002 /* Flow structure. */
1004 uint32_t dev_handles;
1005 /**< Device flow handles that are part of the flow. */
1007 uint32_t drv_type:2; /**< Driver type. */
1009 uint32_t meter:24; /**< Holds flow meter id. */
1010 uint32_t indirect_type:2; /**< Indirect action type. */
1011 uint32_t rix_mreg_copy;
1012 /**< Index to metadata register copy table resource. */
1013 uint32_t counter; /**< Holds flow counter. */
1014 uint32_t tunnel_id; /**< Tunnel id */
1016 uint32_t age; /**< Holds ASO age bit index. */
1017 uint32_t ct; /**< Holds ASO CT index. */
1019 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */
1022 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1024 /* HWS flow struct. */
1025 struct rte_flow_hw {
1026 uint32_t idx; /* Flow index from indexed pool. */
1027 uint32_t fate_type; /* Fate action type. */
1030 struct mlx5_hw_jump_action *jump;
1031 struct mlx5_hrxq *hrxq; /* TIR action. */
1033 struct rte_flow_template_table *table; /* The table flow allcated from. */
1034 struct mlx5dr_rule rule; /* HWS layer data struct. */
1037 /* rte flow action translate to DR action struct. */
1038 struct mlx5_action_construct_data {
1039 LIST_ENTRY(mlx5_action_construct_data) next;
1040 /* Ensure the action types are matched. */
1042 uint32_t idx; /* Data index. */
1043 uint16_t action_src; /* rte_flow_action src offset. */
1044 uint16_t action_dst; /* mlx5dr_rule_action dst offset. */
1047 /* encap src(item) offset. */
1049 /* encap dst data offset. */
1051 /* encap data len. */
1055 uint64_t types; /* RSS hash types. */
1056 uint32_t level; /* RSS level. */
1057 uint32_t idx; /* Shared action index. */
1062 /* Flow item template struct. */
1063 struct rte_flow_pattern_template {
1064 LIST_ENTRY(rte_flow_pattern_template) next;
1065 /* Template attributes. */
1066 struct rte_flow_pattern_template_attr attr;
1067 struct mlx5dr_match_template *mt; /* mlx5 match template. */
1068 uint64_t item_flags; /* Item layer flags. */
1069 uint32_t refcnt; /* Reference counter. */
1072 /* Flow action template struct. */
1073 struct rte_flow_actions_template {
1074 LIST_ENTRY(rte_flow_actions_template) next;
1075 /* Template attributes. */
1076 struct rte_flow_actions_template_attr attr;
1077 struct rte_flow_action *actions; /* Cached flow actions. */
1078 struct rte_flow_action *masks; /* Cached action masks.*/
1079 uint32_t refcnt; /* Reference counter. */
1082 /* Jump action struct. */
1083 struct mlx5_hw_jump_action {
1084 /* Action jump from root. */
1085 struct mlx5dr_action *root_action;
1086 /* HW steering jump action. */
1087 struct mlx5dr_action *hws_action;
1090 /* Encap decap action struct. */
1091 struct mlx5_hw_encap_decap_action {
1092 struct mlx5dr_action *action; /* Action object. */
1093 size_t data_size; /* Action metadata size. */
1094 uint8_t data[]; /* Action data. */
1097 /* The maximum actions support in the flow. */
1098 #define MLX5_HW_MAX_ACTS 16
1100 /* DR action set struct. */
1101 struct mlx5_hw_actions {
1102 /* Dynamic action list. */
1103 LIST_HEAD(act_list, mlx5_action_construct_data) act_list;
1104 struct mlx5_hw_jump_action *jump; /* Jump action. */
1105 struct mlx5_hrxq *tir; /* TIR action. */
1106 /* Encap/Decap action. */
1107 struct mlx5_hw_encap_decap_action *encap_decap;
1108 uint16_t encap_decap_pos; /* Encap/Decap action position. */
1109 uint32_t acts_num:4; /* Total action number. */
1110 uint32_t mark:1; /* Indicate the mark action. */
1111 /* Translated DR action array from action template. */
1112 struct mlx5dr_rule_action rule_acts[MLX5_HW_MAX_ACTS];
1115 /* mlx5 action template struct. */
1116 struct mlx5_hw_action_template {
1117 /* Action template pointer. */
1118 struct rte_flow_actions_template *action_template;
1119 struct mlx5_hw_actions acts; /* Template actions. */
1122 /* mlx5 flow group struct. */
1123 struct mlx5_flow_group {
1124 struct mlx5_list_entry entry;
1125 struct mlx5dr_table *tbl; /* HWS table object. */
1126 struct mlx5_hw_jump_action jump; /* Jump action. */
1127 enum mlx5dr_table_type type; /* Table type. */
1128 uint32_t group_id; /* Group id. */
1129 uint32_t idx; /* Group memory index. */
1133 #define MLX5_HW_TBL_MAX_ITEM_TEMPLATE 2
1134 #define MLX5_HW_TBL_MAX_ACTION_TEMPLATE 32
1136 struct rte_flow_template_table {
1137 LIST_ENTRY(rte_flow_template_table) next;
1138 struct mlx5_flow_group *grp; /* The group rte_flow_template_table uses. */
1139 struct mlx5dr_matcher *matcher; /* Template matcher. */
1140 /* Item templates bind to the table. */
1141 struct rte_flow_pattern_template *its[MLX5_HW_TBL_MAX_ITEM_TEMPLATE];
1142 /* Action templates bind to the table. */
1143 struct mlx5_hw_action_template ats[MLX5_HW_TBL_MAX_ACTION_TEMPLATE];
1144 struct mlx5_indexed_pool *flow; /* The table's flow ipool. */
1145 uint32_t type; /* Flow table type RX/TX/FDB. */
1146 uint8_t nb_item_templates; /* Item template number. */
1147 uint8_t nb_action_templates; /* Action template number. */
1148 uint32_t refcnt; /* Table reference counter. */
1154 * Define list of valid combinations of RX Hash fields
1155 * (see enum ibv_rx_hash_fields).
1157 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1158 #define MLX5_RSS_HASH_IPV4_TCP \
1159 (MLX5_RSS_HASH_IPV4 | \
1160 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1161 #define MLX5_RSS_HASH_IPV4_UDP \
1162 (MLX5_RSS_HASH_IPV4 | \
1163 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1164 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1165 #define MLX5_RSS_HASH_IPV6_TCP \
1166 (MLX5_RSS_HASH_IPV6 | \
1167 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)
1168 #define MLX5_RSS_HASH_IPV6_UDP \
1169 (MLX5_RSS_HASH_IPV6 | \
1170 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP)
1171 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4
1172 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4
1173 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6
1174 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6
1175 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \
1176 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP)
1177 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \
1178 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP)
1179 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \
1180 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP)
1181 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \
1182 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP)
1183 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \
1184 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP)
1185 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \
1186 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP)
1187 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \
1188 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP)
1189 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \
1190 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP)
1192 #ifndef HAVE_IBV_RX_HASH_IPSEC_SPI
1193 #define IBV_RX_HASH_IPSEC_SPI (1U << 8)
1196 #define MLX5_RSS_HASH_ESP_SPI IBV_RX_HASH_IPSEC_SPI
1197 #define MLX5_RSS_HASH_IPV4_ESP (MLX5_RSS_HASH_IPV4 | \
1198 MLX5_RSS_HASH_ESP_SPI)
1199 #define MLX5_RSS_HASH_IPV6_ESP (MLX5_RSS_HASH_IPV6 | \
1200 MLX5_RSS_HASH_ESP_SPI)
1201 #define MLX5_RSS_HASH_NONE 0ULL
1204 /* extract next protocol type from Ethernet & VLAN headers */
1205 #define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \
1206 (_prt) = ((const struct _s *)(_itm)->mask)->_m; \
1207 (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \
1208 (_prt) = rte_be_to_cpu_16((_prt)); \
1211 /* array of valid combinations of RX Hash fields for RSS */
1212 static const uint64_t mlx5_rss_hash_fields[] = {
1214 MLX5_RSS_HASH_IPV4_TCP,
1215 MLX5_RSS_HASH_IPV4_UDP,
1216 MLX5_RSS_HASH_IPV4_ESP,
1218 MLX5_RSS_HASH_IPV6_TCP,
1219 MLX5_RSS_HASH_IPV6_UDP,
1220 MLX5_RSS_HASH_IPV6_ESP,
1221 MLX5_RSS_HASH_ESP_SPI,
1225 /* Shared RSS action structure */
1226 struct mlx5_shared_action_rss {
1227 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1228 uint32_t refcnt; /**< Atomically accessed refcnt. */
1229 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1230 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1231 struct mlx5_ind_table_obj *ind_tbl;
1232 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
1233 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1234 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1235 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
1238 struct rte_flow_action_handle {
1242 /* Thread specific flow workspace intermediate data. */
1243 struct mlx5_flow_workspace {
1244 /* If creating another flow in same thread, push new as stack. */
1245 struct mlx5_flow_workspace *prev;
1246 struct mlx5_flow_workspace *next;
1247 uint32_t inuse; /* can't create new flow with current. */
1248 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1249 struct mlx5_flow_rss_desc rss_desc;
1250 uint32_t rssq_num; /* Allocated queue num in rss_desc. */
1251 uint32_t flow_idx; /* Intermediate device flow index. */
1252 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */
1253 struct mlx5_flow_meter_policy *policy;
1254 /* The meter policy used by meter in flow. */
1255 struct mlx5_flow_meter_policy *final_policy;
1256 /* The final policy when meter policy is hierarchy. */
1257 uint32_t skip_matcher_reg:1;
1258 /* Indicates if need to skip matcher register in translate. */
1259 uint32_t mark:1; /* Indicates if flow contains mark action. */
1262 struct mlx5_flow_split_info {
1263 uint32_t external:1;
1264 /**< True if flow is created by request external to PMD. */
1265 uint32_t prefix_mark:1; /**< Prefix subflow mark flag. */
1266 uint32_t skip_scale:8; /**< Skip the scale the table with factor. */
1267 uint32_t flow_idx; /**< This memory pool index to the flow. */
1268 uint32_t table_id; /**< Flow table identifier. */
1269 uint64_t prefix_layers; /**< Prefix subflow layers. */
1272 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1273 const struct rte_flow_attr *attr,
1274 const struct rte_flow_item items[],
1275 const struct rte_flow_action actions[],
1278 struct rte_flow_error *error);
1279 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1280 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1281 const struct rte_flow_item items[],
1282 const struct rte_flow_action actions[], struct rte_flow_error *error);
1283 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1284 struct mlx5_flow *dev_flow,
1285 const struct rte_flow_attr *attr,
1286 const struct rte_flow_item items[],
1287 const struct rte_flow_action actions[],
1288 struct rte_flow_error *error);
1289 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1290 struct rte_flow_error *error);
1291 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1292 struct rte_flow *flow);
1293 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1294 struct rte_flow *flow);
1295 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1296 struct rte_flow *flow,
1297 const struct rte_flow_action *actions,
1299 struct rte_flow_error *error);
1300 typedef int (*mlx5_flow_create_mtr_tbls_t)(struct rte_eth_dev *dev,
1301 struct mlx5_flow_meter_info *fm,
1303 uint8_t domain_bitmap);
1304 typedef void (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1305 struct mlx5_flow_meter_info *fm);
1306 typedef void (*mlx5_flow_destroy_mtr_drop_tbls_t)(struct rte_eth_dev *dev);
1307 typedef struct mlx5_flow_meter_sub_policy *
1308 (*mlx5_flow_meter_sub_policy_rss_prepare_t)
1309 (struct rte_eth_dev *dev,
1310 struct mlx5_flow_meter_policy *mtr_policy,
1311 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1312 typedef int (*mlx5_flow_meter_hierarchy_rule_create_t)
1313 (struct rte_eth_dev *dev,
1314 struct mlx5_flow_meter_info *fm,
1316 const struct rte_flow_item *item,
1317 struct rte_flow_error *error);
1318 typedef void (*mlx5_flow_destroy_sub_policy_with_rxq_t)
1319 (struct rte_eth_dev *dev,
1320 struct mlx5_flow_meter_policy *mtr_policy);
1321 typedef uint32_t (*mlx5_flow_mtr_alloc_t)
1322 (struct rte_eth_dev *dev);
1323 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev,
1325 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1326 (struct rte_eth_dev *dev);
1327 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1329 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1331 bool clear, uint64_t *pkts,
1332 uint64_t *bytes, void **action);
1333 typedef int (*mlx5_flow_get_aged_flows_t)
1334 (struct rte_eth_dev *dev,
1336 uint32_t nb_contexts,
1337 struct rte_flow_error *error);
1338 typedef int (*mlx5_flow_action_validate_t)
1339 (struct rte_eth_dev *dev,
1340 const struct rte_flow_indir_action_conf *conf,
1341 const struct rte_flow_action *action,
1342 struct rte_flow_error *error);
1343 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t)
1344 (struct rte_eth_dev *dev,
1345 const struct rte_flow_indir_action_conf *conf,
1346 const struct rte_flow_action *action,
1347 struct rte_flow_error *error);
1348 typedef int (*mlx5_flow_action_destroy_t)
1349 (struct rte_eth_dev *dev,
1350 struct rte_flow_action_handle *action,
1351 struct rte_flow_error *error);
1352 typedef int (*mlx5_flow_action_update_t)
1353 (struct rte_eth_dev *dev,
1354 struct rte_flow_action_handle *action,
1356 struct rte_flow_error *error);
1357 typedef int (*mlx5_flow_action_query_t)
1358 (struct rte_eth_dev *dev,
1359 const struct rte_flow_action_handle *action,
1361 struct rte_flow_error *error);
1362 typedef int (*mlx5_flow_sync_domain_t)
1363 (struct rte_eth_dev *dev,
1366 typedef int (*mlx5_flow_validate_mtr_acts_t)
1367 (struct rte_eth_dev *dev,
1368 const struct rte_flow_action *actions[RTE_COLORS],
1369 struct rte_flow_attr *attr,
1371 uint8_t *domain_bitmap,
1372 uint8_t *policy_mode,
1373 struct rte_mtr_error *error);
1374 typedef int (*mlx5_flow_create_mtr_acts_t)
1375 (struct rte_eth_dev *dev,
1376 struct mlx5_flow_meter_policy *mtr_policy,
1377 const struct rte_flow_action *actions[RTE_COLORS],
1378 struct rte_mtr_error *error);
1379 typedef void (*mlx5_flow_destroy_mtr_acts_t)
1380 (struct rte_eth_dev *dev,
1381 struct mlx5_flow_meter_policy *mtr_policy);
1382 typedef int (*mlx5_flow_create_policy_rules_t)
1383 (struct rte_eth_dev *dev,
1384 struct mlx5_flow_meter_policy *mtr_policy);
1385 typedef void (*mlx5_flow_destroy_policy_rules_t)
1386 (struct rte_eth_dev *dev,
1387 struct mlx5_flow_meter_policy *mtr_policy);
1388 typedef int (*mlx5_flow_create_def_policy_t)
1389 (struct rte_eth_dev *dev);
1390 typedef void (*mlx5_flow_destroy_def_policy_t)
1391 (struct rte_eth_dev *dev);
1392 typedef int (*mlx5_flow_discover_priorities_t)
1393 (struct rte_eth_dev *dev,
1394 const uint16_t *vprio, int vprio_n);
1395 typedef struct rte_flow_item_flex_handle *(*mlx5_flow_item_create_t)
1396 (struct rte_eth_dev *dev,
1397 const struct rte_flow_item_flex_conf *conf,
1398 struct rte_flow_error *error);
1399 typedef int (*mlx5_flow_item_release_t)
1400 (struct rte_eth_dev *dev,
1401 const struct rte_flow_item_flex_handle *handle,
1402 struct rte_flow_error *error);
1403 typedef int (*mlx5_flow_item_update_t)
1404 (struct rte_eth_dev *dev,
1405 const struct rte_flow_item_flex_handle *handle,
1406 const struct rte_flow_item_flex_conf *conf,
1407 struct rte_flow_error *error);
1408 typedef int (*mlx5_flow_info_get_t)
1409 (struct rte_eth_dev *dev,
1410 struct rte_flow_port_info *port_info,
1411 struct rte_flow_queue_info *queue_info,
1412 struct rte_flow_error *error);
1413 typedef int (*mlx5_flow_port_configure_t)
1414 (struct rte_eth_dev *dev,
1415 const struct rte_flow_port_attr *port_attr,
1417 const struct rte_flow_queue_attr *queue_attr[],
1418 struct rte_flow_error *err);
1419 typedef struct rte_flow_pattern_template *(*mlx5_flow_pattern_template_create_t)
1420 (struct rte_eth_dev *dev,
1421 const struct rte_flow_pattern_template_attr *attr,
1422 const struct rte_flow_item items[],
1423 struct rte_flow_error *error);
1424 typedef int (*mlx5_flow_pattern_template_destroy_t)
1425 (struct rte_eth_dev *dev,
1426 struct rte_flow_pattern_template *template,
1427 struct rte_flow_error *error);
1428 typedef struct rte_flow_actions_template *(*mlx5_flow_actions_template_create_t)
1429 (struct rte_eth_dev *dev,
1430 const struct rte_flow_actions_template_attr *attr,
1431 const struct rte_flow_action actions[],
1432 const struct rte_flow_action masks[],
1433 struct rte_flow_error *error);
1434 typedef int (*mlx5_flow_actions_template_destroy_t)
1435 (struct rte_eth_dev *dev,
1436 struct rte_flow_actions_template *template,
1437 struct rte_flow_error *error);
1438 typedef struct rte_flow_template_table *(*mlx5_flow_table_create_t)
1439 (struct rte_eth_dev *dev,
1440 const struct rte_flow_template_table_attr *attr,
1441 struct rte_flow_pattern_template *item_templates[],
1442 uint8_t nb_item_templates,
1443 struct rte_flow_actions_template *action_templates[],
1444 uint8_t nb_action_templates,
1445 struct rte_flow_error *error);
1446 typedef int (*mlx5_flow_table_destroy_t)
1447 (struct rte_eth_dev *dev,
1448 struct rte_flow_template_table *table,
1449 struct rte_flow_error *error);
1450 typedef struct rte_flow *(*mlx5_flow_async_flow_create_t)
1451 (struct rte_eth_dev *dev,
1453 const struct rte_flow_op_attr *attr,
1454 struct rte_flow_template_table *table,
1455 const struct rte_flow_item items[],
1456 uint8_t pattern_template_index,
1457 const struct rte_flow_action actions[],
1458 uint8_t action_template_index,
1460 struct rte_flow_error *error);
1461 typedef int (*mlx5_flow_async_flow_destroy_t)
1462 (struct rte_eth_dev *dev,
1464 const struct rte_flow_op_attr *attr,
1465 struct rte_flow *flow,
1467 struct rte_flow_error *error);
1468 typedef int (*mlx5_flow_pull_t)
1469 (struct rte_eth_dev *dev,
1471 struct rte_flow_op_result res[],
1473 struct rte_flow_error *error);
1474 typedef int (*mlx5_flow_push_t)
1475 (struct rte_eth_dev *dev,
1477 struct rte_flow_error *error);
1479 typedef struct rte_flow_action_handle *(*mlx5_flow_async_action_handle_create_t)
1480 (struct rte_eth_dev *dev,
1482 const struct rte_flow_op_attr *attr,
1483 const struct rte_flow_indir_action_conf *conf,
1484 const struct rte_flow_action *action,
1486 struct rte_flow_error *error);
1488 typedef int (*mlx5_flow_async_action_handle_update_t)
1489 (struct rte_eth_dev *dev,
1491 const struct rte_flow_op_attr *attr,
1492 struct rte_flow_action_handle *handle,
1495 struct rte_flow_error *error);
1497 typedef int (*mlx5_flow_async_action_handle_destroy_t)
1498 (struct rte_eth_dev *dev,
1500 const struct rte_flow_op_attr *attr,
1501 struct rte_flow_action_handle *handle,
1503 struct rte_flow_error *error);
1505 struct mlx5_flow_driver_ops {
1506 mlx5_flow_validate_t validate;
1507 mlx5_flow_prepare_t prepare;
1508 mlx5_flow_translate_t translate;
1509 mlx5_flow_apply_t apply;
1510 mlx5_flow_remove_t remove;
1511 mlx5_flow_destroy_t destroy;
1512 mlx5_flow_query_t query;
1513 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1514 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1515 mlx5_flow_destroy_mtr_drop_tbls_t destroy_mtr_drop_tbls;
1516 mlx5_flow_mtr_alloc_t create_meter;
1517 mlx5_flow_mtr_free_t free_meter;
1518 mlx5_flow_validate_mtr_acts_t validate_mtr_acts;
1519 mlx5_flow_create_mtr_acts_t create_mtr_acts;
1520 mlx5_flow_destroy_mtr_acts_t destroy_mtr_acts;
1521 mlx5_flow_create_policy_rules_t create_policy_rules;
1522 mlx5_flow_destroy_policy_rules_t destroy_policy_rules;
1523 mlx5_flow_create_def_policy_t create_def_policy;
1524 mlx5_flow_destroy_def_policy_t destroy_def_policy;
1525 mlx5_flow_meter_sub_policy_rss_prepare_t meter_sub_policy_rss_prepare;
1526 mlx5_flow_meter_hierarchy_rule_create_t meter_hierarchy_rule_create;
1527 mlx5_flow_destroy_sub_policy_with_rxq_t destroy_sub_policy_with_rxq;
1528 mlx5_flow_counter_alloc_t counter_alloc;
1529 mlx5_flow_counter_free_t counter_free;
1530 mlx5_flow_counter_query_t counter_query;
1531 mlx5_flow_get_aged_flows_t get_aged_flows;
1532 mlx5_flow_action_validate_t action_validate;
1533 mlx5_flow_action_create_t action_create;
1534 mlx5_flow_action_destroy_t action_destroy;
1535 mlx5_flow_action_update_t action_update;
1536 mlx5_flow_action_query_t action_query;
1537 mlx5_flow_sync_domain_t sync_domain;
1538 mlx5_flow_discover_priorities_t discover_priorities;
1539 mlx5_flow_item_create_t item_create;
1540 mlx5_flow_item_release_t item_release;
1541 mlx5_flow_item_update_t item_update;
1542 mlx5_flow_info_get_t info_get;
1543 mlx5_flow_port_configure_t configure;
1544 mlx5_flow_pattern_template_create_t pattern_template_create;
1545 mlx5_flow_pattern_template_destroy_t pattern_template_destroy;
1546 mlx5_flow_actions_template_create_t actions_template_create;
1547 mlx5_flow_actions_template_destroy_t actions_template_destroy;
1548 mlx5_flow_table_create_t template_table_create;
1549 mlx5_flow_table_destroy_t template_table_destroy;
1550 mlx5_flow_async_flow_create_t async_flow_create;
1551 mlx5_flow_async_flow_destroy_t async_flow_destroy;
1552 mlx5_flow_pull_t pull;
1553 mlx5_flow_push_t push;
1554 mlx5_flow_async_action_handle_create_t async_action_create;
1555 mlx5_flow_async_action_handle_update_t async_action_update;
1556 mlx5_flow_async_action_handle_destroy_t async_action_destroy;
1561 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1563 struct flow_grp_info {
1564 uint64_t external:1;
1565 uint64_t transfer:1;
1566 uint64_t fdb_def_rule:1;
1567 /* force standard group translation */
1568 uint64_t std_tbl_fix:1;
1569 uint64_t skip_scale:2;
1573 tunnel_use_standard_attr_group_translate
1574 (const struct rte_eth_dev *dev,
1575 const struct rte_flow_attr *attr,
1576 const struct mlx5_flow_tunnel *tunnel,
1577 enum mlx5_tof_rule_type tof_rule_type)
1581 if (!is_tunnel_offload_active(dev))
1582 /* no tunnel offload API */
1586 * OvS will use jump to group 0 in tunnel steer rule.
1587 * If tunnel steer rule starts from group 0 (attr.group == 0)
1588 * that 0 group must be translated with standard method.
1589 * attr.group == 0 in tunnel match rule translated with tunnel
1592 verdict = !attr->group &&
1593 is_flow_tunnel_steer_rule(tof_rule_type);
1596 * non-tunnel group translation uses standard method for
1597 * root group only: attr.group == 0
1599 verdict = !attr->group;
1606 * Get DV flow aso meter by index.
1609 * Pointer to the Ethernet device structure.
1611 * mlx5 flow aso meter index in the container.
1613 * mlx5 flow aso meter pool in the container,
1616 * Pointer to the aso meter, NULL otherwise.
1618 static inline struct mlx5_aso_mtr *
1619 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)
1621 struct mlx5_aso_mtr_pool *pool;
1622 struct mlx5_aso_mtr_pools_mng *pools_mng =
1623 &priv->sh->mtrmng->pools_mng;
1625 /* Decrease to original index. */
1627 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < pools_mng->n);
1628 rte_rwlock_read_lock(&pools_mng->resize_mtrwl);
1629 pool = pools_mng->pools[idx / MLX5_ASO_MTRS_PER_POOL];
1630 rte_rwlock_read_unlock(&pools_mng->resize_mtrwl);
1631 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL];
1634 static __rte_always_inline const struct rte_flow_item *
1635 mlx5_find_end_item(const struct rte_flow_item *item)
1637 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++);
1641 static __rte_always_inline bool
1642 mlx5_validate_integrity_item(const struct rte_flow_item_integrity *item)
1644 struct rte_flow_item_integrity test = *item;
1647 test.ipv4_csum_ok = 0;
1648 test.l4_csum_ok = 0;
1649 return (test.value == 0);
1653 * Get ASO CT action by device and index.
1656 * Pointer to the Ethernet device structure.
1658 * Index to the ASO CT action.
1661 * The specified ASO CT action pointer.
1663 static inline struct mlx5_aso_ct_action *
1664 flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx)
1666 struct mlx5_priv *priv = dev->data->dev_private;
1667 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
1668 struct mlx5_aso_ct_pool *pool;
1671 MLX5_ASSERT((idx / MLX5_ASO_CT_ACTIONS_PER_POOL) < mng->n);
1672 /* Bit operation AND could be used. */
1673 rte_rwlock_read_lock(&mng->resize_rwl);
1674 pool = mng->pools[idx / MLX5_ASO_CT_ACTIONS_PER_POOL];
1675 rte_rwlock_read_unlock(&mng->resize_rwl);
1676 return &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];
1680 * Get ASO CT action by owner & index.
1683 * Pointer to the Ethernet device structure.
1685 * Index to the ASO CT action and owner port combination.
1688 * The specified ASO CT action pointer.
1690 static inline struct mlx5_aso_ct_action *
1691 flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx)
1693 struct mlx5_priv *priv = dev->data->dev_private;
1694 struct mlx5_aso_ct_action *ct;
1695 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
1696 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
1698 if (owner == PORT_ID(priv)) {
1699 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
1701 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
1703 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
1704 if (dev->data->dev_started != 1)
1706 ct = flow_aso_ct_get_by_dev_idx(owndev, idx);
1707 if (ct->peer != PORT_ID(priv))
1713 static inline uint16_t
1714 mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
1716 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
1717 return RTE_ETHER_TYPE_TEB;
1718 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
1719 return RTE_ETHER_TYPE_IPV4;
1720 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
1721 return RTE_ETHER_TYPE_IPV6;
1722 else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
1723 return RTE_ETHER_TYPE_MPLS;
1727 int flow_hw_q_flow_flush(struct rte_eth_dev *dev,
1728 struct rte_flow_error *error);
1729 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1730 const struct mlx5_flow_tunnel *tunnel,
1731 uint32_t group, uint32_t *table,
1732 const struct flow_grp_info *flags,
1733 struct rte_flow_error *error);
1734 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1735 int tunnel, uint64_t layer_types,
1736 uint64_t hash_fields);
1737 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1738 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1739 uint32_t subpriority);
1740 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev,
1741 const struct rte_flow_attr *attr);
1742 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev,
1743 const struct rte_flow_attr *attr,
1744 uint32_t subpriority, bool external);
1745 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1746 enum mlx5_feature_name feature,
1748 struct rte_flow_error *error);
1749 const struct rte_flow_action *mlx5_flow_find_action
1750 (const struct rte_flow_action *actions,
1751 enum rte_flow_action_type action);
1752 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1753 const struct rte_flow_action *action,
1754 struct rte_flow_error *error);
1755 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1756 const struct rte_flow_attr *attr,
1757 struct rte_flow_error *error);
1758 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1759 const struct rte_flow_attr *attr,
1760 struct rte_flow_error *error);
1761 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1762 const struct rte_flow_attr *attr,
1763 struct rte_flow_error *error);
1764 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1765 uint64_t action_flags,
1766 const struct rte_flow_attr *attr,
1767 struct rte_flow_error *error);
1768 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1769 uint64_t action_flags,
1770 struct rte_eth_dev *dev,
1771 const struct rte_flow_attr *attr,
1772 struct rte_flow_error *error);
1773 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1774 uint64_t action_flags,
1775 struct rte_eth_dev *dev,
1776 const struct rte_flow_attr *attr,
1777 uint64_t item_flags,
1778 struct rte_flow_error *error);
1779 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1780 const struct rte_flow_attr *attr,
1781 struct rte_flow_error *error);
1782 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1783 const struct rte_flow_attr *attributes,
1784 struct rte_flow_error *error);
1785 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1786 const uint8_t *mask,
1787 const uint8_t *nic_mask,
1789 bool range_accepted,
1790 struct rte_flow_error *error);
1791 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1792 uint64_t item_flags, bool ext_vlan_sup,
1793 struct rte_flow_error *error);
1794 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1795 uint64_t item_flags,
1796 uint8_t target_protocol,
1797 struct rte_flow_error *error);
1798 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1799 uint64_t item_flags,
1800 const struct rte_flow_item *gre_item,
1801 struct rte_flow_error *error);
1802 int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
1803 const struct rte_flow_item *item,
1804 uint64_t item_flags,
1805 const struct rte_flow_attr *attr,
1806 const struct rte_flow_item *gre_item,
1807 struct rte_flow_error *error);
1808 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1809 uint64_t item_flags,
1811 uint16_t ether_type,
1812 const struct rte_flow_item_ipv4 *acc_mask,
1813 bool range_accepted,
1814 struct rte_flow_error *error);
1815 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1816 uint64_t item_flags,
1818 uint16_t ether_type,
1819 const struct rte_flow_item_ipv6 *acc_mask,
1820 struct rte_flow_error *error);
1821 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1822 const struct rte_flow_item *item,
1823 uint64_t item_flags,
1824 uint64_t prev_layer,
1825 struct rte_flow_error *error);
1826 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1827 uint64_t item_flags,
1828 uint8_t target_protocol,
1829 const struct rte_flow_item_tcp *flow_mask,
1830 struct rte_flow_error *error);
1831 int mlx5_flow_validate_item_esp(const struct rte_flow_item *item,
1832 uint64_t item_flags,
1833 uint8_t target_protocol,
1834 struct rte_flow_error *error);
1835 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1836 uint64_t item_flags,
1837 uint8_t target_protocol,
1838 struct rte_flow_error *error);
1839 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1840 uint64_t item_flags,
1841 struct rte_eth_dev *dev,
1842 struct rte_flow_error *error);
1843 int mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev,
1845 const struct rte_flow_item *item,
1846 uint64_t item_flags,
1847 const struct rte_flow_attr *attr,
1848 struct rte_flow_error *error);
1849 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1850 uint64_t item_flags,
1851 struct rte_eth_dev *dev,
1852 struct rte_flow_error *error);
1853 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1854 uint64_t item_flags,
1855 uint8_t target_protocol,
1856 struct rte_flow_error *error);
1857 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1858 uint64_t item_flags,
1859 uint8_t target_protocol,
1860 struct rte_flow_error *error);
1861 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1862 uint64_t item_flags,
1863 uint8_t target_protocol,
1864 struct rte_flow_error *error);
1865 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1866 uint64_t item_flags,
1867 struct rte_eth_dev *dev,
1868 struct rte_flow_error *error);
1869 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,
1871 const struct rte_flow_item *geneve_item,
1872 struct rte_eth_dev *dev,
1873 struct rte_flow_error *error);
1874 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1875 uint64_t item_flags,
1877 uint16_t ether_type,
1878 const struct rte_flow_item_ecpri *acc_mask,
1879 struct rte_flow_error *error);
1880 int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,
1881 struct mlx5_flow_meter_info *fm,
1883 uint8_t domain_bitmap);
1884 void mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1885 struct mlx5_flow_meter_info *fm);
1886 void mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev);
1887 struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare
1888 (struct rte_eth_dev *dev,
1889 struct mlx5_flow_meter_policy *mtr_policy,
1890 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]);
1891 void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
1892 struct mlx5_flow_meter_policy *mtr_policy);
1893 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1894 int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev);
1895 int mlx5_action_handle_attach(struct rte_eth_dev *dev);
1896 int mlx5_action_handle_detach(struct rte_eth_dev *dev);
1897 int mlx5_action_handle_flush(struct rte_eth_dev *dev);
1898 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1899 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1901 struct mlx5_list_entry *flow_dv_tbl_create_cb(void *tool_ctx, void *entry_ctx);
1902 int flow_dv_tbl_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1904 void flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1905 struct mlx5_list_entry *flow_dv_tbl_clone_cb(void *tool_ctx,
1906 struct mlx5_list_entry *oentry,
1908 void flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1909 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1910 uint32_t table_level, uint8_t egress, uint8_t transfer,
1911 bool external, const struct mlx5_flow_tunnel *tunnel,
1912 uint32_t group_id, uint8_t dummy,
1913 uint32_t table_id, struct rte_flow_error *error);
1915 struct mlx5_list_entry *flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx);
1916 int flow_dv_tag_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1918 void flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1919 struct mlx5_list_entry *flow_dv_tag_clone_cb(void *tool_ctx,
1920 struct mlx5_list_entry *oentry,
1922 void flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1924 int flow_dv_modify_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1926 struct mlx5_list_entry *flow_dv_modify_create_cb(void *tool_ctx, void *ctx);
1927 void flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1928 struct mlx5_list_entry *flow_dv_modify_clone_cb(void *tool_ctx,
1929 struct mlx5_list_entry *oentry,
1931 void flow_dv_modify_clone_free_cb(void *tool_ctx,
1932 struct mlx5_list_entry *entry);
1934 struct mlx5_list_entry *flow_dv_mreg_create_cb(void *tool_ctx, void *ctx);
1935 int flow_dv_mreg_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1937 void flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1938 struct mlx5_list_entry *flow_dv_mreg_clone_cb(void *tool_ctx,
1939 struct mlx5_list_entry *entry,
1941 void flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1943 int flow_dv_encap_decap_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1945 struct mlx5_list_entry *flow_dv_encap_decap_create_cb(void *tool_ctx,
1947 void flow_dv_encap_decap_remove_cb(void *tool_ctx,
1948 struct mlx5_list_entry *entry);
1949 struct mlx5_list_entry *flow_dv_encap_decap_clone_cb(void *tool_ctx,
1950 struct mlx5_list_entry *entry,
1952 void flow_dv_encap_decap_clone_free_cb(void *tool_ctx,
1953 struct mlx5_list_entry *entry);
1955 int flow_dv_matcher_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1957 struct mlx5_list_entry *flow_dv_matcher_create_cb(void *tool_ctx, void *ctx);
1958 void flow_dv_matcher_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1960 int flow_dv_port_id_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1962 struct mlx5_list_entry *flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx);
1963 void flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1964 struct mlx5_list_entry *flow_dv_port_id_clone_cb(void *tool_ctx,
1965 struct mlx5_list_entry *entry, void *cb_ctx);
1966 void flow_dv_port_id_clone_free_cb(void *tool_ctx,
1967 struct mlx5_list_entry *entry);
1969 int flow_dv_push_vlan_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1971 struct mlx5_list_entry *flow_dv_push_vlan_create_cb(void *tool_ctx,
1973 void flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1974 struct mlx5_list_entry *flow_dv_push_vlan_clone_cb(void *tool_ctx,
1975 struct mlx5_list_entry *entry, void *cb_ctx);
1976 void flow_dv_push_vlan_clone_free_cb(void *tool_ctx,
1977 struct mlx5_list_entry *entry);
1979 int flow_dv_sample_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1981 struct mlx5_list_entry *flow_dv_sample_create_cb(void *tool_ctx, void *cb_ctx);
1982 void flow_dv_sample_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
1983 struct mlx5_list_entry *flow_dv_sample_clone_cb(void *tool_ctx,
1984 struct mlx5_list_entry *entry, void *cb_ctx);
1985 void flow_dv_sample_clone_free_cb(void *tool_ctx,
1986 struct mlx5_list_entry *entry);
1988 int flow_dv_dest_array_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
1990 struct mlx5_list_entry *flow_dv_dest_array_create_cb(void *tool_ctx,
1992 void flow_dv_dest_array_remove_cb(void *tool_ctx,
1993 struct mlx5_list_entry *entry);
1994 struct mlx5_list_entry *flow_dv_dest_array_clone_cb(void *tool_ctx,
1995 struct mlx5_list_entry *entry, void *cb_ctx);
1996 void flow_dv_dest_array_clone_free_cb(void *tool_ctx,
1997 struct mlx5_list_entry *entry);
1998 void flow_dv_hashfields_set(uint64_t item_flags,
1999 struct mlx5_flow_rss_desc *rss_desc,
2000 uint64_t *hash_fields);
2001 void flow_dv_action_rss_l34_hash_adjust(uint64_t rss_types,
2002 uint64_t *hash_field);
2003 uint32_t flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
2004 const uint64_t hash_fields);
2006 struct mlx5_list_entry *flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx);
2007 void flow_hw_grp_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
2008 int flow_hw_grp_match_cb(void *tool_ctx,
2009 struct mlx5_list_entry *entry,
2011 struct mlx5_list_entry *flow_hw_grp_clone_cb(void *tool_ctx,
2012 struct mlx5_list_entry *oentry,
2014 void flow_hw_grp_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry);
2016 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,
2018 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
2019 const struct rte_flow_item *item,
2020 struct rte_flow_error *error);
2021 void flow_release_workspace(void *data);
2022 int mlx5_flow_os_init_workspace_once(void);
2023 void *mlx5_flow_os_get_specific_workspace(void);
2024 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);
2025 void mlx5_flow_os_release_workspace(void);
2026 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev);
2027 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx);
2028 int mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev,
2029 const struct rte_flow_action *actions[RTE_COLORS],
2030 struct rte_flow_attr *attr,
2032 uint8_t *domain_bitmap,
2033 uint8_t *policy_mode,
2034 struct rte_mtr_error *error);
2035 void mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev,
2036 struct mlx5_flow_meter_policy *mtr_policy);
2037 int mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev,
2038 struct mlx5_flow_meter_policy *mtr_policy,
2039 const struct rte_flow_action *actions[RTE_COLORS],
2040 struct rte_mtr_error *error);
2041 int mlx5_flow_create_policy_rules(struct rte_eth_dev *dev,
2042 struct mlx5_flow_meter_policy *mtr_policy);
2043 void mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev,
2044 struct mlx5_flow_meter_policy *mtr_policy);
2045 int mlx5_flow_create_def_policy(struct rte_eth_dev *dev);
2046 void mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev);
2047 void flow_drv_rxq_flags_set(struct rte_eth_dev *dev,
2048 struct mlx5_flow_handle *dev_handle);
2049 const struct mlx5_flow_tunnel *
2050 mlx5_get_tof(const struct rte_flow_item *items,
2051 const struct rte_flow_action *actions,
2052 enum mlx5_tof_rule_type *rule_type);
2054 flow_hw_resource_release(struct rte_eth_dev *dev);
2055 int flow_dv_action_validate(struct rte_eth_dev *dev,
2056 const struct rte_flow_indir_action_conf *conf,
2057 const struct rte_flow_action *action,
2058 struct rte_flow_error *err);
2059 struct rte_flow_action_handle *flow_dv_action_create(struct rte_eth_dev *dev,
2060 const struct rte_flow_indir_action_conf *conf,
2061 const struct rte_flow_action *action,
2062 struct rte_flow_error *err);
2063 int flow_dv_action_destroy(struct rte_eth_dev *dev,
2064 struct rte_flow_action_handle *handle,
2065 struct rte_flow_error *error);
2066 int flow_dv_action_update(struct rte_eth_dev *dev,
2067 struct rte_flow_action_handle *handle,
2069 struct rte_flow_error *err);
2070 int flow_dv_action_query(struct rte_eth_dev *dev,
2071 const struct rte_flow_action_handle *handle,
2073 struct rte_flow_error *error);
2074 size_t flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type);
2075 int flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2076 size_t *size, struct rte_flow_error *error);
2077 #endif /* RTE_PMD_MLX5_FLOW_H_ */