1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_alarm.h>
17 #include <mlx5_glue.h>
22 /* Private rte flow items. */
23 enum mlx5_rte_flow_item_type {
24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
25 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
38 MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS,
39 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
42 /* Matches on selected register. */
43 struct mlx5_rte_flow_item_tag {
48 /* Modify selected register. */
49 struct mlx5_rte_flow_action_set_tag {
54 struct mlx5_flow_action_copy_mreg {
59 /* Matches on source queue. */
60 struct mlx5_rte_flow_item_tx_queue {
64 /* Feature name to allocate metadata register. */
65 enum mlx5_feature_name {
78 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
79 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
80 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
81 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
82 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
83 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
85 /* Pattern inner Layer bits. */
86 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
87 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
88 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
89 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
90 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
91 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
93 /* Pattern tunnel Layer bits. */
94 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
95 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
96 #define MLX5_FLOW_LAYER_GRE (1u << 14)
97 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
98 /* List of tunnel Layer bits continued below. */
100 /* General pattern items bits. */
101 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
102 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
103 #define MLX5_FLOW_ITEM_TAG (1u << 18)
104 #define MLX5_FLOW_ITEM_MARK (1u << 19)
106 /* Pattern MISC bits. */
107 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
108 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
109 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
111 /* Pattern tunnel Layer bits (continued). */
112 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
113 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
114 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
115 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
118 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
120 /* Pattern tunnel Layer bits (continued). */
121 #define MLX5_FLOW_LAYER_GTP (1u << 28)
123 /* Pattern eCPRI Layer bit. */
124 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
126 /* IPv6 Fragment Extension Header bit. */
127 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
128 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
131 #define MLX5_FLOW_LAYER_OUTER_L3 \
132 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
133 #define MLX5_FLOW_LAYER_OUTER_L4 \
134 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
135 #define MLX5_FLOW_LAYER_OUTER \
136 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
137 MLX5_FLOW_LAYER_OUTER_L4)
140 #define MLX5_FLOW_LAYER_TUNNEL \
141 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
142 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
143 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
144 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
147 #define MLX5_FLOW_LAYER_INNER_L3 \
148 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
149 #define MLX5_FLOW_LAYER_INNER_L4 \
150 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
151 #define MLX5_FLOW_LAYER_INNER \
152 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
153 MLX5_FLOW_LAYER_INNER_L4)
156 #define MLX5_FLOW_LAYER_L2 \
157 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
158 #define MLX5_FLOW_LAYER_L3_IPV4 \
159 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
160 #define MLX5_FLOW_LAYER_L3_IPV6 \
161 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
162 #define MLX5_FLOW_LAYER_L3 \
163 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
164 #define MLX5_FLOW_LAYER_L4 \
165 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
168 #define MLX5_FLOW_ACTION_DROP (1u << 0)
169 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
170 #define MLX5_FLOW_ACTION_RSS (1u << 2)
171 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
172 #define MLX5_FLOW_ACTION_MARK (1u << 4)
173 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
174 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
175 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
176 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
177 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
178 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
179 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
180 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
181 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
182 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
183 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
184 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
185 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
186 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
187 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
188 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
189 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
190 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
191 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
192 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
193 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
194 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
195 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
196 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
197 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
198 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
199 #define MLX5_FLOW_ACTION_METER (1ull << 31)
200 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
201 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
202 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
203 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
204 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
205 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
206 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
208 #define MLX5_FLOW_FATE_ACTIONS \
209 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
210 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
211 MLX5_FLOW_ACTION_DEFAULT_MISS)
213 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
214 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
215 MLX5_FLOW_ACTION_JUMP)
218 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
219 MLX5_FLOW_ACTION_SET_IPV4_DST | \
220 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
221 MLX5_FLOW_ACTION_SET_IPV6_DST | \
222 MLX5_FLOW_ACTION_SET_TP_SRC | \
223 MLX5_FLOW_ACTION_SET_TP_DST | \
224 MLX5_FLOW_ACTION_SET_TTL | \
225 MLX5_FLOW_ACTION_DEC_TTL | \
226 MLX5_FLOW_ACTION_SET_MAC_SRC | \
227 MLX5_FLOW_ACTION_SET_MAC_DST | \
228 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
229 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
230 MLX5_FLOW_ACTION_INC_TCP_ACK | \
231 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
232 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
233 MLX5_FLOW_ACTION_SET_TAG | \
234 MLX5_FLOW_ACTION_MARK_EXT | \
235 MLX5_FLOW_ACTION_SET_META | \
236 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
237 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
239 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
240 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
242 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
245 #define IPPROTO_MPLS 137
248 /* UDP port number for MPLS */
249 #define MLX5_UDP_PORT_MPLS 6635
251 /* UDP port numbers for VxLAN. */
252 #define MLX5_UDP_PORT_VXLAN 4789
253 #define MLX5_UDP_PORT_VXLAN_GPE 4790
255 /* UDP port numbers for GENEVE. */
256 #define MLX5_UDP_PORT_GENEVE 6081
258 /* Priority reserved for default flows. */
259 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
262 * Number of sub priorities.
263 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
264 * matching on the NIC (firmware dependent) L4 most have the higher priority
265 * followed by L3 and ending with L2.
267 #define MLX5_PRIORITY_MAP_L2 2
268 #define MLX5_PRIORITY_MAP_L3 1
269 #define MLX5_PRIORITY_MAP_L4 0
270 #define MLX5_PRIORITY_MAP_MAX 3
272 /* Valid layer type for IPV4 RSS. */
273 #define MLX5_IPV4_LAYER_TYPES \
274 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
275 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
276 ETH_RSS_NONFRAG_IPV4_OTHER)
278 /* IBV hash source bits for IPV4. */
279 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
281 /* Valid layer type for IPV6 RSS. */
282 #define MLX5_IPV6_LAYER_TYPES \
283 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
284 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
285 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
287 /* IBV hash source bits for IPV6. */
288 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
290 /* IBV hash bits for L3 SRC. */
291 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
293 /* IBV hash bits for L3 DST. */
294 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
296 /* IBV hash bits for TCP. */
297 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
298 IBV_RX_HASH_DST_PORT_TCP)
300 /* IBV hash bits for UDP. */
301 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
302 IBV_RX_HASH_DST_PORT_UDP)
304 /* IBV hash bits for L4 SRC. */
305 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
306 IBV_RX_HASH_SRC_PORT_UDP)
308 /* IBV hash bits for L4 DST. */
309 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
310 IBV_RX_HASH_DST_PORT_UDP)
312 /* Geneve header first 16Bit */
313 #define MLX5_GENEVE_VER_MASK 0x3
314 #define MLX5_GENEVE_VER_SHIFT 14
315 #define MLX5_GENEVE_VER_VAL(a) \
316 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
317 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
318 #define MLX5_GENEVE_OPTLEN_SHIFT 7
319 #define MLX5_GENEVE_OPTLEN_VAL(a) \
320 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
321 #define MLX5_GENEVE_OAMF_MASK 0x1
322 #define MLX5_GENEVE_OAMF_SHIFT 7
323 #define MLX5_GENEVE_OAMF_VAL(a) \
324 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
325 #define MLX5_GENEVE_CRITO_MASK 0x1
326 #define MLX5_GENEVE_CRITO_SHIFT 6
327 #define MLX5_GENEVE_CRITO_VAL(a) \
328 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
329 #define MLX5_GENEVE_RSVD_MASK 0x3F
330 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
332 * The length of the Geneve options fields, expressed in four byte multiples,
333 * not including the eight byte fixed tunnel.
335 #define MLX5_GENEVE_OPT_LEN_0 14
336 #define MLX5_GENEVE_OPT_LEN_1 63
338 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
339 sizeof(struct rte_flow_item_ipv4))
341 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
342 #define MLX5_IPV4_FRAG_OFFSET_MASK \
343 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
345 /* Specific item's fields can accept a range of values (using spec and last). */
346 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
347 #define MLX5_ITEM_RANGE_ACCEPTED true
349 /* Software header modify action numbers of a flow. */
350 #define MLX5_ACT_NUM_MDF_IPV4 1
351 #define MLX5_ACT_NUM_MDF_IPV6 4
352 #define MLX5_ACT_NUM_MDF_MAC 2
353 #define MLX5_ACT_NUM_MDF_VID 1
354 #define MLX5_ACT_NUM_MDF_PORT 2
355 #define MLX5_ACT_NUM_MDF_TTL 1
356 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
357 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
358 #define MLX5_ACT_NUM_MDF_TCPACK 1
359 #define MLX5_ACT_NUM_SET_REG 1
360 #define MLX5_ACT_NUM_SET_TAG 1
361 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
362 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
363 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
364 #define MLX5_ACT_NUM_SET_DSCP 1
366 enum mlx5_flow_drv_type {
369 MLX5_FLOW_TYPE_VERBS,
373 /* Fate action type. */
374 enum mlx5_flow_fate_type {
375 MLX5_FLOW_FATE_NONE, /* Egress flow. */
376 MLX5_FLOW_FATE_QUEUE,
378 MLX5_FLOW_FATE_PORT_ID,
380 MLX5_FLOW_FATE_DEFAULT_MISS,
384 /* Matcher PRM representation */
385 struct mlx5_flow_dv_match_params {
387 /**< Size of match value. Do NOT split size and key! */
388 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
389 /**< Matcher value. This value is used as the mask or as a key. */
392 /* Matcher structure. */
393 struct mlx5_flow_dv_matcher {
394 LIST_ENTRY(mlx5_flow_dv_matcher) next;
395 /**< Pointer to the next element. */
396 struct mlx5_flow_tbl_resource *tbl;
397 /**< Pointer to the table(group) the matcher associated with. */
398 uint32_t refcnt; /**< Reference counter. */
399 void *matcher_object; /**< Pointer to DV matcher */
400 uint16_t crc; /**< CRC of key. */
401 uint16_t priority; /**< Priority of matcher. */
402 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
405 #define MLX5_ENCAP_MAX_LEN 132
407 /* Encap/decap resource key of the hash organization. */
408 union mlx5_flow_encap_decap_key {
410 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
411 uint32_t refmt_type:8; /**< Header reformat type. */
412 uint32_t buf_size:8; /**< Encap buf size. */
413 uint32_t table_level:8; /**< Root table or not. */
414 uint32_t cksum; /**< Encap buf check sum. */
416 uint64_t v64; /**< full 64bits value of key */
419 /* Encap/decap resource structure. */
420 struct mlx5_flow_dv_encap_decap_resource {
421 struct mlx5_hlist_entry entry;
422 /* Pointer to next element. */
423 uint32_t refcnt; /**< Reference counter. */
425 /**< Encap/decap action object. */
426 uint8_t buf[MLX5_ENCAP_MAX_LEN];
428 uint8_t reformat_type;
430 uint64_t flags; /**< Flags for RDMA API. */
431 uint32_t idx; /**< Index for the index memory pool. */
434 /* Tag resource structure. */
435 struct mlx5_flow_dv_tag_resource {
436 struct mlx5_hlist_entry entry;
437 /**< hash list entry for tag resource, tag value as the key. */
439 /**< Tag action object. */
440 uint32_t refcnt; /**< Reference counter. */
441 uint32_t idx; /**< Index for the index memory pool. */
445 * Number of modification commands.
446 * The maximal actions amount in FW is some constant, and it is 16 in the
447 * latest releases. In some old releases, it will be limited to 8.
448 * Since there is no interface to query the capacity, the maximal value should
449 * be used to allow PMD to create the flow. The validation will be done in the
450 * lower driver layer or FW. A failure will be returned if exceeds the maximal
451 * supported actions number on the root table.
452 * On non-root tables, there is no limitation, but 32 is enough right now.
454 #define MLX5_MAX_MODIFY_NUM 32
455 #define MLX5_ROOT_TBL_MODIFY_NUM 16
457 /* Modify resource structure */
458 struct mlx5_flow_dv_modify_hdr_resource {
459 struct mlx5_hlist_entry entry;
460 /* Pointer to next element. */
461 uint32_t refcnt; /**< Reference counter. */
463 /**< Modify header action object. */
464 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
465 uint32_t actions_num; /**< Number of modification actions. */
466 uint64_t flags; /**< Flags for RDMA API. */
467 struct mlx5_modification_cmd actions[];
468 /**< Modification actions. */
471 /* Modify resource key of the hash organization. */
472 union mlx5_flow_modify_hdr_key {
474 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
475 uint32_t actions_num:5; /**< Number of modification actions. */
476 uint32_t group:19; /**< Flow group id. */
477 uint32_t cksum; /**< Actions check sum. */
479 uint64_t v64; /**< full 64bits value of key */
482 /* Jump action resource structure. */
483 struct mlx5_flow_dv_jump_tbl_resource {
484 uint32_t refcnt; /**< Reference counter. */
485 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
486 void *action; /**< Pointer to the rdma core action. */
489 /* Port ID resource structure. */
490 struct mlx5_flow_dv_port_id_action_resource {
491 ILIST_ENTRY(uint32_t)next;
492 /* Pointer to next element. */
493 uint32_t refcnt; /**< Reference counter. */
495 /**< Action object. */
496 uint32_t port_id; /**< Port ID value. */
499 /* Push VLAN action resource structure */
500 struct mlx5_flow_dv_push_vlan_action_resource {
501 ILIST_ENTRY(uint32_t)next;
502 /* Pointer to next element. */
503 uint32_t refcnt; /**< Reference counter. */
504 void *action; /**< Action object. */
505 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
506 rte_be32_t vlan_tag; /**< VLAN tag value. */
509 /* Metadata register copy table entry. */
510 struct mlx5_flow_mreg_copy_resource {
512 * Hash list entry for copy table.
513 * - Key is 32/64-bit MARK action ID.
514 * - MUST be the first entry.
516 struct mlx5_hlist_entry hlist_ent;
517 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
518 /* List entry for device flows. */
519 uint32_t refcnt; /* Reference counter. */
520 uint32_t appcnt; /* Apply/Remove counter. */
522 uint32_t rix_flow; /* Built flow for copy. */
525 /* Table data structure of the hash organization. */
526 struct mlx5_flow_tbl_data_entry {
527 struct mlx5_hlist_entry entry;
528 /**< hash list entry, 64-bits key inside. */
529 struct mlx5_flow_tbl_resource tbl;
530 /**< flow table resource. */
531 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
532 /**< matchers' header associated with the flow table. */
533 struct mlx5_flow_dv_jump_tbl_resource jump;
534 /**< jump resource, at most one for each table created. */
535 uint32_t idx; /**< index for the indexed mempool. */
536 /**< tunnel offload */
537 const struct mlx5_flow_tunnel *tunnel;
542 /* Sub rdma-core actions list. */
543 struct mlx5_flow_sub_actions_list {
544 uint32_t actions_num; /**< Number of sample actions. */
545 uint64_t action_flags;
546 void *dr_queue_action;
549 void *dr_port_id_action;
550 void *dr_encap_action;
553 /* Sample sub-actions resource list. */
554 struct mlx5_flow_sub_actions_idx {
555 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
556 uint32_t rix_tag; /**< Index to the tag action. */
558 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
559 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
562 /* Sample action resource structure. */
563 struct mlx5_flow_dv_sample_resource {
564 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
565 uint32_t refcnt; /**< Reference counter. */
566 void *verbs_action; /**< Verbs sample action object. */
567 uint8_t ft_type; /** Flow Table Type */
568 uint32_t ft_id; /** Flow Table Level */
569 uint32_t ratio; /** Sample Ratio */
570 uint64_t set_action; /** Restore reg_c0 value */
571 void *normal_path_tbl; /** Flow Table pointer */
572 void *default_miss; /** default_miss dr_action. */
573 struct mlx5_flow_sub_actions_idx sample_idx;
574 /**< Action index resources. */
575 struct mlx5_flow_sub_actions_list sample_act;
576 /**< Action resources. */
579 #define MLX5_MAX_DEST_NUM 2
581 /* Destination array action resource structure. */
582 struct mlx5_flow_dv_dest_array_resource {
583 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
584 uint32_t refcnt; /**< Reference counter. */
585 uint8_t ft_type; /** Flow Table Type */
586 uint8_t num_of_dest; /**< Number of destination actions. */
587 void *action; /**< Pointer to the rdma core action. */
588 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
589 /**< Action index resources. */
590 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
591 /**< Action resources. */
594 /* Verbs specification header. */
595 struct ibv_spec_header {
596 enum ibv_flow_spec_type type;
600 /* RSS description. */
601 struct mlx5_flow_rss_desc {
603 uint32_t queue_num; /**< Number of entries in @p queue. */
604 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
605 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
606 uint16_t queue[]; /**< Destination queues to redirect traffic to. */
609 /* PMD flow priority for tunnel */
610 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
611 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
614 /** Device flow handle structure for DV mode only. */
615 struct mlx5_flow_handle_dv {
617 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
618 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
619 /**< Pointer to modify header resource in cache. */
620 uint32_t rix_encap_decap;
621 /**< Index to encap/decap resource in cache. */
622 uint32_t rix_push_vlan;
623 /**< Index to push VLAN action resource in cache. */
625 /**< Index to the tag action. */
627 /**< Index to sample action resource in cache. */
628 uint32_t rix_dest_array;
629 /**< Index to destination array resource in cache. */
632 /** Device flow handle structure: used both for creating & destroying. */
633 struct mlx5_flow_handle {
634 SILIST_ENTRY(uint32_t)next;
635 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
636 /**< Index to next device flow handle. */
638 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
639 void *drv_flow; /**< pointer to driver flow object. */
640 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
641 uint32_t mark:1; /**< Metadate rxq mark flag. */
642 uint32_t fate_action:3; /**< Fate action type. */
644 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
645 uint32_t rix_jump; /**< Index to the jump action resource. */
646 uint32_t rix_port_id_action;
647 /**< Index to port ID action resource. */
649 /**< Generic value indicates the fate action. */
650 uint32_t rix_default_fate;
651 /**< Indicates default miss fate action. */
653 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
654 struct mlx5_flow_handle_dv dvh;
659 * Size for Verbs device flow handle structure only. Do not use the DV only
660 * structure in Verbs. No DV flows attributes will be accessed.
661 * Macro offsetof() could also be used here.
663 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
664 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
665 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
667 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
671 * Max number of actions per DV flow.
672 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
673 * in rdma-core file providers/mlx5/verbs.c.
675 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
677 /** Device flow structure only for DV flow creation. */
678 struct mlx5_flow_dv_workspace {
679 uint32_t group; /**< The group index. */
680 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
681 int actions_n; /**< number of actions. */
682 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
683 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
684 /**< Pointer to encap/decap resource in cache. */
685 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
686 /**< Pointer to push VLAN action resource in cache. */
687 struct mlx5_flow_dv_tag_resource *tag_resource;
688 /**< pointer to the tag action. */
689 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
690 /**< Pointer to port ID action resource. */
691 struct mlx5_flow_dv_jump_tbl_resource *jump;
692 /**< Pointer to the jump action resource. */
693 struct mlx5_flow_dv_match_params value;
694 /**< Holds the value that the packet is compared to. */
695 struct mlx5_flow_dv_sample_resource *sample_res;
696 /**< Pointer to the sample action resource. */
697 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
698 /**< Pointer to the destination array resource. */
702 * Maximal Verbs flow specifications & actions size.
703 * Some elements are mutually exclusive, but enough space should be allocated.
704 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
705 * 2. One tunnel header (exception: GRE + MPLS),
706 * SPEC length: GRE == tunnel.
707 * Actions: 1. 1 Mark OR Flag.
708 * 2. 1 Drop (if any).
709 * 3. No limitation for counters, but it makes no sense to support too
710 * many counters in a single device flow.
712 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
713 #define MLX5_VERBS_MAX_SPEC_SIZE \
715 (2 * (sizeof(struct ibv_flow_spec_eth) + \
716 sizeof(struct ibv_flow_spec_ipv6) + \
717 sizeof(struct ibv_flow_spec_tcp_udp)) + \
718 sizeof(struct ibv_flow_spec_gre) + \
719 sizeof(struct ibv_flow_spec_mpls)) \
722 #define MLX5_VERBS_MAX_SPEC_SIZE \
724 (2 * (sizeof(struct ibv_flow_spec_eth) + \
725 sizeof(struct ibv_flow_spec_ipv6) + \
726 sizeof(struct ibv_flow_spec_tcp_udp)) + \
727 sizeof(struct ibv_flow_spec_tunnel)) \
731 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
732 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
733 #define MLX5_VERBS_MAX_ACT_SIZE \
735 sizeof(struct ibv_flow_spec_action_tag) + \
736 sizeof(struct ibv_flow_spec_action_drop) + \
737 sizeof(struct ibv_flow_spec_counter_action) * 4 \
740 #define MLX5_VERBS_MAX_ACT_SIZE \
742 sizeof(struct ibv_flow_spec_action_tag) + \
743 sizeof(struct ibv_flow_spec_action_drop) \
747 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
748 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
750 /** Device flow structure only for Verbs flow creation. */
751 struct mlx5_flow_verbs_workspace {
752 unsigned int size; /**< Size of the attribute. */
753 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
754 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
755 /**< Specifications & actions buffer of verbs flow. */
758 /** Maximal number of device sub-flows supported. */
759 #define MLX5_NUM_MAX_DEV_FLOWS 32
761 /** Device flow structure. */
763 struct rte_flow *flow; /**< Pointer to the main flow. */
764 uint32_t flow_idx; /**< The memory pool index to the main flow. */
765 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
767 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
768 bool external; /**< true if the flow is created external to PMD. */
769 uint8_t ingress; /**< 1 if the flow is ingress. */
771 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
772 struct mlx5_flow_dv_workspace dv;
774 struct mlx5_flow_verbs_workspace verbs;
776 struct mlx5_flow_handle *handle;
777 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
778 const struct mlx5_flow_tunnel *tunnel;
781 /* Flow meter state. */
782 #define MLX5_FLOW_METER_DISABLE 0
783 #define MLX5_FLOW_METER_ENABLE 1
785 #define MLX5_MAN_WIDTH 8
786 /* Modify this value if enum rte_mtr_color changes. */
787 #define RTE_MTR_DROPPED RTE_COLORS
789 /* Meter policer statistics */
790 struct mlx5_flow_policer_stats {
791 uint32_t cnt[RTE_COLORS + 1];
792 /**< Color counter, extra for drop. */
794 /**< Statistics mask for the colors. */
797 /* Meter table structure. */
798 struct mlx5_meter_domain_info {
799 struct mlx5_flow_tbl_resource *tbl;
801 struct mlx5_flow_tbl_resource *sfx_tbl;
802 /**< Meter suffix table. */
804 /**< Meter color not match default criteria. */
806 /**< Meter color match criteria. */
808 /**< Meter match action. */
809 void *policer_rules[RTE_MTR_DROPPED + 1];
810 /**< Meter policer for the match. */
813 /* Meter table set for TX RX FDB. */
814 struct mlx5_meter_domains_infos {
816 /**< Table user count. */
817 struct mlx5_meter_domain_info egress;
818 /**< TX meter table. */
819 struct mlx5_meter_domain_info ingress;
820 /**< RX meter table. */
821 struct mlx5_meter_domain_info transfer;
822 /**< FDB meter table. */
824 /**< Drop action as not matched. */
825 void *count_actns[RTE_MTR_DROPPED + 1];
826 /**< Counters for match and unmatched statistics. */
827 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
828 /**< Flow meter parameter. */
830 /**< Flow meter parameter size. */
832 /**< Flow meter action. */
835 /* Meter parameter structure. */
836 struct mlx5_flow_meter {
837 TAILQ_ENTRY(mlx5_flow_meter) next;
838 /**< Pointer to the next flow meter structure. */
839 uint32_t idx; /* Index to meter object. */
842 struct mlx5_flow_meter_profile *profile;
843 /**< Meter profile parameters. */
845 /** Policer actions (per meter output color). */
846 enum rte_mtr_policer_action action[RTE_COLORS];
848 /** Set of stats counters to be enabled.
849 * @see enum rte_mtr_stats_type
853 /**< Rule applies to ingress traffic. */
856 /**< Rule applies to egress traffic. */
859 * Instead of simply matching the properties of traffic as it would
860 * appear on a given DPDK port ID, enabling this attribute transfers
861 * a flow rule to the lowest possible level of any device endpoints
862 * found in the pattern.
864 * When supported, this effectively enables an application to
865 * re-route traffic not necessarily intended for it (e.g. coming
866 * from or addressed to different physical ports, VFs or
867 * applications) at the device level.
869 * It complements the behavior of some pattern items such as
870 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
872 * When transferring flow rules, ingress and egress attributes keep
873 * their original meaning, as if processing traffic emitted or
874 * received by the application.
877 struct mlx5_meter_domains_infos *mfts;
878 /**< Flow table created for this meter. */
879 struct mlx5_flow_policer_stats policer_stats;
880 /**< Meter policer statistics. */
883 uint32_t active_state:1;
886 /**< Meter shared or not. */
889 /* RFC2697 parameter structure. */
890 struct mlx5_flow_meter_srtcm_rfc2697_prm {
891 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
892 uint32_t cbs_exponent:5;
893 uint32_t cbs_mantissa:8;
894 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
895 uint32_t cir_exponent:5;
896 uint32_t cir_mantissa:8;
897 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
898 uint32_t ebs_exponent:5;
899 uint32_t ebs_mantissa:8;
902 /* Flow meter profile structure. */
903 struct mlx5_flow_meter_profile {
904 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
905 /**< Pointer to the next flow meter structure. */
906 uint32_t meter_profile_id; /**< Profile id. */
907 struct rte_mtr_meter_profile profile; /**< Profile detail. */
909 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
910 /**< srtcm_rfc2697 struct. */
912 uint32_t ref_cnt; /**< Use count. */
915 /* Fdir flow structure */
916 struct mlx5_fdir_flow {
917 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */
918 struct mlx5_fdir *fdir; /* Pointer to fdir. */
919 uint32_t rix_flow; /* Index to flow. */
922 #define HAIRPIN_FLOW_ID_BITS 28
924 #define MLX5_MAX_TUNNELS 256
925 #define MLX5_TNL_MISS_RULE_PRIORITY 3
926 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
929 * When tunnel offload is active, all JUMP group ids are converted
930 * using the same method. That conversion is applied both to tunnel and
931 * regular rule types.
932 * Group ids used in tunnel rules are relative to it's tunnel (!).
933 * Application can create number of steer rules, using the same
934 * tunnel, with different group id in each rule.
935 * Each tunnel stores its groups internally in PMD tunnel object.
936 * Groups used in regular rules do not belong to any tunnel and are stored
940 struct mlx5_flow_tunnel {
941 LIST_ENTRY(mlx5_flow_tunnel) chain;
942 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
943 uint32_t tunnel_id; /** unique tunnel ID */
945 struct rte_flow_action action;
946 struct rte_flow_item item;
947 struct mlx5_hlist *groups; /** tunnel groups */
950 /** PMD tunnel related context */
951 struct mlx5_flow_tunnel_hub {
952 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
953 struct mlx5_flow_id_pool *tunnel_ids;
954 struct mlx5_flow_id_pool *table_ids;
955 struct mlx5_hlist *groups; /** non tunnel groups */
958 /* convert jump group to flow table ID in tunnel rules */
959 struct tunnel_tbl_entry {
960 struct mlx5_hlist_entry hash;
964 static inline uint32_t
965 tunnel_id_to_flow_tbl(uint32_t id)
967 return id | (1u << 16);
970 static inline uint32_t
971 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
973 return flow_tbl & ~(1u << 16);
976 union tunnel_tbl_key {
984 static inline struct mlx5_flow_tunnel_hub *
985 mlx5_tunnel_hub(struct rte_eth_dev *dev)
987 struct mlx5_priv *priv = dev->data->dev_private;
988 return priv->sh->tunnel_hub;
992 is_tunnel_offload_active(struct rte_eth_dev *dev)
994 struct mlx5_priv *priv = dev->data->dev_private;
995 return !!priv->config.dv_miss_info;
999 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
1000 __rte_unused const struct rte_flow_attr *attr,
1001 __rte_unused const struct rte_flow_item items[],
1002 __rte_unused const struct rte_flow_action actions[])
1004 return (items[0].type == (typeof(items[0].type))
1005 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1009 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1010 __rte_unused const struct rte_flow_attr *attr,
1011 __rte_unused const struct rte_flow_item items[],
1012 __rte_unused const struct rte_flow_action actions[])
1014 return (actions[0].type == (typeof(actions[0].type))
1015 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1018 static inline const struct mlx5_flow_tunnel *
1019 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1021 return actions[0].conf;
1024 static inline const struct mlx5_flow_tunnel *
1025 flow_items_to_tunnel(const struct rte_flow_item items[])
1027 return items[0].spec;
1030 /* Flow structure. */
1032 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1033 struct mlx5_shared_action_rss *shared_rss; /** < Shred RSS action. */
1034 uint32_t dev_handles;
1035 /**< Device flow handles that are part of the flow. */
1036 uint32_t drv_type:2; /**< Driver type. */
1037 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */
1039 uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS;
1040 /**< The flow id used for hairpin. */
1041 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
1042 uint32_t rix_mreg_copy;
1043 /**< Index to metadata register copy table resource. */
1044 uint32_t counter; /**< Holds flow counter. */
1045 uint32_t tunnel_id; /**< Tunnel id */
1046 uint16_t meter; /**< Holds flow meter id. */
1050 * Define list of valid combinations of RX Hash fields
1051 * (see enum ibv_rx_hash_fields).
1053 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1054 #define MLX5_RSS_HASH_IPV4_TCP \
1055 (MLX5_RSS_HASH_IPV4 | \
1056 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1057 #define MLX5_RSS_HASH_IPV4_UDP \
1058 (MLX5_RSS_HASH_IPV4 | \
1059 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1060 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1061 #define MLX5_RSS_HASH_IPV6_TCP \
1062 (MLX5_RSS_HASH_IPV6 | \
1063 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1064 #define MLX5_RSS_HASH_IPV6_UDP \
1065 (MLX5_RSS_HASH_IPV6 | \
1066 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1067 #define MLX5_RSS_HASH_NONE 0ULL
1069 /* array of valid combinations of RX Hash fields for RSS */
1070 static const uint64_t mlx5_rss_hash_fields[] = {
1072 MLX5_RSS_HASH_IPV4_TCP,
1073 MLX5_RSS_HASH_IPV4_UDP,
1075 MLX5_RSS_HASH_IPV6_TCP,
1076 MLX5_RSS_HASH_IPV6_UDP,
1080 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
1082 /* Shared RSS action structure */
1083 struct mlx5_shared_action_rss {
1084 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1085 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1086 uint16_t *queue; /**< Queue indices to use. */
1087 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1088 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1089 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
1090 /**< Hash RX queue indexes for tunneled RSS */
1093 struct rte_flow_shared_action {
1094 LIST_ENTRY(rte_flow_shared_action) next;
1095 /**< Pointer to the next element. */
1096 uint32_t refcnt; /**< Atomically accessed refcnt. */
1098 /**< Shared action type (see MLX5_FLOW_ACTION_SHARED_*). */
1100 struct mlx5_shared_action_rss rss;
1101 /**< Shared RSS action. */
1105 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1106 const struct rte_flow_attr *attr,
1107 const struct rte_flow_item items[],
1108 const struct rte_flow_action actions[],
1111 struct rte_flow_error *error);
1112 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1113 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1114 const struct rte_flow_item items[],
1115 const struct rte_flow_action actions[], struct rte_flow_error *error);
1116 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1117 struct mlx5_flow *dev_flow,
1118 const struct rte_flow_attr *attr,
1119 const struct rte_flow_item items[],
1120 const struct rte_flow_action actions[],
1121 struct rte_flow_error *error);
1122 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1123 struct rte_flow_error *error);
1124 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1125 struct rte_flow *flow);
1126 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1127 struct rte_flow *flow);
1128 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1129 struct rte_flow *flow,
1130 const struct rte_flow_action *actions,
1132 struct rte_flow_error *error);
1133 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1134 (struct rte_eth_dev *dev,
1135 const struct mlx5_flow_meter *fm);
1136 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1137 struct mlx5_meter_domains_infos *tbls);
1138 typedef int (*mlx5_flow_create_policer_rules_t)
1139 (struct rte_eth_dev *dev,
1140 struct mlx5_flow_meter *fm,
1141 const struct rte_flow_attr *attr);
1142 typedef int (*mlx5_flow_destroy_policer_rules_t)
1143 (struct rte_eth_dev *dev,
1144 const struct mlx5_flow_meter *fm,
1145 const struct rte_flow_attr *attr);
1146 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1147 (struct rte_eth_dev *dev);
1148 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1150 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1152 bool clear, uint64_t *pkts,
1154 typedef int (*mlx5_flow_get_aged_flows_t)
1155 (struct rte_eth_dev *dev,
1157 uint32_t nb_contexts,
1158 struct rte_flow_error *error);
1159 typedef int (*mlx5_flow_action_validate_t)
1160 (struct rte_eth_dev *dev,
1161 const struct rte_flow_shared_action_conf *conf,
1162 const struct rte_flow_action *action,
1163 struct rte_flow_error *error);
1164 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1165 (struct rte_eth_dev *dev,
1166 const struct rte_flow_shared_action_conf *conf,
1167 const struct rte_flow_action *action,
1168 struct rte_flow_error *error);
1169 typedef int (*mlx5_flow_action_destroy_t)
1170 (struct rte_eth_dev *dev,
1171 struct rte_flow_shared_action *action,
1172 struct rte_flow_error *error);
1173 typedef int (*mlx5_flow_action_update_t)
1174 (struct rte_eth_dev *dev,
1175 struct rte_flow_shared_action *action,
1176 const void *action_conf,
1177 struct rte_flow_error *error);
1178 typedef int (*mlx5_flow_sync_domain_t)
1179 (struct rte_eth_dev *dev,
1182 struct mlx5_flow_driver_ops {
1183 mlx5_flow_validate_t validate;
1184 mlx5_flow_prepare_t prepare;
1185 mlx5_flow_translate_t translate;
1186 mlx5_flow_apply_t apply;
1187 mlx5_flow_remove_t remove;
1188 mlx5_flow_destroy_t destroy;
1189 mlx5_flow_query_t query;
1190 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1191 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1192 mlx5_flow_create_policer_rules_t create_policer_rules;
1193 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1194 mlx5_flow_counter_alloc_t counter_alloc;
1195 mlx5_flow_counter_free_t counter_free;
1196 mlx5_flow_counter_query_t counter_query;
1197 mlx5_flow_get_aged_flows_t get_aged_flows;
1198 mlx5_flow_action_validate_t action_validate;
1199 mlx5_flow_action_create_t action_create;
1200 mlx5_flow_action_destroy_t action_destroy;
1201 mlx5_flow_action_update_t action_update;
1202 mlx5_flow_sync_domain_t sync_domain;
1207 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id);
1208 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
1209 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
1210 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
1213 struct flow_grp_info {
1214 uint64_t external:1;
1215 uint64_t transfer:1;
1216 uint64_t fdb_def_rule:1;
1217 /* force standard group translation */
1218 uint64_t std_tbl_fix:1;
1222 tunnel_use_standard_attr_group_translate
1223 (struct rte_eth_dev *dev,
1224 const struct mlx5_flow_tunnel *tunnel,
1225 const struct rte_flow_attr *attr,
1226 const struct rte_flow_item items[],
1227 const struct rte_flow_action actions[])
1231 if (!is_tunnel_offload_active(dev))
1232 /* no tunnel offload API */
1236 * OvS will use jump to group 0 in tunnel steer rule.
1237 * If tunnel steer rule starts from group 0 (attr.group == 0)
1238 * that 0 group must be translated with standard method.
1239 * attr.group == 0 in tunnel match rule translated with tunnel
1242 verdict = !attr->group &&
1243 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1246 * non-tunnel group translation uses standard method for
1247 * root group only: attr.group == 0
1249 verdict = !attr->group;
1255 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1256 const struct mlx5_flow_tunnel *tunnel,
1257 uint32_t group, uint32_t *table,
1258 struct flow_grp_info flags,
1259 struct rte_flow_error *error);
1260 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1261 int tunnel, uint64_t layer_types,
1262 uint64_t hash_fields);
1263 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1264 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1265 uint32_t subpriority);
1266 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1267 enum mlx5_feature_name feature,
1269 struct rte_flow_error *error);
1270 const struct rte_flow_action *mlx5_flow_find_action
1271 (const struct rte_flow_action *actions,
1272 enum rte_flow_action_type action);
1273 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1274 const struct rte_flow_action *action,
1275 struct rte_flow_error *error);
1276 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1277 const struct rte_flow_attr *attr,
1278 struct rte_flow_error *error);
1279 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1280 const struct rte_flow_attr *attr,
1281 struct rte_flow_error *error);
1282 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1283 const struct rte_flow_attr *attr,
1284 struct rte_flow_error *error);
1285 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1286 uint64_t action_flags,
1287 const struct rte_flow_attr *attr,
1288 struct rte_flow_error *error);
1289 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1290 uint64_t action_flags,
1291 struct rte_eth_dev *dev,
1292 const struct rte_flow_attr *attr,
1293 struct rte_flow_error *error);
1294 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1295 uint64_t action_flags,
1296 struct rte_eth_dev *dev,
1297 const struct rte_flow_attr *attr,
1298 uint64_t item_flags,
1299 struct rte_flow_error *error);
1300 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1301 const struct rte_flow_attr *attr,
1302 struct rte_flow_error *error);
1303 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1304 const struct rte_flow_attr *attributes,
1305 struct rte_flow_error *error);
1306 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1307 const uint8_t *mask,
1308 const uint8_t *nic_mask,
1310 bool range_accepted,
1311 struct rte_flow_error *error);
1312 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1313 uint64_t item_flags, bool ext_vlan_sup,
1314 struct rte_flow_error *error);
1315 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1316 uint64_t item_flags,
1317 uint8_t target_protocol,
1318 struct rte_flow_error *error);
1319 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1320 uint64_t item_flags,
1321 const struct rte_flow_item *gre_item,
1322 struct rte_flow_error *error);
1323 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1324 uint64_t item_flags,
1326 uint16_t ether_type,
1327 const struct rte_flow_item_ipv4 *acc_mask,
1328 bool range_accepted,
1329 struct rte_flow_error *error);
1330 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1331 uint64_t item_flags,
1333 uint16_t ether_type,
1334 const struct rte_flow_item_ipv6 *acc_mask,
1335 struct rte_flow_error *error);
1336 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1337 const struct rte_flow_item *item,
1338 uint64_t item_flags,
1339 uint64_t prev_layer,
1340 struct rte_flow_error *error);
1341 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1342 uint64_t item_flags,
1343 uint8_t target_protocol,
1344 const struct rte_flow_item_tcp *flow_mask,
1345 struct rte_flow_error *error);
1346 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1347 uint64_t item_flags,
1348 uint8_t target_protocol,
1349 struct rte_flow_error *error);
1350 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1351 uint64_t item_flags,
1352 struct rte_eth_dev *dev,
1353 struct rte_flow_error *error);
1354 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1355 uint64_t item_flags,
1356 struct rte_flow_error *error);
1357 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1358 uint64_t item_flags,
1359 struct rte_eth_dev *dev,
1360 struct rte_flow_error *error);
1361 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1362 uint64_t item_flags,
1363 uint8_t target_protocol,
1364 struct rte_flow_error *error);
1365 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1366 uint64_t item_flags,
1367 uint8_t target_protocol,
1368 struct rte_flow_error *error);
1369 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1370 uint64_t item_flags,
1371 uint8_t target_protocol,
1372 struct rte_flow_error *error);
1373 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1374 uint64_t item_flags,
1375 struct rte_eth_dev *dev,
1376 struct rte_flow_error *error);
1377 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1378 uint64_t item_flags,
1380 uint16_t ether_type,
1381 const struct rte_flow_item_ecpri *acc_mask,
1382 struct rte_flow_error *error);
1383 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1384 (struct rte_eth_dev *dev,
1385 const struct mlx5_flow_meter *fm);
1386 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1387 struct mlx5_meter_domains_infos *tbl);
1388 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1389 struct mlx5_flow_meter *fm,
1390 const struct rte_flow_attr *attr);
1391 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1392 struct mlx5_flow_meter *fm,
1393 const struct rte_flow_attr *attr);
1394 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1395 struct rte_mtr_error *error);
1396 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1397 struct rte_flow_shared_action *mlx5_flow_get_shared_rss(struct rte_flow *flow);
1398 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1399 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1400 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1401 #endif /* RTE_PMD_MLX5_FLOW_H_ */