1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
27 /* Pattern outer Layer bits. */
28 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
29 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
30 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
31 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
32 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
33 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
35 /* Pattern inner Layer bits. */
36 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
37 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
38 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
39 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
40 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
41 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
43 /* Pattern tunnel Layer bits. */
44 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
45 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
46 #define MLX5_FLOW_LAYER_GRE (1u << 14)
47 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
49 /* General pattern items bits. */
50 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
51 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
54 #define MLX5_FLOW_LAYER_OUTER_L3 \
55 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
56 #define MLX5_FLOW_LAYER_OUTER_L4 \
57 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
58 #define MLX5_FLOW_LAYER_OUTER \
59 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
60 MLX5_FLOW_LAYER_OUTER_L4)
63 #define MLX5_FLOW_LAYER_TUNNEL \
64 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
65 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS)
68 #define MLX5_FLOW_LAYER_INNER_L3 \
69 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
70 #define MLX5_FLOW_LAYER_INNER_L4 \
71 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
72 #define MLX5_FLOW_LAYER_INNER \
73 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
74 MLX5_FLOW_LAYER_INNER_L4)
77 #define MLX5_FLOW_LAYER_L2 \
78 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
79 #define MLX5_FLOW_LAYER_L3_IPV4 \
80 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
81 #define MLX5_FLOW_LAYER_L3_IPV6 \
82 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
83 #define MLX5_FLOW_LAYER_L3 \
84 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
85 #define MLX5_FLOW_LAYER_L4 \
86 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
89 #define MLX5_FLOW_ACTION_DROP (1u << 0)
90 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
91 #define MLX5_FLOW_ACTION_RSS (1u << 2)
92 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
93 #define MLX5_FLOW_ACTION_MARK (1u << 4)
94 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
95 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
96 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
97 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
98 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
99 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
100 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
101 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
102 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
103 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
104 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
105 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
106 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
107 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
108 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
109 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
110 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
111 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
112 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
113 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
114 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
115 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
116 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
117 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
118 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
119 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
120 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
122 #define MLX5_FLOW_FATE_ACTIONS \
123 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
124 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
126 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
127 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
128 MLX5_FLOW_ACTION_JUMP)
130 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
131 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
132 MLX5_FLOW_ACTION_RAW_ENCAP)
134 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
135 MLX5_FLOW_ACTION_NVGRE_DECAP | \
136 MLX5_FLOW_ACTION_RAW_DECAP)
138 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
139 MLX5_FLOW_ACTION_SET_IPV4_DST | \
140 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
141 MLX5_FLOW_ACTION_SET_IPV6_DST | \
142 MLX5_FLOW_ACTION_SET_TP_SRC | \
143 MLX5_FLOW_ACTION_SET_TP_DST | \
144 MLX5_FLOW_ACTION_SET_TTL | \
145 MLX5_FLOW_ACTION_DEC_TTL | \
146 MLX5_FLOW_ACTION_SET_MAC_SRC | \
147 MLX5_FLOW_ACTION_SET_MAC_DST | \
148 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
149 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
150 MLX5_FLOW_ACTION_INC_TCP_ACK | \
151 MLX5_FLOW_ACTION_DEC_TCP_ACK)
154 #define IPPROTO_MPLS 137
157 /* UDP port number for MPLS */
158 #define MLX5_UDP_PORT_MPLS 6635
160 /* UDP port numbers for VxLAN. */
161 #define MLX5_UDP_PORT_VXLAN 4789
162 #define MLX5_UDP_PORT_VXLAN_GPE 4790
164 /* Priority reserved for default flows. */
165 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
168 * Number of sub priorities.
169 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
170 * matching on the NIC (firmware dependent) L4 most have the higher priority
171 * followed by L3 and ending with L2.
173 #define MLX5_PRIORITY_MAP_L2 2
174 #define MLX5_PRIORITY_MAP_L3 1
175 #define MLX5_PRIORITY_MAP_L4 0
176 #define MLX5_PRIORITY_MAP_MAX 3
178 /* Valid layer type for IPV4 RSS. */
179 #define MLX5_IPV4_LAYER_TYPES \
180 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
181 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
182 ETH_RSS_NONFRAG_IPV4_OTHER)
184 /* IBV hash source bits for IPV4. */
185 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
187 /* Valid layer type for IPV6 RSS. */
188 #define MLX5_IPV6_LAYER_TYPES \
189 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
190 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
191 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
193 /* IBV hash source bits for IPV6. */
194 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
196 enum mlx5_flow_drv_type {
200 MLX5_FLOW_TYPE_VERBS,
204 /* Matcher PRM representation */
205 struct mlx5_flow_dv_match_params {
207 /**< Size of match value. Do NOT split size and key! */
208 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
209 /**< Matcher value. This value is used as the mask or as a key. */
212 /* Matcher structure. */
213 struct mlx5_flow_dv_matcher {
214 LIST_ENTRY(mlx5_flow_dv_matcher) next;
215 /* Pointer to the next element. */
216 rte_atomic32_t refcnt; /**< Reference counter. */
217 void *matcher_object; /**< Pointer to DV matcher */
218 uint16_t crc; /**< CRC of key. */
219 uint16_t priority; /**< Priority of matcher. */
220 uint8_t egress; /**< Egress matcher. */
221 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
222 uint32_t group; /**< The matcher group. */
223 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
226 #define MLX5_ENCAP_MAX_LEN 132
228 /* Encap/decap resource structure. */
229 struct mlx5_flow_dv_encap_decap_resource {
230 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
231 /* Pointer to next element. */
232 rte_atomic32_t refcnt; /**< Reference counter. */
234 /**< Verbs encap/decap action object. */
235 uint8_t buf[MLX5_ENCAP_MAX_LEN];
237 uint8_t reformat_type;
239 uint64_t flags; /**< Flags for RDMA API. */
242 /* Tag resource structure. */
243 struct mlx5_flow_dv_tag_resource {
244 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
245 /* Pointer to next element. */
246 rte_atomic32_t refcnt; /**< Reference counter. */
248 /**< Verbs tag action object. */
249 uint32_t tag; /**< the tag value. */
252 /* Number of modification commands. */
253 #define MLX5_MODIFY_NUM 8
255 /* Modify resource structure */
256 struct mlx5_flow_dv_modify_hdr_resource {
257 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
258 /* Pointer to next element. */
259 rte_atomic32_t refcnt; /**< Reference counter. */
260 struct ibv_flow_action *verbs_action;
261 /**< Verbs modify header action object. */
262 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
263 uint32_t actions_num; /**< Number of modification actions. */
264 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
265 /**< Modification actions. */
266 uint64_t flags; /**< Flags for RDMA API. */
269 /* Jump action resource structure. */
270 struct mlx5_flow_dv_jump_tbl_resource {
271 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
272 /* Pointer to next element. */
273 rte_atomic32_t refcnt; /**< Reference counter. */
274 void *action; /**< Pointer to the rdma core action. */
275 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
276 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
279 /* Port ID resource structure. */
280 struct mlx5_flow_dv_port_id_action_resource {
281 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
282 /* Pointer to next element. */
283 rte_atomic32_t refcnt; /**< Reference counter. */
285 /**< Verbs tag action object. */
286 uint32_t port_id; /**< Port ID value. */
290 * Max number of actions per DV flow.
291 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
292 * In rdma-core file providers/mlx5/verbs.c
294 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
296 /* DV flows structure. */
297 struct mlx5_flow_dv {
298 uint64_t hash_fields; /**< Fields that participate in the hash. */
299 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
301 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
302 struct mlx5_flow_dv_match_params value;
303 /**< Holds the value that the packet is compared to. */
304 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
305 /**< Pointer to encap/decap resource in cache. */
306 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
307 /**< Pointer to modify header resource in cache. */
308 struct ibv_flow *flow; /**< Installed flow. */
309 struct mlx5_flow_dv_jump_tbl_resource *jump;
310 /**< Pointer to the jump action resource. */
311 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
312 /**< Pointer to port ID action resource. */
313 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
314 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
317 int actions_n; /**< number of actions. */
320 /** Linux TC flower driver for E-Switch flow. */
321 struct mlx5_flow_tcf {
322 struct nlmsghdr *nlh;
324 uint32_t *ptc_flags; /**< tc rule applied flags. */
325 union { /**< Tunnel encap/decap descriptor. */
326 struct flow_tcf_tunnel_hdr *tunnel;
327 struct flow_tcf_vxlan_decap *vxlan_decap;
328 struct flow_tcf_vxlan_encap *vxlan_encap;
330 uint32_t applied:1; /**< Whether rule is currently applied. */
332 uint32_t nlsize; /**< Size of NL message buffer for debug check. */
336 /* Verbs specification header. */
337 struct ibv_spec_header {
338 enum ibv_flow_spec_type type;
342 /** Handles information leading to a drop fate. */
343 struct mlx5_flow_verbs {
344 LIST_ENTRY(mlx5_flow_verbs) next;
345 unsigned int size; /**< Size of the attribute. */
347 struct ibv_flow_attr *attr;
348 /**< Pointer to the Specification buffer. */
349 uint8_t *specs; /**< Pointer to the specifications. */
351 struct ibv_flow *flow; /**< Verbs flow pointer. */
352 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
353 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
356 /** Device flow structure. */
358 LIST_ENTRY(mlx5_flow) next;
359 struct rte_flow *flow; /**< Pointer to the main flow. */
361 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
363 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
364 struct mlx5_flow_dv dv;
366 struct mlx5_flow_tcf tcf;
367 struct mlx5_flow_verbs verbs;
371 /* Counters information. */
372 struct mlx5_flow_counter {
373 LIST_ENTRY(mlx5_flow_counter) next; /**< Pointer to the next counter. */
374 uint32_t shared:1; /**< Share counter ID with other flow rules. */
375 uint32_t ref_cnt:31; /**< Reference counter. */
376 uint32_t id; /**< Counter ID. */
377 union { /**< Holds the counters for the rule. */
378 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
379 struct ibv_counter_set *cs;
380 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
381 struct ibv_counters *cs;
383 struct mlx5_devx_counter_set *dcs;
385 uint64_t hits; /**< Number of packets matched by the rule. */
386 uint64_t bytes; /**< Number of bytes matched by the rule. */
387 void *action; /**< Pointer to the dv action. */
390 /* Flow structure. */
392 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
393 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
394 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
395 struct mlx5_flow_dv_tag_resource *tag_resource;
396 /**< pointer to the tag action. */
397 struct rte_flow_action_rss rss;/**< RSS context. */
398 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
399 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
400 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
401 /**< Device flows that are part of the flow. */
403 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
404 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
405 uint8_t ingress; /**< 1 if the flow is ingress. */
406 uint32_t group; /**< The group index. */
407 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
410 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
411 const struct rte_flow_attr *attr,
412 const struct rte_flow_item items[],
413 const struct rte_flow_action actions[],
414 struct rte_flow_error *error);
415 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
416 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
417 const struct rte_flow_action actions[], struct rte_flow_error *error);
418 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
419 struct mlx5_flow *dev_flow,
420 const struct rte_flow_attr *attr,
421 const struct rte_flow_item items[],
422 const struct rte_flow_action actions[],
423 struct rte_flow_error *error);
424 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
425 struct rte_flow_error *error);
426 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
427 struct rte_flow *flow);
428 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
429 struct rte_flow *flow);
430 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
431 struct rte_flow *flow,
432 const struct rte_flow_action *actions,
434 struct rte_flow_error *error);
435 struct mlx5_flow_driver_ops {
436 mlx5_flow_validate_t validate;
437 mlx5_flow_prepare_t prepare;
438 mlx5_flow_translate_t translate;
439 mlx5_flow_apply_t apply;
440 mlx5_flow_remove_t remove;
441 mlx5_flow_destroy_t destroy;
442 mlx5_flow_query_t query;
447 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
448 uint64_t layer_types,
449 uint64_t hash_fields);
450 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
451 uint32_t subpriority);
452 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
453 const struct rte_flow_attr *attr,
454 struct rte_flow_error *error);
455 int mlx5_flow_validate_action_drop(uint64_t action_flags,
456 const struct rte_flow_attr *attr,
457 struct rte_flow_error *error);
458 int mlx5_flow_validate_action_flag(uint64_t action_flags,
459 const struct rte_flow_attr *attr,
460 struct rte_flow_error *error);
461 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
462 uint64_t action_flags,
463 const struct rte_flow_attr *attr,
464 struct rte_flow_error *error);
465 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
466 uint64_t action_flags,
467 struct rte_eth_dev *dev,
468 const struct rte_flow_attr *attr,
469 struct rte_flow_error *error);
470 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
471 uint64_t action_flags,
472 struct rte_eth_dev *dev,
473 const struct rte_flow_attr *attr,
475 struct rte_flow_error *error);
476 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
477 const struct rte_flow_attr *attributes,
478 struct rte_flow_error *error);
479 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
481 const uint8_t *nic_mask,
483 struct rte_flow_error *error);
484 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
486 struct rte_flow_error *error);
487 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
489 uint8_t target_protocol,
490 struct rte_flow_error *error);
491 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
493 const struct rte_flow_item_ipv4 *acc_mask,
494 struct rte_flow_error *error);
495 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
497 const struct rte_flow_item_ipv6 *acc_mask,
498 struct rte_flow_error *error);
499 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
500 const struct rte_flow_item *item,
503 struct rte_flow_error *error);
504 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
506 uint8_t target_protocol,
507 const struct rte_flow_item_tcp *flow_mask,
508 struct rte_flow_error *error);
509 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
511 uint8_t target_protocol,
512 struct rte_flow_error *error);
513 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
515 struct rte_flow_error *error);
516 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
518 struct rte_flow_error *error);
519 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
521 struct rte_eth_dev *dev,
522 struct rte_flow_error *error);
524 /* mlx5_flow_tcf.c */
526 int mlx5_flow_tcf_init(struct mlx5_flow_tcf_context *ctx,
527 unsigned int ifindex, struct rte_flow_error *error);
528 struct mlx5_flow_tcf_context *mlx5_flow_tcf_context_create(void);
529 void mlx5_flow_tcf_context_destroy(struct mlx5_flow_tcf_context *ctx);
531 #endif /* RTE_PMD_MLX5_FLOW_H_ */