1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_atomic.h>
15 #include <rte_alarm.h>
18 #include <mlx5_glue.h>
23 /* Private rte flow items. */
24 enum mlx5_rte_flow_item_type {
25 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
26 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
27 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
28 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
40 /* Matches on selected register. */
41 struct mlx5_rte_flow_item_tag {
46 /* Modify selected register. */
47 struct mlx5_rte_flow_action_set_tag {
52 struct mlx5_flow_action_copy_mreg {
57 /* Matches on source queue. */
58 struct mlx5_rte_flow_item_tx_queue {
62 /* Feature name to allocate metadata register. */
63 enum mlx5_feature_name {
76 /* Pattern outer Layer bits. */
77 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
78 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
79 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
80 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
81 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
82 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
84 /* Pattern inner Layer bits. */
85 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
86 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
87 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
88 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
89 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
90 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
92 /* Pattern tunnel Layer bits. */
93 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
94 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
95 #define MLX5_FLOW_LAYER_GRE (1u << 14)
96 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
97 /* List of tunnel Layer bits continued below. */
99 /* General pattern items bits. */
100 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
101 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
102 #define MLX5_FLOW_ITEM_TAG (1u << 18)
103 #define MLX5_FLOW_ITEM_MARK (1u << 19)
105 /* Pattern MISC bits. */
106 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
107 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
108 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
110 /* Pattern tunnel Layer bits (continued). */
111 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
112 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
113 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
114 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
117 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
119 /* Pattern tunnel Layer bits (continued). */
120 #define MLX5_FLOW_LAYER_GTP (1u << 28)
122 /* Pattern eCPRI Layer bit. */
123 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
126 #define MLX5_FLOW_LAYER_OUTER_L3 \
127 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
128 #define MLX5_FLOW_LAYER_OUTER_L4 \
129 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
130 #define MLX5_FLOW_LAYER_OUTER \
131 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
132 MLX5_FLOW_LAYER_OUTER_L4)
135 #define MLX5_FLOW_LAYER_TUNNEL \
136 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
137 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
138 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
139 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
142 #define MLX5_FLOW_LAYER_INNER_L3 \
143 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
144 #define MLX5_FLOW_LAYER_INNER_L4 \
145 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
146 #define MLX5_FLOW_LAYER_INNER \
147 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
148 MLX5_FLOW_LAYER_INNER_L4)
151 #define MLX5_FLOW_LAYER_L2 \
152 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
153 #define MLX5_FLOW_LAYER_L3_IPV4 \
154 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
155 #define MLX5_FLOW_LAYER_L3_IPV6 \
156 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
157 #define MLX5_FLOW_LAYER_L3 \
158 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
159 #define MLX5_FLOW_LAYER_L4 \
160 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
163 #define MLX5_FLOW_ACTION_DROP (1u << 0)
164 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
165 #define MLX5_FLOW_ACTION_RSS (1u << 2)
166 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
167 #define MLX5_FLOW_ACTION_MARK (1u << 4)
168 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
169 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
170 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
171 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
172 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
173 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
174 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
175 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
176 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
177 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
178 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
179 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
180 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
181 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
182 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
183 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
184 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
185 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
186 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
187 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
188 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
189 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
190 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
191 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
192 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
193 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
194 #define MLX5_FLOW_ACTION_METER (1ull << 31)
195 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
196 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
197 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
198 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
199 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
201 #define MLX5_FLOW_FATE_ACTIONS \
202 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
203 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
204 MLX5_FLOW_ACTION_DEFAULT_MISS)
206 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
207 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
208 MLX5_FLOW_ACTION_JUMP)
211 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
212 MLX5_FLOW_ACTION_SET_IPV4_DST | \
213 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
214 MLX5_FLOW_ACTION_SET_IPV6_DST | \
215 MLX5_FLOW_ACTION_SET_TP_SRC | \
216 MLX5_FLOW_ACTION_SET_TP_DST | \
217 MLX5_FLOW_ACTION_SET_TTL | \
218 MLX5_FLOW_ACTION_DEC_TTL | \
219 MLX5_FLOW_ACTION_SET_MAC_SRC | \
220 MLX5_FLOW_ACTION_SET_MAC_DST | \
221 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
222 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
223 MLX5_FLOW_ACTION_INC_TCP_ACK | \
224 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
225 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
226 MLX5_FLOW_ACTION_SET_TAG | \
227 MLX5_FLOW_ACTION_MARK_EXT | \
228 MLX5_FLOW_ACTION_SET_META | \
229 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
230 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
232 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
233 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
235 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
238 #define IPPROTO_MPLS 137
241 /* UDP port number for MPLS */
242 #define MLX5_UDP_PORT_MPLS 6635
244 /* UDP port numbers for VxLAN. */
245 #define MLX5_UDP_PORT_VXLAN 4789
246 #define MLX5_UDP_PORT_VXLAN_GPE 4790
248 /* UDP port numbers for GENEVE. */
249 #define MLX5_UDP_PORT_GENEVE 6081
251 /* Priority reserved for default flows. */
252 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
255 * Number of sub priorities.
256 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
257 * matching on the NIC (firmware dependent) L4 most have the higher priority
258 * followed by L3 and ending with L2.
260 #define MLX5_PRIORITY_MAP_L2 2
261 #define MLX5_PRIORITY_MAP_L3 1
262 #define MLX5_PRIORITY_MAP_L4 0
263 #define MLX5_PRIORITY_MAP_MAX 3
265 /* Valid layer type for IPV4 RSS. */
266 #define MLX5_IPV4_LAYER_TYPES \
267 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
268 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
269 ETH_RSS_NONFRAG_IPV4_OTHER)
271 /* IBV hash source bits for IPV4. */
272 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
274 /* Valid layer type for IPV6 RSS. */
275 #define MLX5_IPV6_LAYER_TYPES \
276 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
277 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
278 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
280 /* IBV hash source bits for IPV6. */
281 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
283 /* IBV hash bits for L3 SRC. */
284 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
286 /* IBV hash bits for L3 DST. */
287 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
289 /* IBV hash bits for TCP. */
290 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
291 IBV_RX_HASH_DST_PORT_TCP)
293 /* IBV hash bits for UDP. */
294 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
295 IBV_RX_HASH_DST_PORT_UDP)
297 /* IBV hash bits for L4 SRC. */
298 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
299 IBV_RX_HASH_SRC_PORT_UDP)
301 /* IBV hash bits for L4 DST. */
302 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
303 IBV_RX_HASH_DST_PORT_UDP)
305 /* Geneve header first 16Bit */
306 #define MLX5_GENEVE_VER_MASK 0x3
307 #define MLX5_GENEVE_VER_SHIFT 14
308 #define MLX5_GENEVE_VER_VAL(a) \
309 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
310 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
311 #define MLX5_GENEVE_OPTLEN_SHIFT 7
312 #define MLX5_GENEVE_OPTLEN_VAL(a) \
313 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
314 #define MLX5_GENEVE_OAMF_MASK 0x1
315 #define MLX5_GENEVE_OAMF_SHIFT 7
316 #define MLX5_GENEVE_OAMF_VAL(a) \
317 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
318 #define MLX5_GENEVE_CRITO_MASK 0x1
319 #define MLX5_GENEVE_CRITO_SHIFT 6
320 #define MLX5_GENEVE_CRITO_VAL(a) \
321 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
322 #define MLX5_GENEVE_RSVD_MASK 0x3F
323 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
325 * The length of the Geneve options fields, expressed in four byte multiples,
326 * not including the eight byte fixed tunnel.
328 #define MLX5_GENEVE_OPT_LEN_0 14
329 #define MLX5_GENEVE_OPT_LEN_1 63
331 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
332 sizeof(struct rte_flow_item_ipv4))
334 /* Software header modify action numbers of a flow. */
335 #define MLX5_ACT_NUM_MDF_IPV4 1
336 #define MLX5_ACT_NUM_MDF_IPV6 4
337 #define MLX5_ACT_NUM_MDF_MAC 2
338 #define MLX5_ACT_NUM_MDF_VID 1
339 #define MLX5_ACT_NUM_MDF_PORT 2
340 #define MLX5_ACT_NUM_MDF_TTL 1
341 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
342 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
343 #define MLX5_ACT_NUM_MDF_TCPACK 1
344 #define MLX5_ACT_NUM_SET_REG 1
345 #define MLX5_ACT_NUM_SET_TAG 1
346 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
347 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
348 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
349 #define MLX5_ACT_NUM_SET_DSCP 1
351 enum mlx5_flow_drv_type {
354 MLX5_FLOW_TYPE_VERBS,
358 /* Fate action type. */
359 enum mlx5_flow_fate_type {
360 MLX5_FLOW_FATE_NONE, /* Egress flow. */
361 MLX5_FLOW_FATE_QUEUE,
363 MLX5_FLOW_FATE_PORT_ID,
365 MLX5_FLOW_FATE_DEFAULT_MISS,
369 /* Matcher PRM representation */
370 struct mlx5_flow_dv_match_params {
372 /**< Size of match value. Do NOT split size and key! */
373 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
374 /**< Matcher value. This value is used as the mask or as a key. */
377 /* Matcher structure. */
378 struct mlx5_flow_dv_matcher {
379 LIST_ENTRY(mlx5_flow_dv_matcher) next;
380 /**< Pointer to the next element. */
381 struct mlx5_flow_tbl_resource *tbl;
382 /**< Pointer to the table(group) the matcher associated with. */
383 rte_atomic32_t refcnt; /**< Reference counter. */
384 void *matcher_object; /**< Pointer to DV matcher */
385 uint16_t crc; /**< CRC of key. */
386 uint16_t priority; /**< Priority of matcher. */
387 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
390 #define MLX5_ENCAP_MAX_LEN 132
392 /* Encap/decap resource key of the hash organization. */
393 union mlx5_flow_encap_decap_key {
395 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
396 uint32_t refmt_type:8; /**< Header reformat type. */
397 uint32_t buf_size:8; /**< Encap buf size. */
398 uint32_t table_level:8; /**< Root table or not. */
399 uint32_t cksum; /**< Encap buf check sum. */
401 uint64_t v64; /**< full 64bits value of key */
404 /* Encap/decap resource structure. */
405 struct mlx5_flow_dv_encap_decap_resource {
406 struct mlx5_hlist_entry entry;
407 /* Pointer to next element. */
408 rte_atomic32_t refcnt; /**< Reference counter. */
410 /**< Encap/decap action object. */
411 uint8_t buf[MLX5_ENCAP_MAX_LEN];
413 uint8_t reformat_type;
415 uint64_t flags; /**< Flags for RDMA API. */
416 uint32_t idx; /**< Index for the index memory pool. */
419 /* Tag resource structure. */
420 struct mlx5_flow_dv_tag_resource {
421 struct mlx5_hlist_entry entry;
422 /**< hash list entry for tag resource, tag value as the key. */
424 /**< Tag action object. */
425 rte_atomic32_t refcnt; /**< Reference counter. */
426 uint32_t idx; /**< Index for the index memory pool. */
430 * Number of modification commands.
431 * The maximal actions amount in FW is some constant, and it is 16 in the
432 * latest releases. In some old releases, it will be limited to 8.
433 * Since there is no interface to query the capacity, the maximal value should
434 * be used to allow PMD to create the flow. The validation will be done in the
435 * lower driver layer or FW. A failure will be returned if exceeds the maximal
436 * supported actions number on the root table.
437 * On non-root tables, there is no limitation, but 32 is enough right now.
439 #define MLX5_MAX_MODIFY_NUM 32
440 #define MLX5_ROOT_TBL_MODIFY_NUM 16
442 /* Modify resource structure */
443 struct mlx5_flow_dv_modify_hdr_resource {
444 struct mlx5_hlist_entry entry;
445 /* Pointer to next element. */
446 rte_atomic32_t refcnt; /**< Reference counter. */
448 /**< Modify header action object. */
449 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
450 uint32_t actions_num; /**< Number of modification actions. */
451 uint64_t flags; /**< Flags for RDMA API. */
452 struct mlx5_modification_cmd actions[];
453 /**< Modification actions. */
456 /* Modify resource key of the hash organization. */
457 union mlx5_flow_modify_hdr_key {
459 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
460 uint32_t actions_num:5; /**< Number of modification actions. */
461 uint32_t group:19; /**< Flow group id. */
462 uint32_t cksum; /**< Actions check sum. */
464 uint64_t v64; /**< full 64bits value of key */
467 /* Jump action resource structure. */
468 struct mlx5_flow_dv_jump_tbl_resource {
469 rte_atomic32_t refcnt; /**< Reference counter. */
470 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
471 void *action; /**< Pointer to the rdma core action. */
474 /* Port ID resource structure. */
475 struct mlx5_flow_dv_port_id_action_resource {
476 ILIST_ENTRY(uint32_t)next;
477 /* Pointer to next element. */
478 rte_atomic32_t refcnt; /**< Reference counter. */
480 /**< Action object. */
481 uint32_t port_id; /**< Port ID value. */
484 /* Push VLAN action resource structure */
485 struct mlx5_flow_dv_push_vlan_action_resource {
486 ILIST_ENTRY(uint32_t)next;
487 /* Pointer to next element. */
488 rte_atomic32_t refcnt; /**< Reference counter. */
489 void *action; /**< Action object. */
490 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
491 rte_be32_t vlan_tag; /**< VLAN tag value. */
494 /* Metadata register copy table entry. */
495 struct mlx5_flow_mreg_copy_resource {
497 * Hash list entry for copy table.
498 * - Key is 32/64-bit MARK action ID.
499 * - MUST be the first entry.
501 struct mlx5_hlist_entry hlist_ent;
502 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
503 /* List entry for device flows. */
504 uint32_t refcnt; /* Reference counter. */
505 uint32_t appcnt; /* Apply/Remove counter. */
507 uint32_t rix_flow; /* Built flow for copy. */
510 /* Table data structure of the hash organization. */
511 struct mlx5_flow_tbl_data_entry {
512 struct mlx5_hlist_entry entry;
513 /**< hash list entry, 64-bits key inside. */
514 struct mlx5_flow_tbl_resource tbl;
515 /**< flow table resource. */
516 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
517 /**< matchers' header associated with the flow table. */
518 struct mlx5_flow_dv_jump_tbl_resource jump;
519 /**< jump resource, at most one for each table created. */
520 uint32_t idx; /**< index for the indexed mempool. */
523 /* Verbs specification header. */
524 struct ibv_spec_header {
525 enum ibv_flow_spec_type type;
529 /* RSS description. */
530 struct mlx5_flow_rss_desc {
532 uint32_t queue_num; /**< Number of entries in @p queue. */
533 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
534 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
535 uint16_t queue[]; /**< Destination queues to redirect traffic to. */
538 /* PMD flow priority for tunnel */
539 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
540 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
543 /** Device flow handle structure for DV mode only. */
544 struct mlx5_flow_handle_dv {
546 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
547 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
548 /**< Pointer to modify header resource in cache. */
549 uint32_t rix_encap_decap;
550 /**< Index to encap/decap resource in cache. */
551 uint32_t rix_push_vlan;
552 /**< Index to push VLAN action resource in cache. */
554 /**< Index to the tag action. */
557 /** Device flow handle structure: used both for creating & destroying. */
558 struct mlx5_flow_handle {
559 SILIST_ENTRY(uint32_t)next;
560 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
561 /**< Index to next device flow handle. */
563 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
564 void *drv_flow; /**< pointer to driver flow object. */
565 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
566 uint32_t mark:1; /**< Metadate rxq mark flag. */
567 uint32_t fate_action:3; /**< Fate action type. */
569 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
570 uint32_t rix_jump; /**< Index to the jump action resource. */
571 uint32_t rix_port_id_action;
572 /**< Index to port ID action resource. */
574 /**< Generic value indicates the fate action. */
575 uint32_t rix_default_fate;
576 /**< Indicates default miss fate action. */
578 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
579 struct mlx5_flow_handle_dv dvh;
584 * Size for Verbs device flow handle structure only. Do not use the DV only
585 * structure in Verbs. No DV flows attributes will be accessed.
586 * Macro offsetof() could also be used here.
588 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
589 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
590 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
592 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
596 * Max number of actions per DV flow.
597 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
598 * in rdma-core file providers/mlx5/verbs.c.
600 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
602 /** Device flow structure only for DV flow creation. */
603 struct mlx5_flow_dv_workspace {
604 uint32_t group; /**< The group index. */
605 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
606 int actions_n; /**< number of actions. */
607 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
608 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
609 /**< Pointer to encap/decap resource in cache. */
610 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
611 /**< Pointer to push VLAN action resource in cache. */
612 struct mlx5_flow_dv_tag_resource *tag_resource;
613 /**< pointer to the tag action. */
614 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
615 /**< Pointer to port ID action resource. */
616 struct mlx5_flow_dv_jump_tbl_resource *jump;
617 /**< Pointer to the jump action resource. */
618 struct mlx5_flow_dv_match_params value;
619 /**< Holds the value that the packet is compared to. */
623 * Maximal Verbs flow specifications & actions size.
624 * Some elements are mutually exclusive, but enough space should be allocated.
625 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
626 * 2. One tunnel header (exception: GRE + MPLS),
627 * SPEC length: GRE == tunnel.
628 * Actions: 1. 1 Mark OR Flag.
629 * 2. 1 Drop (if any).
630 * 3. No limitation for counters, but it makes no sense to support too
631 * many counters in a single device flow.
633 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
634 #define MLX5_VERBS_MAX_SPEC_SIZE \
636 (2 * (sizeof(struct ibv_flow_spec_eth) + \
637 sizeof(struct ibv_flow_spec_ipv6) + \
638 sizeof(struct ibv_flow_spec_tcp_udp)) + \
639 sizeof(struct ibv_flow_spec_gre) + \
640 sizeof(struct ibv_flow_spec_mpls)) \
643 #define MLX5_VERBS_MAX_SPEC_SIZE \
645 (2 * (sizeof(struct ibv_flow_spec_eth) + \
646 sizeof(struct ibv_flow_spec_ipv6) + \
647 sizeof(struct ibv_flow_spec_tcp_udp)) + \
648 sizeof(struct ibv_flow_spec_tunnel)) \
652 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
653 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
654 #define MLX5_VERBS_MAX_ACT_SIZE \
656 sizeof(struct ibv_flow_spec_action_tag) + \
657 sizeof(struct ibv_flow_spec_action_drop) + \
658 sizeof(struct ibv_flow_spec_counter_action) * 4 \
661 #define MLX5_VERBS_MAX_ACT_SIZE \
663 sizeof(struct ibv_flow_spec_action_tag) + \
664 sizeof(struct ibv_flow_spec_action_drop) \
668 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
669 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
671 /** Device flow structure only for Verbs flow creation. */
672 struct mlx5_flow_verbs_workspace {
673 unsigned int size; /**< Size of the attribute. */
674 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
675 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
676 /**< Specifications & actions buffer of verbs flow. */
679 /** Maximal number of device sub-flows supported. */
680 #define MLX5_NUM_MAX_DEV_FLOWS 32
682 /** Device flow structure. */
684 struct rte_flow *flow; /**< Pointer to the main flow. */
685 uint32_t flow_idx; /**< The memory pool index to the main flow. */
686 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
688 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
689 bool external; /**< true if the flow is created external to PMD. */
690 uint8_t ingress; /**< 1 if the flow is ingress. */
692 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
693 struct mlx5_flow_dv_workspace dv;
695 struct mlx5_flow_verbs_workspace verbs;
697 struct mlx5_flow_handle *handle;
698 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
701 /* Flow meter state. */
702 #define MLX5_FLOW_METER_DISABLE 0
703 #define MLX5_FLOW_METER_ENABLE 1
705 #define MLX5_MAN_WIDTH 8
706 /* Modify this value if enum rte_mtr_color changes. */
707 #define RTE_MTR_DROPPED RTE_COLORS
709 /* Meter policer statistics */
710 struct mlx5_flow_policer_stats {
711 uint32_t cnt[RTE_COLORS + 1];
712 /**< Color counter, extra for drop. */
714 /**< Statistics mask for the colors. */
717 /* Meter table structure. */
718 struct mlx5_meter_domain_info {
719 struct mlx5_flow_tbl_resource *tbl;
721 struct mlx5_flow_tbl_resource *sfx_tbl;
722 /**< Meter suffix table. */
724 /**< Meter color not match default criteria. */
726 /**< Meter color match criteria. */
728 /**< Meter match action. */
729 void *policer_rules[RTE_MTR_DROPPED + 1];
730 /**< Meter policer for the match. */
733 /* Meter table set for TX RX FDB. */
734 struct mlx5_meter_domains_infos {
736 /**< Table user count. */
737 struct mlx5_meter_domain_info egress;
738 /**< TX meter table. */
739 struct mlx5_meter_domain_info ingress;
740 /**< RX meter table. */
741 struct mlx5_meter_domain_info transfer;
742 /**< FDB meter table. */
744 /**< Drop action as not matched. */
745 void *count_actns[RTE_MTR_DROPPED + 1];
746 /**< Counters for match and unmatched statistics. */
747 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
748 /**< Flow meter parameter. */
750 /**< Flow meter parameter size. */
752 /**< Flow meter action. */
755 /* Meter parameter structure. */
756 struct mlx5_flow_meter {
757 TAILQ_ENTRY(mlx5_flow_meter) next;
758 /**< Pointer to the next flow meter structure. */
759 uint32_t idx; /* Index to meter object. */
762 struct mlx5_flow_meter_profile *profile;
763 /**< Meter profile parameters. */
765 /** Policer actions (per meter output color). */
766 enum rte_mtr_policer_action action[RTE_COLORS];
768 /** Set of stats counters to be enabled.
769 * @see enum rte_mtr_stats_type
773 /**< Rule applies to ingress traffic. */
776 /**< Rule applies to egress traffic. */
779 * Instead of simply matching the properties of traffic as it would
780 * appear on a given DPDK port ID, enabling this attribute transfers
781 * a flow rule to the lowest possible level of any device endpoints
782 * found in the pattern.
784 * When supported, this effectively enables an application to
785 * re-route traffic not necessarily intended for it (e.g. coming
786 * from or addressed to different physical ports, VFs or
787 * applications) at the device level.
789 * It complements the behavior of some pattern items such as
790 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
792 * When transferring flow rules, ingress and egress attributes keep
793 * their original meaning, as if processing traffic emitted or
794 * received by the application.
797 struct mlx5_meter_domains_infos *mfts;
798 /**< Flow table created for this meter. */
799 struct mlx5_flow_policer_stats policer_stats;
800 /**< Meter policer statistics. */
803 uint32_t active_state:1;
806 /**< Meter shared or not. */
809 /* RFC2697 parameter structure. */
810 struct mlx5_flow_meter_srtcm_rfc2697_prm {
811 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
812 uint32_t cbs_exponent:5;
813 uint32_t cbs_mantissa:8;
814 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
815 uint32_t cir_exponent:5;
816 uint32_t cir_mantissa:8;
817 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
818 uint32_t ebs_exponent:5;
819 uint32_t ebs_mantissa:8;
822 /* Flow meter profile structure. */
823 struct mlx5_flow_meter_profile {
824 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
825 /**< Pointer to the next flow meter structure. */
826 uint32_t meter_profile_id; /**< Profile id. */
827 struct rte_mtr_meter_profile profile; /**< Profile detail. */
829 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
830 /**< srtcm_rfc2697 struct. */
832 uint32_t ref_cnt; /**< Use count. */
835 /* Fdir flow structure */
836 struct mlx5_fdir_flow {
837 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */
838 struct mlx5_fdir *fdir; /* Pointer to fdir. */
839 uint32_t rix_flow; /* Index to flow. */
842 #define HAIRPIN_FLOW_ID_BITS 28
844 /* Flow structure. */
846 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
847 uint32_t dev_handles;
848 /**< Device flow handles that are part of the flow. */
849 uint32_t drv_type:2; /**< Driver type. */
850 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */
851 uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS;
852 /**< The flow id used for hairpin. */
853 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
854 uint32_t rix_mreg_copy;
855 /**< Index to metadata register copy table resource. */
856 uint32_t counter; /**< Holds flow counter. */
857 uint16_t meter; /**< Holds flow meter id. */
860 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
861 const struct rte_flow_attr *attr,
862 const struct rte_flow_item items[],
863 const struct rte_flow_action actions[],
866 struct rte_flow_error *error);
867 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
868 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
869 const struct rte_flow_item items[],
870 const struct rte_flow_action actions[], struct rte_flow_error *error);
871 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
872 struct mlx5_flow *dev_flow,
873 const struct rte_flow_attr *attr,
874 const struct rte_flow_item items[],
875 const struct rte_flow_action actions[],
876 struct rte_flow_error *error);
877 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
878 struct rte_flow_error *error);
879 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
880 struct rte_flow *flow);
881 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
882 struct rte_flow *flow);
883 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
884 struct rte_flow *flow,
885 const struct rte_flow_action *actions,
887 struct rte_flow_error *error);
888 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
889 (struct rte_eth_dev *dev,
890 const struct mlx5_flow_meter *fm);
891 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
892 struct mlx5_meter_domains_infos *tbls);
893 typedef int (*mlx5_flow_create_policer_rules_t)
894 (struct rte_eth_dev *dev,
895 struct mlx5_flow_meter *fm,
896 const struct rte_flow_attr *attr);
897 typedef int (*mlx5_flow_destroy_policer_rules_t)
898 (struct rte_eth_dev *dev,
899 const struct mlx5_flow_meter *fm,
900 const struct rte_flow_attr *attr);
901 typedef uint32_t (*mlx5_flow_counter_alloc_t)
902 (struct rte_eth_dev *dev);
903 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
905 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
907 bool clear, uint64_t *pkts,
909 typedef int (*mlx5_flow_get_aged_flows_t)
910 (struct rte_eth_dev *dev,
912 uint32_t nb_contexts,
913 struct rte_flow_error *error);
914 struct mlx5_flow_driver_ops {
915 mlx5_flow_validate_t validate;
916 mlx5_flow_prepare_t prepare;
917 mlx5_flow_translate_t translate;
918 mlx5_flow_apply_t apply;
919 mlx5_flow_remove_t remove;
920 mlx5_flow_destroy_t destroy;
921 mlx5_flow_query_t query;
922 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
923 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
924 mlx5_flow_create_policer_rules_t create_policer_rules;
925 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
926 mlx5_flow_counter_alloc_t counter_alloc;
927 mlx5_flow_counter_free_t counter_free;
928 mlx5_flow_counter_query_t counter_query;
929 mlx5_flow_get_aged_flows_t get_aged_flows;
934 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id);
935 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
936 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
937 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
939 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
940 bool external, uint32_t group, bool fdb_def_rule,
941 uint32_t *table, struct rte_flow_error *error);
942 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
943 int tunnel, uint64_t layer_types,
944 uint64_t hash_fields);
945 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
946 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
947 uint32_t subpriority);
948 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
949 enum mlx5_feature_name feature,
951 struct rte_flow_error *error);
952 const struct rte_flow_action *mlx5_flow_find_action
953 (const struct rte_flow_action *actions,
954 enum rte_flow_action_type action);
955 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
956 const struct rte_flow_attr *attr,
957 struct rte_flow_error *error);
958 int mlx5_flow_validate_action_drop(uint64_t action_flags,
959 const struct rte_flow_attr *attr,
960 struct rte_flow_error *error);
961 int mlx5_flow_validate_action_flag(uint64_t action_flags,
962 const struct rte_flow_attr *attr,
963 struct rte_flow_error *error);
964 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
965 uint64_t action_flags,
966 const struct rte_flow_attr *attr,
967 struct rte_flow_error *error);
968 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
969 uint64_t action_flags,
970 struct rte_eth_dev *dev,
971 const struct rte_flow_attr *attr,
972 struct rte_flow_error *error);
973 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
974 uint64_t action_flags,
975 struct rte_eth_dev *dev,
976 const struct rte_flow_attr *attr,
978 struct rte_flow_error *error);
979 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
980 const struct rte_flow_attr *attr,
981 struct rte_flow_error *error);
982 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
983 const struct rte_flow_attr *attributes,
984 struct rte_flow_error *error);
985 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
987 const uint8_t *nic_mask,
989 struct rte_flow_error *error);
990 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
992 struct rte_flow_error *error);
993 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
995 uint8_t target_protocol,
996 struct rte_flow_error *error);
997 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
999 const struct rte_flow_item *gre_item,
1000 struct rte_flow_error *error);
1001 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1002 uint64_t item_flags,
1004 uint16_t ether_type,
1005 const struct rte_flow_item_ipv4 *acc_mask,
1006 struct rte_flow_error *error);
1007 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1008 uint64_t item_flags,
1010 uint16_t ether_type,
1011 const struct rte_flow_item_ipv6 *acc_mask,
1012 struct rte_flow_error *error);
1013 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1014 const struct rte_flow_item *item,
1015 uint64_t item_flags,
1016 uint64_t prev_layer,
1017 struct rte_flow_error *error);
1018 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1019 uint64_t item_flags,
1020 uint8_t target_protocol,
1021 const struct rte_flow_item_tcp *flow_mask,
1022 struct rte_flow_error *error);
1023 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1024 uint64_t item_flags,
1025 uint8_t target_protocol,
1026 struct rte_flow_error *error);
1027 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1028 uint64_t item_flags,
1029 struct rte_eth_dev *dev,
1030 struct rte_flow_error *error);
1031 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1032 uint64_t item_flags,
1033 struct rte_flow_error *error);
1034 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1035 uint64_t item_flags,
1036 struct rte_eth_dev *dev,
1037 struct rte_flow_error *error);
1038 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1039 uint64_t item_flags,
1040 uint8_t target_protocol,
1041 struct rte_flow_error *error);
1042 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1043 uint64_t item_flags,
1044 uint8_t target_protocol,
1045 struct rte_flow_error *error);
1046 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1047 uint64_t item_flags,
1048 uint8_t target_protocol,
1049 struct rte_flow_error *error);
1050 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1051 uint64_t item_flags,
1052 struct rte_eth_dev *dev,
1053 struct rte_flow_error *error);
1054 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1055 uint64_t item_flags,
1057 uint16_t ether_type,
1058 const struct rte_flow_item_ecpri *acc_mask,
1059 struct rte_flow_error *error);
1060 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1061 (struct rte_eth_dev *dev,
1062 const struct mlx5_flow_meter *fm);
1063 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1064 struct mlx5_meter_domains_infos *tbl);
1065 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1066 struct mlx5_flow_meter *fm,
1067 const struct rte_flow_attr *attr);
1068 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1069 struct mlx5_flow_meter *fm,
1070 const struct rte_flow_attr *attr);
1071 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1072 struct rte_mtr_error *error);
1073 #endif /* RTE_PMD_MLX5_FLOW_H_ */