1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
31 /* Private rte flow items. */
32 enum mlx5_rte_flow_item_type {
33 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
35 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
38 /* Private (internal) rte flow actions. */
39 enum mlx5_rte_flow_action_type {
40 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
41 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
42 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
43 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
46 /* Matches on selected register. */
47 struct mlx5_rte_flow_item_tag {
52 /* Modify selected register. */
53 struct mlx5_rte_flow_action_set_tag {
58 struct mlx5_flow_action_copy_mreg {
63 /* Matches on source queue. */
64 struct mlx5_rte_flow_item_tx_queue {
68 /* Feature name to allocate metadata register. */
69 enum mlx5_feature_name {
82 /* Pattern outer Layer bits. */
83 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
84 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
85 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
86 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
87 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
88 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
90 /* Pattern inner Layer bits. */
91 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
92 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
93 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
94 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
95 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
96 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
98 /* Pattern tunnel Layer bits. */
99 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
100 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
101 #define MLX5_FLOW_LAYER_GRE (1u << 14)
102 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
103 /* List of tunnel Layer bits continued below. */
105 /* General pattern items bits. */
106 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
107 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
108 #define MLX5_FLOW_ITEM_TAG (1u << 18)
109 #define MLX5_FLOW_ITEM_MARK (1u << 19)
111 /* Pattern MISC bits. */
112 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
113 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
114 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
116 /* Pattern tunnel Layer bits (continued). */
117 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
118 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
119 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
120 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
123 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
125 /* Pattern tunnel Layer bits (continued). */
126 #define MLX5_FLOW_LAYER_GTP (1u << 28)
129 #define MLX5_FLOW_LAYER_OUTER_L3 \
130 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
131 #define MLX5_FLOW_LAYER_OUTER_L4 \
132 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
133 #define MLX5_FLOW_LAYER_OUTER \
134 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
135 MLX5_FLOW_LAYER_OUTER_L4)
138 #define MLX5_FLOW_LAYER_TUNNEL \
139 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
140 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
141 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
142 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
145 #define MLX5_FLOW_LAYER_INNER_L3 \
146 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
147 #define MLX5_FLOW_LAYER_INNER_L4 \
148 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
149 #define MLX5_FLOW_LAYER_INNER \
150 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
151 MLX5_FLOW_LAYER_INNER_L4)
154 #define MLX5_FLOW_LAYER_L2 \
155 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
156 #define MLX5_FLOW_LAYER_L3_IPV4 \
157 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
158 #define MLX5_FLOW_LAYER_L3_IPV6 \
159 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
160 #define MLX5_FLOW_LAYER_L3 \
161 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
162 #define MLX5_FLOW_LAYER_L4 \
163 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
166 #define MLX5_FLOW_ACTION_DROP (1u << 0)
167 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
168 #define MLX5_FLOW_ACTION_RSS (1u << 2)
169 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
170 #define MLX5_FLOW_ACTION_MARK (1u << 4)
171 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
172 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
173 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
174 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
175 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
176 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
177 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
178 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
179 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
180 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
181 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
182 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
183 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
184 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
185 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
186 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
187 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
188 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
189 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
190 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
191 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
192 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
193 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
194 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
195 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
196 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
197 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
198 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
199 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33)
200 #define MLX5_FLOW_ACTION_SET_META (1ull << 34)
201 #define MLX5_FLOW_ACTION_METER (1ull << 35)
202 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 36)
203 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 37)
205 #define MLX5_FLOW_FATE_ACTIONS \
206 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
207 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
209 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
210 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
211 MLX5_FLOW_ACTION_JUMP)
213 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
214 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
215 MLX5_FLOW_ACTION_RAW_ENCAP)
217 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
218 MLX5_FLOW_ACTION_NVGRE_DECAP | \
219 MLX5_FLOW_ACTION_RAW_DECAP)
221 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
222 MLX5_FLOW_ACTION_SET_IPV4_DST | \
223 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
224 MLX5_FLOW_ACTION_SET_IPV6_DST | \
225 MLX5_FLOW_ACTION_SET_TP_SRC | \
226 MLX5_FLOW_ACTION_SET_TP_DST | \
227 MLX5_FLOW_ACTION_SET_TTL | \
228 MLX5_FLOW_ACTION_DEC_TTL | \
229 MLX5_FLOW_ACTION_SET_MAC_SRC | \
230 MLX5_FLOW_ACTION_SET_MAC_DST | \
231 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
232 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
233 MLX5_FLOW_ACTION_INC_TCP_ACK | \
234 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
235 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
236 MLX5_FLOW_ACTION_SET_TAG | \
237 MLX5_FLOW_ACTION_MARK_EXT | \
238 MLX5_FLOW_ACTION_SET_META | \
239 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
240 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
242 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
243 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
245 #define IPPROTO_MPLS 137
248 /* UDP port number for MPLS */
249 #define MLX5_UDP_PORT_MPLS 6635
251 /* UDP port numbers for VxLAN. */
252 #define MLX5_UDP_PORT_VXLAN 4789
253 #define MLX5_UDP_PORT_VXLAN_GPE 4790
255 /* UDP port numbers for GENEVE. */
256 #define MLX5_UDP_PORT_GENEVE 6081
258 /* Priority reserved for default flows. */
259 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
262 * Number of sub priorities.
263 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
264 * matching on the NIC (firmware dependent) L4 most have the higher priority
265 * followed by L3 and ending with L2.
267 #define MLX5_PRIORITY_MAP_L2 2
268 #define MLX5_PRIORITY_MAP_L3 1
269 #define MLX5_PRIORITY_MAP_L4 0
270 #define MLX5_PRIORITY_MAP_MAX 3
272 /* Valid layer type for IPV4 RSS. */
273 #define MLX5_IPV4_LAYER_TYPES \
274 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
275 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
276 ETH_RSS_NONFRAG_IPV4_OTHER)
278 /* IBV hash source bits for IPV4. */
279 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
281 /* Valid layer type for IPV6 RSS. */
282 #define MLX5_IPV6_LAYER_TYPES \
283 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
284 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
285 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
287 /* IBV hash source bits for IPV6. */
288 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
290 /* IBV hash bits for L3 SRC. */
291 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
293 /* IBV hash bits for L3 DST. */
294 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
296 /* IBV hash bits for TCP. */
297 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
298 IBV_RX_HASH_DST_PORT_TCP)
300 /* IBV hash bits for UDP. */
301 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
302 IBV_RX_HASH_DST_PORT_UDP)
304 /* IBV hash bits for L4 SRC. */
305 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
306 IBV_RX_HASH_SRC_PORT_UDP)
308 /* IBV hash bits for L4 DST. */
309 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
310 IBV_RX_HASH_DST_PORT_UDP)
312 /* Geneve header first 16Bit */
313 #define MLX5_GENEVE_VER_MASK 0x3
314 #define MLX5_GENEVE_VER_SHIFT 14
315 #define MLX5_GENEVE_VER_VAL(a) \
316 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
317 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
318 #define MLX5_GENEVE_OPTLEN_SHIFT 7
319 #define MLX5_GENEVE_OPTLEN_VAL(a) \
320 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
321 #define MLX5_GENEVE_OAMF_MASK 0x1
322 #define MLX5_GENEVE_OAMF_SHIFT 7
323 #define MLX5_GENEVE_OAMF_VAL(a) \
324 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
325 #define MLX5_GENEVE_CRITO_MASK 0x1
326 #define MLX5_GENEVE_CRITO_SHIFT 6
327 #define MLX5_GENEVE_CRITO_VAL(a) \
328 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
329 #define MLX5_GENEVE_RSVD_MASK 0x3F
330 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
332 * The length of the Geneve options fields, expressed in four byte multiples,
333 * not including the eight byte fixed tunnel.
335 #define MLX5_GENEVE_OPT_LEN_0 14
336 #define MLX5_GENEVE_OPT_LEN_1 63
338 enum mlx5_flow_drv_type {
341 MLX5_FLOW_TYPE_VERBS,
345 /* Matcher PRM representation */
346 struct mlx5_flow_dv_match_params {
348 /**< Size of match value. Do NOT split size and key! */
349 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
350 /**< Matcher value. This value is used as the mask or as a key. */
353 /* Matcher structure. */
354 struct mlx5_flow_dv_matcher {
355 LIST_ENTRY(mlx5_flow_dv_matcher) next;
356 /**< Pointer to the next element. */
357 struct mlx5_flow_tbl_resource *tbl;
358 /**< Pointer to the table(group) the matcher associated with. */
359 rte_atomic32_t refcnt; /**< Reference counter. */
360 void *matcher_object; /**< Pointer to DV matcher */
361 uint16_t crc; /**< CRC of key. */
362 uint16_t priority; /**< Priority of matcher. */
363 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
366 #define MLX5_ENCAP_MAX_LEN 132
368 /* Encap/decap resource structure. */
369 struct mlx5_flow_dv_encap_decap_resource {
370 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
371 /* Pointer to next element. */
372 rte_atomic32_t refcnt; /**< Reference counter. */
374 /**< Verbs encap/decap action object. */
375 uint8_t buf[MLX5_ENCAP_MAX_LEN];
377 uint8_t reformat_type;
379 uint64_t flags; /**< Flags for RDMA API. */
382 /* Tag resource structure. */
383 struct mlx5_flow_dv_tag_resource {
384 struct mlx5_hlist_entry entry;
385 /**< hash list entry for tag resource, tag value as the key. */
387 /**< Verbs tag action object. */
388 rte_atomic32_t refcnt; /**< Reference counter. */
392 * Number of modification commands.
393 * If extensive metadata registers are supported, the maximal actions amount is
394 * 16 and 8 otherwise on root table. The validation could also be done in the
395 * lower driver layer.
396 * On non-root table, there is no limitation, but 32 is enough right now.
398 #define MLX5_MAX_MODIFY_NUM 32
399 #define MLX5_ROOT_TBL_MODIFY_NUM 16
400 #define MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG 8
402 /* Modify resource structure */
403 struct mlx5_flow_dv_modify_hdr_resource {
404 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
405 /* Pointer to next element. */
406 rte_atomic32_t refcnt; /**< Reference counter. */
407 struct ibv_flow_action *verbs_action;
408 /**< Verbs modify header action object. */
409 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
410 uint32_t actions_num; /**< Number of modification actions. */
411 uint64_t flags; /**< Flags for RDMA API. */
412 struct mlx5_modification_cmd actions[];
413 /**< Modification actions. */
416 /* Jump action resource structure. */
417 struct mlx5_flow_dv_jump_tbl_resource {
418 rte_atomic32_t refcnt; /**< Reference counter. */
419 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
420 void *action; /**< Pointer to the rdma core action. */
423 /* Port ID resource structure. */
424 struct mlx5_flow_dv_port_id_action_resource {
425 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
426 /* Pointer to next element. */
427 rte_atomic32_t refcnt; /**< Reference counter. */
429 /**< Verbs tag action object. */
430 uint32_t port_id; /**< Port ID value. */
433 /* Push VLAN action resource structure */
434 struct mlx5_flow_dv_push_vlan_action_resource {
435 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
436 /* Pointer to next element. */
437 rte_atomic32_t refcnt; /**< Reference counter. */
438 void *action; /**< Direct verbs action object. */
439 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
440 rte_be32_t vlan_tag; /**< VLAN tag value. */
443 /* Metadata register copy table entry. */
444 struct mlx5_flow_mreg_copy_resource {
446 * Hash list entry for copy table.
447 * - Key is 32/64-bit MARK action ID.
448 * - MUST be the first entry.
450 struct mlx5_hlist_entry hlist_ent;
451 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
452 /* List entry for device flows. */
453 uint32_t refcnt; /* Reference counter. */
454 uint32_t appcnt; /* Apply/Remove counter. */
455 struct rte_flow *flow; /* Built flow for copy. */
458 /* Table data structure of the hash organization. */
459 struct mlx5_flow_tbl_data_entry {
460 struct mlx5_hlist_entry entry;
461 /**< hash list entry, 64-bits key inside. */
462 struct mlx5_flow_tbl_resource tbl;
463 /**< flow table resource. */
464 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
465 /**< matchers' header associated with the flow table. */
466 struct mlx5_flow_dv_jump_tbl_resource jump;
467 /**< jump resource, at most one for each table created. */
471 * Max number of actions per DV flow.
472 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
473 * In rdma-core file providers/mlx5/verbs.c
475 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
477 /* DV flows structure. */
478 struct mlx5_flow_dv {
479 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
481 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
482 struct mlx5_flow_dv_match_params value;
483 /**< Holds the value that the packet is compared to. */
484 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
485 /**< Pointer to encap/decap resource in cache. */
486 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
487 /**< Pointer to modify header resource in cache. */
488 struct ibv_flow *flow; /**< Installed flow. */
489 struct mlx5_flow_dv_jump_tbl_resource *jump;
490 /**< Pointer to the jump action resource. */
491 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
492 /**< Pointer to port ID action resource. */
493 struct mlx5_vf_vlan vf_vlan;
494 /**< Structure for VF VLAN workaround. */
495 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
496 /**< Pointer to push VLAN action resource in cache. */
497 struct mlx5_flow_dv_tag_resource *tag_resource;
498 /**< pointer to the tag action. */
499 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
500 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
503 int actions_n; /**< number of actions. */
506 /* Verbs specification header. */
507 struct ibv_spec_header {
508 enum ibv_flow_spec_type type;
512 /** Handles information leading to a drop fate. */
513 struct mlx5_flow_verbs {
514 LIST_ENTRY(mlx5_flow_verbs) next;
515 unsigned int size; /**< Size of the attribute. */
517 struct ibv_flow_attr *attr;
518 /**< Pointer to the Specification buffer. */
519 uint8_t *specs; /**< Pointer to the specifications. */
521 struct ibv_flow *flow; /**< Verbs flow pointer. */
522 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
523 struct mlx5_vf_vlan vf_vlan;
524 /**< Structure for VF VLAN workaround. */
527 struct mlx5_flow_rss {
529 uint32_t queue_num; /**< Number of entries in @p queue. */
530 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
531 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
532 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
535 /** Device flow structure. */
537 LIST_ENTRY(mlx5_flow) next;
538 struct rte_flow *flow; /**< Pointer to the main flow. */
540 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
542 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
543 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
544 uint8_t ingress; /**< 1 if the flow is ingress. */
545 uint32_t group; /**< The group index. */
546 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
548 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
549 struct mlx5_flow_dv dv;
551 struct mlx5_flow_verbs verbs;
554 uint32_t qrss_id; /**< Uniqie Q/RSS suffix subflow tag. */
555 uint32_t mtr_flow_id; /**< Unique meter match flow id. */
557 bool external; /**< true if the flow is created external to PMD. */
560 /* Flow meter state. */
561 #define MLX5_FLOW_METER_DISABLE 0
562 #define MLX5_FLOW_METER_ENABLE 1
564 #define MLX5_MAN_WIDTH 8
565 /* Modify this value if enum rte_mtr_color changes. */
566 #define RTE_MTR_DROPPED RTE_COLORS
568 /* Meter policer statistics */
569 struct mlx5_flow_policer_stats {
570 struct mlx5_flow_counter *cnt[RTE_COLORS + 1];
571 /**< Color counter, extra for drop. */
573 /**< Statistics mask for the colors. */
576 /* Meter table structure. */
577 struct mlx5_meter_domain_info {
578 struct mlx5_flow_tbl_resource *tbl;
581 /**< Meter color not match default criteria. */
583 /**< Meter color match criteria. */
585 /**< Meter match action. */
586 void *policer_rules[RTE_MTR_DROPPED + 1];
587 /**< Meter policer for the match. */
590 /* Meter table set for TX RX FDB. */
591 struct mlx5_meter_domains_infos {
593 /**< Table user count. */
594 struct mlx5_meter_domain_info egress;
595 /**< TX meter table. */
596 struct mlx5_meter_domain_info ingress;
597 /**< RX meter table. */
598 struct mlx5_meter_domain_info transfer;
599 /**< FDB meter table. */
601 /**< Drop action as not matched. */
602 void *count_actns[RTE_MTR_DROPPED + 1];
603 /**< Counters for match and unmatched statistics. */
604 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
605 /**< Flow meter parameter. */
607 /**< Flow meter parameter size. */
609 /**< Flow meter action. */
612 /* Meter parameter structure. */
613 struct mlx5_flow_meter {
614 TAILQ_ENTRY(mlx5_flow_meter) next;
615 /**< Pointer to the next flow meter structure. */
618 struct rte_mtr_params params;
619 /**< Meter rule parameters. */
620 struct mlx5_flow_meter_profile *profile;
621 /**< Meter profile parameters. */
622 struct rte_flow_attr attr;
623 /**< Flow attributes. */
624 struct mlx5_meter_domains_infos *mfts;
625 /**< Flow table created for this meter. */
626 struct mlx5_flow_policer_stats policer_stats;
627 /**< Meter policer statistics. */
630 uint32_t active_state:1;
633 /**< Meter shared or not. */
636 /* RFC2697 parameter structure. */
637 struct mlx5_flow_meter_srtcm_rfc2697_prm {
638 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
639 uint32_t cbs_exponent:5;
640 uint32_t cbs_mantissa:8;
641 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
642 uint32_t cir_exponent:5;
643 uint32_t cir_mantissa:8;
644 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
645 uint32_t ebs_exponent:5;
646 uint32_t ebs_mantissa:8;
649 /* Flow meter profile structure. */
650 struct mlx5_flow_meter_profile {
651 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
652 /**< Pointer to the next flow meter structure. */
653 uint32_t meter_profile_id; /**< Profile id. */
654 struct rte_mtr_meter_profile profile; /**< Profile detail. */
656 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
657 /**< srtcm_rfc2697 struct. */
659 uint32_t ref_cnt; /**< Use count. */
662 /* Flow structure. */
664 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
665 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
666 struct mlx5_flow_rss rss; /**< RSS context. */
667 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
668 struct mlx5_flow_mreg_copy_resource *mreg_copy;
669 /**< pointer to metadata register copy table resource. */
670 struct mlx5_flow_meter *meter; /**< Holds flow meter. */
671 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
672 /**< Device flows that are part of the flow. */
673 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
674 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
675 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
678 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
679 const struct rte_flow_attr *attr,
680 const struct rte_flow_item items[],
681 const struct rte_flow_action actions[],
683 struct rte_flow_error *error);
684 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
685 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
686 const struct rte_flow_action actions[], struct rte_flow_error *error);
687 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
688 struct mlx5_flow *dev_flow,
689 const struct rte_flow_attr *attr,
690 const struct rte_flow_item items[],
691 const struct rte_flow_action actions[],
692 struct rte_flow_error *error);
693 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
694 struct rte_flow_error *error);
695 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
696 struct rte_flow *flow);
697 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
698 struct rte_flow *flow);
699 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
700 struct rte_flow *flow,
701 const struct rte_flow_action *actions,
703 struct rte_flow_error *error);
704 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
705 (struct rte_eth_dev *dev,
706 const struct mlx5_flow_meter *fm);
707 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
708 struct mlx5_meter_domains_infos *tbls);
709 typedef int (*mlx5_flow_create_policer_rules_t)
710 (struct rte_eth_dev *dev,
711 struct mlx5_flow_meter *fm,
712 const struct rte_flow_attr *attr);
713 typedef int (*mlx5_flow_destroy_policer_rules_t)
714 (struct rte_eth_dev *dev,
715 const struct mlx5_flow_meter *fm,
716 const struct rte_flow_attr *attr);
717 typedef struct mlx5_flow_counter * (*mlx5_flow_counter_alloc_t)
718 (struct rte_eth_dev *dev);
719 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
720 struct mlx5_flow_counter *cnt);
721 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
722 struct mlx5_flow_counter *cnt,
723 bool clear, uint64_t *pkts,
725 struct mlx5_flow_driver_ops {
726 mlx5_flow_validate_t validate;
727 mlx5_flow_prepare_t prepare;
728 mlx5_flow_translate_t translate;
729 mlx5_flow_apply_t apply;
730 mlx5_flow_remove_t remove;
731 mlx5_flow_destroy_t destroy;
732 mlx5_flow_query_t query;
733 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
734 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
735 mlx5_flow_create_policer_rules_t create_policer_rules;
736 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
737 mlx5_flow_counter_alloc_t counter_alloc;
738 mlx5_flow_counter_free_t counter_free;
739 mlx5_flow_counter_query_t counter_query;
743 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
744 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
745 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
746 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
750 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
751 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
752 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
753 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
755 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
756 bool external, uint32_t group, uint32_t *table,
757 struct rte_flow_error *error);
758 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
759 uint64_t layer_types,
760 uint64_t hash_fields);
761 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
762 uint32_t subpriority);
763 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
764 enum mlx5_feature_name feature,
766 struct rte_flow_error *error);
767 const struct rte_flow_action *mlx5_flow_find_action
768 (const struct rte_flow_action *actions,
769 enum rte_flow_action_type action);
770 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
771 const struct rte_flow_attr *attr,
772 struct rte_flow_error *error);
773 int mlx5_flow_validate_action_drop(uint64_t action_flags,
774 const struct rte_flow_attr *attr,
775 struct rte_flow_error *error);
776 int mlx5_flow_validate_action_flag(uint64_t action_flags,
777 const struct rte_flow_attr *attr,
778 struct rte_flow_error *error);
779 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
780 uint64_t action_flags,
781 const struct rte_flow_attr *attr,
782 struct rte_flow_error *error);
783 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
784 uint64_t action_flags,
785 struct rte_eth_dev *dev,
786 const struct rte_flow_attr *attr,
787 struct rte_flow_error *error);
788 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
789 uint64_t action_flags,
790 struct rte_eth_dev *dev,
791 const struct rte_flow_attr *attr,
793 struct rte_flow_error *error);
794 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
795 const struct rte_flow_attr *attributes,
796 struct rte_flow_error *error);
797 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
799 const uint8_t *nic_mask,
801 struct rte_flow_error *error);
802 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
804 struct rte_flow_error *error);
805 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
807 uint8_t target_protocol,
808 struct rte_flow_error *error);
809 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
811 const struct rte_flow_item *gre_item,
812 struct rte_flow_error *error);
813 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
817 const struct rte_flow_item_ipv4 *acc_mask,
818 struct rte_flow_error *error);
819 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
823 const struct rte_flow_item_ipv6 *acc_mask,
824 struct rte_flow_error *error);
825 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
826 const struct rte_flow_item *item,
829 struct rte_flow_error *error);
830 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
832 uint8_t target_protocol,
833 const struct rte_flow_item_tcp *flow_mask,
834 struct rte_flow_error *error);
835 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
837 uint8_t target_protocol,
838 struct rte_flow_error *error);
839 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
841 struct rte_eth_dev *dev,
842 struct rte_flow_error *error);
843 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
845 struct rte_flow_error *error);
846 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
848 struct rte_eth_dev *dev,
849 struct rte_flow_error *error);
850 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
852 uint8_t target_protocol,
853 struct rte_flow_error *error);
854 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
856 uint8_t target_protocol,
857 struct rte_flow_error *error);
858 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
860 uint8_t target_protocol,
861 struct rte_flow_error *error);
862 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
864 struct rte_eth_dev *dev,
865 struct rte_flow_error *error);
866 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
867 (struct rte_eth_dev *dev,
868 const struct mlx5_flow_meter *fm);
869 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
870 struct mlx5_meter_domains_infos *tbl);
871 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
872 struct mlx5_flow_meter *fm,
873 const struct rte_flow_attr *attr);
874 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
875 struct mlx5_flow_meter *fm,
876 const struct rte_flow_attr *attr);
877 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
878 struct rte_mtr_error *error);
879 #endif /* RTE_PMD_MLX5_FLOW_H_ */