1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
32 /* Private rte flow items. */
33 enum mlx5_rte_flow_item_type {
34 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
35 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
36 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
37 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
40 /* Private (internal) rte flow actions. */
41 enum mlx5_rte_flow_action_type {
42 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
43 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
44 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
45 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
48 /* Matches on selected register. */
49 struct mlx5_rte_flow_item_tag {
54 /* Modify selected register. */
55 struct mlx5_rte_flow_action_set_tag {
60 struct mlx5_flow_action_copy_mreg {
65 /* Matches on source queue. */
66 struct mlx5_rte_flow_item_tx_queue {
70 /* Feature name to allocate metadata register. */
71 enum mlx5_feature_name {
84 /* Pattern outer Layer bits. */
85 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
86 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
87 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
88 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
89 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
90 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
92 /* Pattern inner Layer bits. */
93 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
94 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
95 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
96 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
97 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
98 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
100 /* Pattern tunnel Layer bits. */
101 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
102 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
103 #define MLX5_FLOW_LAYER_GRE (1u << 14)
104 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
105 /* List of tunnel Layer bits continued below. */
107 /* General pattern items bits. */
108 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
109 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
110 #define MLX5_FLOW_ITEM_TAG (1u << 18)
111 #define MLX5_FLOW_ITEM_MARK (1u << 19)
113 /* Pattern MISC bits. */
114 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
115 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
116 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
118 /* Pattern tunnel Layer bits (continued). */
119 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
120 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
121 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
122 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
125 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
127 /* Pattern tunnel Layer bits (continued). */
128 #define MLX5_FLOW_LAYER_GTP (1u << 28)
131 #define MLX5_FLOW_LAYER_OUTER_L3 \
132 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
133 #define MLX5_FLOW_LAYER_OUTER_L4 \
134 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
135 #define MLX5_FLOW_LAYER_OUTER \
136 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
137 MLX5_FLOW_LAYER_OUTER_L4)
140 #define MLX5_FLOW_LAYER_TUNNEL \
141 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
142 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
143 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
144 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
147 #define MLX5_FLOW_LAYER_INNER_L3 \
148 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
149 #define MLX5_FLOW_LAYER_INNER_L4 \
150 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
151 #define MLX5_FLOW_LAYER_INNER \
152 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
153 MLX5_FLOW_LAYER_INNER_L4)
156 #define MLX5_FLOW_LAYER_L2 \
157 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
158 #define MLX5_FLOW_LAYER_L3_IPV4 \
159 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
160 #define MLX5_FLOW_LAYER_L3_IPV6 \
161 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
162 #define MLX5_FLOW_LAYER_L3 \
163 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
164 #define MLX5_FLOW_LAYER_L4 \
165 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
168 #define MLX5_FLOW_ACTION_DROP (1u << 0)
169 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
170 #define MLX5_FLOW_ACTION_RSS (1u << 2)
171 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
172 #define MLX5_FLOW_ACTION_MARK (1u << 4)
173 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
174 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
175 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
176 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
177 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
178 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
179 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
180 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
181 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
182 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
183 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
184 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
185 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
186 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
187 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
188 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
189 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
190 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
191 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
192 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
193 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
194 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
195 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
196 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
197 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
198 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
199 #define MLX5_FLOW_ACTION_METER (1ull << 31)
200 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
201 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
203 #define MLX5_FLOW_FATE_ACTIONS \
204 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
205 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
207 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
208 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
209 MLX5_FLOW_ACTION_JUMP)
212 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
213 MLX5_FLOW_ACTION_SET_IPV4_DST | \
214 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
215 MLX5_FLOW_ACTION_SET_IPV6_DST | \
216 MLX5_FLOW_ACTION_SET_TP_SRC | \
217 MLX5_FLOW_ACTION_SET_TP_DST | \
218 MLX5_FLOW_ACTION_SET_TTL | \
219 MLX5_FLOW_ACTION_DEC_TTL | \
220 MLX5_FLOW_ACTION_SET_MAC_SRC | \
221 MLX5_FLOW_ACTION_SET_MAC_DST | \
222 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
223 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
224 MLX5_FLOW_ACTION_INC_TCP_ACK | \
225 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
226 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
227 MLX5_FLOW_ACTION_SET_TAG | \
228 MLX5_FLOW_ACTION_MARK_EXT | \
229 MLX5_FLOW_ACTION_SET_META | \
230 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
231 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
233 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
234 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
236 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
239 #define IPPROTO_MPLS 137
242 /* UDP port number for MPLS */
243 #define MLX5_UDP_PORT_MPLS 6635
245 /* UDP port numbers for VxLAN. */
246 #define MLX5_UDP_PORT_VXLAN 4789
247 #define MLX5_UDP_PORT_VXLAN_GPE 4790
249 /* UDP port numbers for GENEVE. */
250 #define MLX5_UDP_PORT_GENEVE 6081
252 /* Priority reserved for default flows. */
253 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
256 * Number of sub priorities.
257 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
258 * matching on the NIC (firmware dependent) L4 most have the higher priority
259 * followed by L3 and ending with L2.
261 #define MLX5_PRIORITY_MAP_L2 2
262 #define MLX5_PRIORITY_MAP_L3 1
263 #define MLX5_PRIORITY_MAP_L4 0
264 #define MLX5_PRIORITY_MAP_MAX 3
266 /* Valid layer type for IPV4 RSS. */
267 #define MLX5_IPV4_LAYER_TYPES \
268 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
269 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
270 ETH_RSS_NONFRAG_IPV4_OTHER)
272 /* IBV hash source bits for IPV4. */
273 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
275 /* Valid layer type for IPV6 RSS. */
276 #define MLX5_IPV6_LAYER_TYPES \
277 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
278 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
279 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
281 /* IBV hash source bits for IPV6. */
282 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
284 /* IBV hash bits for L3 SRC. */
285 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
287 /* IBV hash bits for L3 DST. */
288 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
290 /* IBV hash bits for TCP. */
291 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
292 IBV_RX_HASH_DST_PORT_TCP)
294 /* IBV hash bits for UDP. */
295 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
296 IBV_RX_HASH_DST_PORT_UDP)
298 /* IBV hash bits for L4 SRC. */
299 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
300 IBV_RX_HASH_SRC_PORT_UDP)
302 /* IBV hash bits for L4 DST. */
303 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
304 IBV_RX_HASH_DST_PORT_UDP)
306 /* Geneve header first 16Bit */
307 #define MLX5_GENEVE_VER_MASK 0x3
308 #define MLX5_GENEVE_VER_SHIFT 14
309 #define MLX5_GENEVE_VER_VAL(a) \
310 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
311 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
312 #define MLX5_GENEVE_OPTLEN_SHIFT 7
313 #define MLX5_GENEVE_OPTLEN_VAL(a) \
314 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
315 #define MLX5_GENEVE_OAMF_MASK 0x1
316 #define MLX5_GENEVE_OAMF_SHIFT 7
317 #define MLX5_GENEVE_OAMF_VAL(a) \
318 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
319 #define MLX5_GENEVE_CRITO_MASK 0x1
320 #define MLX5_GENEVE_CRITO_SHIFT 6
321 #define MLX5_GENEVE_CRITO_VAL(a) \
322 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
323 #define MLX5_GENEVE_RSVD_MASK 0x3F
324 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
326 * The length of the Geneve options fields, expressed in four byte multiples,
327 * not including the eight byte fixed tunnel.
329 #define MLX5_GENEVE_OPT_LEN_0 14
330 #define MLX5_GENEVE_OPT_LEN_1 63
332 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
333 sizeof(struct rte_flow_item_ipv4))
335 enum mlx5_flow_drv_type {
338 MLX5_FLOW_TYPE_VERBS,
342 /* Fate action type. */
343 enum mlx5_flow_fate_type {
344 MLX5_FLOW_FATE_NONE, /* Egress flow. */
345 MLX5_FLOW_FATE_QUEUE,
347 MLX5_FLOW_FATE_PORT_ID,
352 /* Matcher PRM representation */
353 struct mlx5_flow_dv_match_params {
355 /**< Size of match value. Do NOT split size and key! */
356 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
357 /**< Matcher value. This value is used as the mask or as a key. */
360 /* Matcher structure. */
361 struct mlx5_flow_dv_matcher {
362 LIST_ENTRY(mlx5_flow_dv_matcher) next;
363 /**< Pointer to the next element. */
364 struct mlx5_flow_tbl_resource *tbl;
365 /**< Pointer to the table(group) the matcher associated with. */
366 rte_atomic32_t refcnt; /**< Reference counter. */
367 void *matcher_object; /**< Pointer to DV matcher */
368 uint16_t crc; /**< CRC of key. */
369 uint16_t priority; /**< Priority of matcher. */
370 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
373 #define MLX5_ENCAP_MAX_LEN 132
375 /* Encap/decap resource structure. */
376 struct mlx5_flow_dv_encap_decap_resource {
377 ILIST_ENTRY(uint32_t)next;
378 /* Pointer to next element. */
379 rte_atomic32_t refcnt; /**< Reference counter. */
381 /**< Verbs encap/decap action object. */
382 uint8_t buf[MLX5_ENCAP_MAX_LEN];
384 uint8_t reformat_type;
386 uint64_t flags; /**< Flags for RDMA API. */
389 /* Tag resource structure. */
390 struct mlx5_flow_dv_tag_resource {
391 struct mlx5_hlist_entry entry;
392 /**< hash list entry for tag resource, tag value as the key. */
394 /**< Verbs tag action object. */
395 rte_atomic32_t refcnt; /**< Reference counter. */
396 uint32_t idx; /**< Index for the index memory pool. */
400 * Number of modification commands.
401 * If extensive metadata registers are supported, the maximal actions amount is
402 * 16 and 8 otherwise on root table. The validation could also be done in the
403 * lower driver layer.
404 * On non-root table, there is no limitation, but 32 is enough right now.
406 #define MLX5_MAX_MODIFY_NUM 32
407 #define MLX5_ROOT_TBL_MODIFY_NUM 16
408 #define MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG 8
410 /* Modify resource structure */
411 struct mlx5_flow_dv_modify_hdr_resource {
412 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
413 /* Pointer to next element. */
414 rte_atomic32_t refcnt; /**< Reference counter. */
415 struct ibv_flow_action *verbs_action;
416 /**< Verbs modify header action object. */
417 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
418 uint32_t actions_num; /**< Number of modification actions. */
419 uint64_t flags; /**< Flags for RDMA API. */
420 struct mlx5_modification_cmd actions[];
421 /**< Modification actions. */
424 /* Jump action resource structure. */
425 struct mlx5_flow_dv_jump_tbl_resource {
426 rte_atomic32_t refcnt; /**< Reference counter. */
427 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
428 void *action; /**< Pointer to the rdma core action. */
431 /* Port ID resource structure. */
432 struct mlx5_flow_dv_port_id_action_resource {
433 ILIST_ENTRY(uint32_t)next;
434 /* Pointer to next element. */
435 rte_atomic32_t refcnt; /**< Reference counter. */
437 /**< Verbs tag action object. */
438 uint32_t port_id; /**< Port ID value. */
441 /* Push VLAN action resource structure */
442 struct mlx5_flow_dv_push_vlan_action_resource {
443 ILIST_ENTRY(uint32_t)next;
444 /* Pointer to next element. */
445 rte_atomic32_t refcnt; /**< Reference counter. */
446 void *action; /**< Direct verbs action object. */
447 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
448 rte_be32_t vlan_tag; /**< VLAN tag value. */
451 /* Metadata register copy table entry. */
452 struct mlx5_flow_mreg_copy_resource {
454 * Hash list entry for copy table.
455 * - Key is 32/64-bit MARK action ID.
456 * - MUST be the first entry.
458 struct mlx5_hlist_entry hlist_ent;
459 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
460 /* List entry for device flows. */
461 uint32_t refcnt; /* Reference counter. */
462 uint32_t appcnt; /* Apply/Remove counter. */
464 uint32_t rix_flow; /* Built flow for copy. */
467 /* Table data structure of the hash organization. */
468 struct mlx5_flow_tbl_data_entry {
469 struct mlx5_hlist_entry entry;
470 /**< hash list entry, 64-bits key inside. */
471 struct mlx5_flow_tbl_resource tbl;
472 /**< flow table resource. */
473 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
474 /**< matchers' header associated with the flow table. */
475 struct mlx5_flow_dv_jump_tbl_resource jump;
476 /**< jump resource, at most one for each table created. */
477 uint32_t idx; /**< index for the indexed mempool. */
480 /* Verbs specification header. */
481 struct ibv_spec_header {
482 enum ibv_flow_spec_type type;
486 /* RSS description. */
487 struct mlx5_flow_rss_desc {
489 uint32_t queue_num; /**< Number of entries in @p queue. */
490 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
491 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
492 uint16_t queue[]; /**< Destination queues to redirect traffic to. */
496 /** Device flow handle structure for DV mode only. */
497 struct mlx5_flow_handle_dv {
499 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
500 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
501 /**< Pointer to modify header resource in cache. */
502 uint32_t rix_encap_decap;
503 /**< Index to encap/decap resource in cache. */
504 uint32_t rix_push_vlan;
505 /**< Index to push VLAN action resource in cache. */
507 /**< Index to the tag action. */
510 /** Device flow handle structure: used both for creating & destroying. */
511 struct mlx5_flow_handle {
512 SILIST_ENTRY(uint32_t)next;
513 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
514 /**< Index to next device flow handle. */
516 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
517 void *ib_flow; /**< Verbs flow pointer. */
518 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
519 uint32_t mark:1; /**< Metadate rxq mark flag. */
520 uint32_t fate_action:3; /**< Fate action type. */
522 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
523 uint32_t rix_jump; /**< Index to the jump action resource. */
524 uint32_t rix_port_id_action;
525 /**< Index to port ID action resource. */
527 /**< Generic value indicates the fate action. */
529 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
530 struct mlx5_flow_handle_dv dvh;
535 * Size for Verbs device flow handle structure only. Do not use the DV only
536 * structure in Verbs. No DV flows attributes will be accessed.
537 * Macro offsetof() could also be used here.
539 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
540 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
541 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
543 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
547 * Max number of actions per DV flow.
548 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
549 * in rdma-core file providers/mlx5/verbs.c.
551 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
553 /** Device flow structure only for DV flow creation. */
554 struct mlx5_flow_dv_workspace {
555 uint32_t group; /**< The group index. */
556 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
557 int actions_n; /**< number of actions. */
558 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
559 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
560 /**< Pointer to encap/decap resource in cache. */
561 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
562 /**< Pointer to push VLAN action resource in cache. */
563 struct mlx5_flow_dv_tag_resource *tag_resource;
564 /**< pointer to the tag action. */
565 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
566 /**< Pointer to port ID action resource. */
567 struct mlx5_flow_dv_jump_tbl_resource *jump;
568 /**< Pointer to the jump action resource. */
569 struct mlx5_flow_dv_match_params value;
570 /**< Holds the value that the packet is compared to. */
574 * Maximal Verbs flow specifications & actions size.
575 * Some elements are mutually exclusive, but enough space should be allocated.
576 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
577 * 2. One tunnel header (exception: GRE + MPLS),
578 * SPEC length: GRE == tunnel.
579 * Actions: 1. 1 Mark OR Flag.
580 * 2. 1 Drop (if any).
581 * 3. No limitation for counters, but it makes no sense to support too
582 * many counters in a single device flow.
584 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
585 #define MLX5_VERBS_MAX_SPEC_SIZE \
587 (2 * (sizeof(struct ibv_flow_spec_eth) + \
588 sizeof(struct ibv_flow_spec_ipv6) + \
589 sizeof(struct ibv_flow_spec_tcp_udp)) + \
590 sizeof(struct ibv_flow_spec_gre) + \
591 sizeof(struct ibv_flow_spec_mpls)) \
594 #define MLX5_VERBS_MAX_SPEC_SIZE \
596 (2 * (sizeof(struct ibv_flow_spec_eth) + \
597 sizeof(struct ibv_flow_spec_ipv6) + \
598 sizeof(struct ibv_flow_spec_tcp_udp)) + \
599 sizeof(struct ibv_flow_spec_tunnel)) \
603 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
604 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
605 #define MLX5_VERBS_MAX_ACT_SIZE \
607 sizeof(struct ibv_flow_spec_action_tag) + \
608 sizeof(struct ibv_flow_spec_action_drop) + \
609 sizeof(struct ibv_flow_spec_counter_action) * 4 \
612 #define MLX5_VERBS_MAX_ACT_SIZE \
614 sizeof(struct ibv_flow_spec_action_tag) + \
615 sizeof(struct ibv_flow_spec_action_drop) \
619 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
620 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
622 /** Device flow structure only for Verbs flow creation. */
623 struct mlx5_flow_verbs_workspace {
624 unsigned int size; /**< Size of the attribute. */
625 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
626 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
627 /**< Specifications & actions buffer of verbs flow. */
630 /** Maximal number of device sub-flows supported. */
631 #define MLX5_NUM_MAX_DEV_FLOWS 32
633 /** Device flow structure. */
635 struct rte_flow *flow; /**< Pointer to the main flow. */
636 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
638 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
639 bool external; /**< true if the flow is created external to PMD. */
640 uint8_t ingress; /**< 1 if the flow is ingress. */
642 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
643 struct mlx5_flow_dv_workspace dv;
645 struct mlx5_flow_verbs_workspace verbs;
647 struct mlx5_flow_handle *handle;
648 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
651 /* Flow meter state. */
652 #define MLX5_FLOW_METER_DISABLE 0
653 #define MLX5_FLOW_METER_ENABLE 1
655 #define MLX5_MAN_WIDTH 8
656 /* Modify this value if enum rte_mtr_color changes. */
657 #define RTE_MTR_DROPPED RTE_COLORS
659 /* Meter policer statistics */
660 struct mlx5_flow_policer_stats {
661 uint32_t cnt[RTE_COLORS + 1];
662 /**< Color counter, extra for drop. */
664 /**< Statistics mask for the colors. */
667 /* Meter table structure. */
668 struct mlx5_meter_domain_info {
669 struct mlx5_flow_tbl_resource *tbl;
671 struct mlx5_flow_tbl_resource *sfx_tbl;
672 /**< Meter suffix table. */
674 /**< Meter color not match default criteria. */
676 /**< Meter color match criteria. */
678 /**< Meter match action. */
679 void *policer_rules[RTE_MTR_DROPPED + 1];
680 /**< Meter policer for the match. */
683 /* Meter table set for TX RX FDB. */
684 struct mlx5_meter_domains_infos {
686 /**< Table user count. */
687 struct mlx5_meter_domain_info egress;
688 /**< TX meter table. */
689 struct mlx5_meter_domain_info ingress;
690 /**< RX meter table. */
691 struct mlx5_meter_domain_info transfer;
692 /**< FDB meter table. */
694 /**< Drop action as not matched. */
695 void *count_actns[RTE_MTR_DROPPED + 1];
696 /**< Counters for match and unmatched statistics. */
697 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
698 /**< Flow meter parameter. */
700 /**< Flow meter parameter size. */
702 /**< Flow meter action. */
705 /* Meter parameter structure. */
706 struct mlx5_flow_meter {
707 TAILQ_ENTRY(mlx5_flow_meter) next;
708 /**< Pointer to the next flow meter structure. */
709 uint32_t idx; /* Index to meter object. */
712 struct rte_mtr_params params;
713 /**< Meter rule parameters. */
714 struct mlx5_flow_meter_profile *profile;
715 /**< Meter profile parameters. */
716 struct rte_flow_attr attr;
717 /**< Flow attributes. */
718 struct mlx5_meter_domains_infos *mfts;
719 /**< Flow table created for this meter. */
720 struct mlx5_flow_policer_stats policer_stats;
721 /**< Meter policer statistics. */
724 uint32_t active_state:1;
727 /**< Meter shared or not. */
730 /* RFC2697 parameter structure. */
731 struct mlx5_flow_meter_srtcm_rfc2697_prm {
732 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
733 uint32_t cbs_exponent:5;
734 uint32_t cbs_mantissa:8;
735 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
736 uint32_t cir_exponent:5;
737 uint32_t cir_mantissa:8;
738 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
739 uint32_t ebs_exponent:5;
740 uint32_t ebs_mantissa:8;
743 /* Flow meter profile structure. */
744 struct mlx5_flow_meter_profile {
745 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
746 /**< Pointer to the next flow meter structure. */
747 uint32_t meter_profile_id; /**< Profile id. */
748 struct rte_mtr_meter_profile profile; /**< Profile detail. */
750 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
751 /**< srtcm_rfc2697 struct. */
753 uint32_t ref_cnt; /**< Use count. */
756 /* Fdir flow structure */
757 struct mlx5_fdir_flow {
758 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */
759 struct mlx5_fdir *fdir; /* Pointer to fdir. */
760 uint32_t rix_flow; /* Index to flow. */
763 /* Flow structure. */
765 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
766 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
767 uint32_t counter; /**< Holds flow counter. */
768 uint32_t rix_mreg_copy;
769 /**< Index to metadata register copy table resource. */
770 uint16_t meter; /**< Holds flow meter id. */
771 uint32_t dev_handles;
772 /**< Device flow handles that are part of the flow. */
773 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */
774 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
775 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
778 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
779 const struct rte_flow_attr *attr,
780 const struct rte_flow_item items[],
781 const struct rte_flow_action actions[],
783 struct rte_flow_error *error);
784 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
785 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
786 const struct rte_flow_item items[],
787 const struct rte_flow_action actions[], struct rte_flow_error *error);
788 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
789 struct mlx5_flow *dev_flow,
790 const struct rte_flow_attr *attr,
791 const struct rte_flow_item items[],
792 const struct rte_flow_action actions[],
793 struct rte_flow_error *error);
794 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
795 struct rte_flow_error *error);
796 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
797 struct rte_flow *flow);
798 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
799 struct rte_flow *flow);
800 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
801 struct rte_flow *flow,
802 const struct rte_flow_action *actions,
804 struct rte_flow_error *error);
805 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
806 (struct rte_eth_dev *dev,
807 const struct mlx5_flow_meter *fm);
808 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
809 struct mlx5_meter_domains_infos *tbls);
810 typedef int (*mlx5_flow_create_policer_rules_t)
811 (struct rte_eth_dev *dev,
812 struct mlx5_flow_meter *fm,
813 const struct rte_flow_attr *attr);
814 typedef int (*mlx5_flow_destroy_policer_rules_t)
815 (struct rte_eth_dev *dev,
816 const struct mlx5_flow_meter *fm,
817 const struct rte_flow_attr *attr);
818 typedef uint32_t (*mlx5_flow_counter_alloc_t)
819 (struct rte_eth_dev *dev);
820 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
822 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
824 bool clear, uint64_t *pkts,
826 struct mlx5_flow_driver_ops {
827 mlx5_flow_validate_t validate;
828 mlx5_flow_prepare_t prepare;
829 mlx5_flow_translate_t translate;
830 mlx5_flow_apply_t apply;
831 mlx5_flow_remove_t remove;
832 mlx5_flow_destroy_t destroy;
833 mlx5_flow_query_t query;
834 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
835 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
836 mlx5_flow_create_policer_rules_t create_policer_rules;
837 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
838 mlx5_flow_counter_alloc_t counter_alloc;
839 mlx5_flow_counter_free_t counter_free;
840 mlx5_flow_counter_query_t counter_query;
844 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
845 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
846 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
847 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
851 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id);
852 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
853 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
854 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
856 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
857 bool external, uint32_t group, bool fdb_def_rule,
858 uint32_t *table, struct rte_flow_error *error);
859 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
860 int tunnel, uint64_t layer_types,
861 uint64_t hash_fields);
862 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
863 uint32_t subpriority);
864 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
865 enum mlx5_feature_name feature,
867 struct rte_flow_error *error);
868 const struct rte_flow_action *mlx5_flow_find_action
869 (const struct rte_flow_action *actions,
870 enum rte_flow_action_type action);
871 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
872 const struct rte_flow_attr *attr,
873 struct rte_flow_error *error);
874 int mlx5_flow_validate_action_drop(uint64_t action_flags,
875 const struct rte_flow_attr *attr,
876 struct rte_flow_error *error);
877 int mlx5_flow_validate_action_flag(uint64_t action_flags,
878 const struct rte_flow_attr *attr,
879 struct rte_flow_error *error);
880 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
881 uint64_t action_flags,
882 const struct rte_flow_attr *attr,
883 struct rte_flow_error *error);
884 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
885 uint64_t action_flags,
886 struct rte_eth_dev *dev,
887 const struct rte_flow_attr *attr,
888 struct rte_flow_error *error);
889 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
890 uint64_t action_flags,
891 struct rte_eth_dev *dev,
892 const struct rte_flow_attr *attr,
894 struct rte_flow_error *error);
895 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
896 const struct rte_flow_attr *attributes,
897 struct rte_flow_error *error);
898 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
900 const uint8_t *nic_mask,
902 struct rte_flow_error *error);
903 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
905 struct rte_flow_error *error);
906 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
908 uint8_t target_protocol,
909 struct rte_flow_error *error);
910 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
912 const struct rte_flow_item *gre_item,
913 struct rte_flow_error *error);
914 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
918 const struct rte_flow_item_ipv4 *acc_mask,
919 struct rte_flow_error *error);
920 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
924 const struct rte_flow_item_ipv6 *acc_mask,
925 struct rte_flow_error *error);
926 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
927 const struct rte_flow_item *item,
930 struct rte_flow_error *error);
931 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
933 uint8_t target_protocol,
934 const struct rte_flow_item_tcp *flow_mask,
935 struct rte_flow_error *error);
936 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
938 uint8_t target_protocol,
939 struct rte_flow_error *error);
940 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
942 struct rte_eth_dev *dev,
943 struct rte_flow_error *error);
944 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
946 struct rte_flow_error *error);
947 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
949 struct rte_eth_dev *dev,
950 struct rte_flow_error *error);
951 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
953 uint8_t target_protocol,
954 struct rte_flow_error *error);
955 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
957 uint8_t target_protocol,
958 struct rte_flow_error *error);
959 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
961 uint8_t target_protocol,
962 struct rte_flow_error *error);
963 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
965 struct rte_eth_dev *dev,
966 struct rte_flow_error *error);
967 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
968 (struct rte_eth_dev *dev,
969 const struct mlx5_flow_meter *fm);
970 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
971 struct mlx5_meter_domains_infos *tbl);
972 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
973 struct mlx5_flow_meter *fm,
974 const struct rte_flow_attr *attr);
975 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
976 struct mlx5_flow_meter *fm,
977 const struct rte_flow_attr *attr);
978 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
979 struct rte_mtr_error *error);
980 #endif /* RTE_PMD_MLX5_FLOW_H_ */