1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_atomic.h>
15 #include <rte_alarm.h>
18 #include <mlx5_glue.h>
23 /* Private rte flow items. */
24 enum mlx5_rte_flow_item_type {
25 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
26 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
27 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
28 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
38 MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS,
41 /* Matches on selected register. */
42 struct mlx5_rte_flow_item_tag {
47 /* Modify selected register. */
48 struct mlx5_rte_flow_action_set_tag {
53 struct mlx5_flow_action_copy_mreg {
58 /* Matches on source queue. */
59 struct mlx5_rte_flow_item_tx_queue {
63 /* Feature name to allocate metadata register. */
64 enum mlx5_feature_name {
77 /* Pattern outer Layer bits. */
78 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
79 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
80 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
81 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
82 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
83 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
85 /* Pattern inner Layer bits. */
86 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
87 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
88 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
89 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
90 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
91 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
93 /* Pattern tunnel Layer bits. */
94 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
95 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
96 #define MLX5_FLOW_LAYER_GRE (1u << 14)
97 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
98 /* List of tunnel Layer bits continued below. */
100 /* General pattern items bits. */
101 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
102 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
103 #define MLX5_FLOW_ITEM_TAG (1u << 18)
104 #define MLX5_FLOW_ITEM_MARK (1u << 19)
106 /* Pattern MISC bits. */
107 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
108 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
109 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
111 /* Pattern tunnel Layer bits (continued). */
112 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
113 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
114 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
115 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
118 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
120 /* Pattern tunnel Layer bits (continued). */
121 #define MLX5_FLOW_LAYER_GTP (1u << 28)
123 /* Pattern eCPRI Layer bit. */
124 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
126 /* IPv6 Fragment Extension Header bit. */
127 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
128 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
131 #define MLX5_FLOW_LAYER_OUTER_L3 \
132 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
133 #define MLX5_FLOW_LAYER_OUTER_L4 \
134 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
135 #define MLX5_FLOW_LAYER_OUTER \
136 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
137 MLX5_FLOW_LAYER_OUTER_L4)
140 #define MLX5_FLOW_LAYER_TUNNEL \
141 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
142 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
143 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
144 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
147 #define MLX5_FLOW_LAYER_INNER_L3 \
148 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
149 #define MLX5_FLOW_LAYER_INNER_L4 \
150 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
151 #define MLX5_FLOW_LAYER_INNER \
152 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
153 MLX5_FLOW_LAYER_INNER_L4)
156 #define MLX5_FLOW_LAYER_L2 \
157 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
158 #define MLX5_FLOW_LAYER_L3_IPV4 \
159 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
160 #define MLX5_FLOW_LAYER_L3_IPV6 \
161 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
162 #define MLX5_FLOW_LAYER_L3 \
163 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
164 #define MLX5_FLOW_LAYER_L4 \
165 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
168 #define MLX5_FLOW_ACTION_DROP (1u << 0)
169 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
170 #define MLX5_FLOW_ACTION_RSS (1u << 2)
171 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
172 #define MLX5_FLOW_ACTION_MARK (1u << 4)
173 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
174 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
175 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
176 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
177 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
178 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
179 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
180 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
181 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
182 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
183 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
184 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
185 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
186 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
187 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
188 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
189 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
190 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
191 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
192 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
193 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
194 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
195 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
196 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
197 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
198 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
199 #define MLX5_FLOW_ACTION_METER (1ull << 31)
200 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
201 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
202 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
203 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
204 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
206 #define MLX5_FLOW_FATE_ACTIONS \
207 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
208 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
209 MLX5_FLOW_ACTION_DEFAULT_MISS)
211 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
212 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
213 MLX5_FLOW_ACTION_JUMP)
216 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
217 MLX5_FLOW_ACTION_SET_IPV4_DST | \
218 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
219 MLX5_FLOW_ACTION_SET_IPV6_DST | \
220 MLX5_FLOW_ACTION_SET_TP_SRC | \
221 MLX5_FLOW_ACTION_SET_TP_DST | \
222 MLX5_FLOW_ACTION_SET_TTL | \
223 MLX5_FLOW_ACTION_DEC_TTL | \
224 MLX5_FLOW_ACTION_SET_MAC_SRC | \
225 MLX5_FLOW_ACTION_SET_MAC_DST | \
226 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
227 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
228 MLX5_FLOW_ACTION_INC_TCP_ACK | \
229 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
230 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
231 MLX5_FLOW_ACTION_SET_TAG | \
232 MLX5_FLOW_ACTION_MARK_EXT | \
233 MLX5_FLOW_ACTION_SET_META | \
234 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
235 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
237 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
238 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
240 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
243 #define IPPROTO_MPLS 137
246 /* UDP port number for MPLS */
247 #define MLX5_UDP_PORT_MPLS 6635
249 /* UDP port numbers for VxLAN. */
250 #define MLX5_UDP_PORT_VXLAN 4789
251 #define MLX5_UDP_PORT_VXLAN_GPE 4790
253 /* UDP port numbers for GENEVE. */
254 #define MLX5_UDP_PORT_GENEVE 6081
256 /* Priority reserved for default flows. */
257 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
260 * Number of sub priorities.
261 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
262 * matching on the NIC (firmware dependent) L4 most have the higher priority
263 * followed by L3 and ending with L2.
265 #define MLX5_PRIORITY_MAP_L2 2
266 #define MLX5_PRIORITY_MAP_L3 1
267 #define MLX5_PRIORITY_MAP_L4 0
268 #define MLX5_PRIORITY_MAP_MAX 3
270 /* Valid layer type for IPV4 RSS. */
271 #define MLX5_IPV4_LAYER_TYPES \
272 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
273 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
274 ETH_RSS_NONFRAG_IPV4_OTHER)
276 /* IBV hash source bits for IPV4. */
277 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
279 /* Valid layer type for IPV6 RSS. */
280 #define MLX5_IPV6_LAYER_TYPES \
281 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
282 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
283 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
285 /* IBV hash source bits for IPV6. */
286 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
288 /* IBV hash bits for L3 SRC. */
289 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
291 /* IBV hash bits for L3 DST. */
292 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
294 /* IBV hash bits for TCP. */
295 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
296 IBV_RX_HASH_DST_PORT_TCP)
298 /* IBV hash bits for UDP. */
299 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
300 IBV_RX_HASH_DST_PORT_UDP)
302 /* IBV hash bits for L4 SRC. */
303 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
304 IBV_RX_HASH_SRC_PORT_UDP)
306 /* IBV hash bits for L4 DST. */
307 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
308 IBV_RX_HASH_DST_PORT_UDP)
310 /* Geneve header first 16Bit */
311 #define MLX5_GENEVE_VER_MASK 0x3
312 #define MLX5_GENEVE_VER_SHIFT 14
313 #define MLX5_GENEVE_VER_VAL(a) \
314 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
315 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
316 #define MLX5_GENEVE_OPTLEN_SHIFT 7
317 #define MLX5_GENEVE_OPTLEN_VAL(a) \
318 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
319 #define MLX5_GENEVE_OAMF_MASK 0x1
320 #define MLX5_GENEVE_OAMF_SHIFT 7
321 #define MLX5_GENEVE_OAMF_VAL(a) \
322 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
323 #define MLX5_GENEVE_CRITO_MASK 0x1
324 #define MLX5_GENEVE_CRITO_SHIFT 6
325 #define MLX5_GENEVE_CRITO_VAL(a) \
326 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
327 #define MLX5_GENEVE_RSVD_MASK 0x3F
328 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
330 * The length of the Geneve options fields, expressed in four byte multiples,
331 * not including the eight byte fixed tunnel.
333 #define MLX5_GENEVE_OPT_LEN_0 14
334 #define MLX5_GENEVE_OPT_LEN_1 63
336 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
337 sizeof(struct rte_flow_item_ipv4))
339 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
340 #define MLX5_IPV4_FRAG_OFFSET_MASK \
341 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
343 /* Specific item's fields can accept a range of values (using spec and last). */
344 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
345 #define MLX5_ITEM_RANGE_ACCEPTED true
347 /* Software header modify action numbers of a flow. */
348 #define MLX5_ACT_NUM_MDF_IPV4 1
349 #define MLX5_ACT_NUM_MDF_IPV6 4
350 #define MLX5_ACT_NUM_MDF_MAC 2
351 #define MLX5_ACT_NUM_MDF_VID 1
352 #define MLX5_ACT_NUM_MDF_PORT 2
353 #define MLX5_ACT_NUM_MDF_TTL 1
354 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
355 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
356 #define MLX5_ACT_NUM_MDF_TCPACK 1
357 #define MLX5_ACT_NUM_SET_REG 1
358 #define MLX5_ACT_NUM_SET_TAG 1
359 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
360 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
361 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
362 #define MLX5_ACT_NUM_SET_DSCP 1
364 enum mlx5_flow_drv_type {
367 MLX5_FLOW_TYPE_VERBS,
371 /* Fate action type. */
372 enum mlx5_flow_fate_type {
373 MLX5_FLOW_FATE_NONE, /* Egress flow. */
374 MLX5_FLOW_FATE_QUEUE,
376 MLX5_FLOW_FATE_PORT_ID,
378 MLX5_FLOW_FATE_DEFAULT_MISS,
382 /* Matcher PRM representation */
383 struct mlx5_flow_dv_match_params {
385 /**< Size of match value. Do NOT split size and key! */
386 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
387 /**< Matcher value. This value is used as the mask or as a key. */
390 /* Matcher structure. */
391 struct mlx5_flow_dv_matcher {
392 LIST_ENTRY(mlx5_flow_dv_matcher) next;
393 /**< Pointer to the next element. */
394 struct mlx5_flow_tbl_resource *tbl;
395 /**< Pointer to the table(group) the matcher associated with. */
396 rte_atomic32_t refcnt; /**< Reference counter. */
397 void *matcher_object; /**< Pointer to DV matcher */
398 uint16_t crc; /**< CRC of key. */
399 uint16_t priority; /**< Priority of matcher. */
400 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
403 #define MLX5_ENCAP_MAX_LEN 132
405 /* Encap/decap resource key of the hash organization. */
406 union mlx5_flow_encap_decap_key {
408 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
409 uint32_t refmt_type:8; /**< Header reformat type. */
410 uint32_t buf_size:8; /**< Encap buf size. */
411 uint32_t table_level:8; /**< Root table or not. */
412 uint32_t cksum; /**< Encap buf check sum. */
414 uint64_t v64; /**< full 64bits value of key */
417 /* Encap/decap resource structure. */
418 struct mlx5_flow_dv_encap_decap_resource {
419 struct mlx5_hlist_entry entry;
420 /* Pointer to next element. */
421 rte_atomic32_t refcnt; /**< Reference counter. */
423 /**< Encap/decap action object. */
424 uint8_t buf[MLX5_ENCAP_MAX_LEN];
426 uint8_t reformat_type;
428 uint64_t flags; /**< Flags for RDMA API. */
429 uint32_t idx; /**< Index for the index memory pool. */
432 /* Tag resource structure. */
433 struct mlx5_flow_dv_tag_resource {
434 struct mlx5_hlist_entry entry;
435 /**< hash list entry for tag resource, tag value as the key. */
437 /**< Tag action object. */
438 rte_atomic32_t refcnt; /**< Reference counter. */
439 uint32_t idx; /**< Index for the index memory pool. */
443 * Number of modification commands.
444 * The maximal actions amount in FW is some constant, and it is 16 in the
445 * latest releases. In some old releases, it will be limited to 8.
446 * Since there is no interface to query the capacity, the maximal value should
447 * be used to allow PMD to create the flow. The validation will be done in the
448 * lower driver layer or FW. A failure will be returned if exceeds the maximal
449 * supported actions number on the root table.
450 * On non-root tables, there is no limitation, but 32 is enough right now.
452 #define MLX5_MAX_MODIFY_NUM 32
453 #define MLX5_ROOT_TBL_MODIFY_NUM 16
455 /* Modify resource structure */
456 struct mlx5_flow_dv_modify_hdr_resource {
457 struct mlx5_hlist_entry entry;
458 /* Pointer to next element. */
459 rte_atomic32_t refcnt; /**< Reference counter. */
461 /**< Modify header action object. */
462 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
463 uint32_t actions_num; /**< Number of modification actions. */
464 uint64_t flags; /**< Flags for RDMA API. */
465 struct mlx5_modification_cmd actions[];
466 /**< Modification actions. */
469 /* Modify resource key of the hash organization. */
470 union mlx5_flow_modify_hdr_key {
472 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
473 uint32_t actions_num:5; /**< Number of modification actions. */
474 uint32_t group:19; /**< Flow group id. */
475 uint32_t cksum; /**< Actions check sum. */
477 uint64_t v64; /**< full 64bits value of key */
480 /* Jump action resource structure. */
481 struct mlx5_flow_dv_jump_tbl_resource {
482 rte_atomic32_t refcnt; /**< Reference counter. */
483 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
484 void *action; /**< Pointer to the rdma core action. */
487 /* Port ID resource structure. */
488 struct mlx5_flow_dv_port_id_action_resource {
489 ILIST_ENTRY(uint32_t)next;
490 /* Pointer to next element. */
491 rte_atomic32_t refcnt; /**< Reference counter. */
493 /**< Action object. */
494 uint32_t port_id; /**< Port ID value. */
497 /* Push VLAN action resource structure */
498 struct mlx5_flow_dv_push_vlan_action_resource {
499 ILIST_ENTRY(uint32_t)next;
500 /* Pointer to next element. */
501 rte_atomic32_t refcnt; /**< Reference counter. */
502 void *action; /**< Action object. */
503 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
504 rte_be32_t vlan_tag; /**< VLAN tag value. */
507 /* Metadata register copy table entry. */
508 struct mlx5_flow_mreg_copy_resource {
510 * Hash list entry for copy table.
511 * - Key is 32/64-bit MARK action ID.
512 * - MUST be the first entry.
514 struct mlx5_hlist_entry hlist_ent;
515 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
516 /* List entry for device flows. */
517 uint32_t refcnt; /* Reference counter. */
518 uint32_t appcnt; /* Apply/Remove counter. */
520 uint32_t rix_flow; /* Built flow for copy. */
523 /* Table data structure of the hash organization. */
524 struct mlx5_flow_tbl_data_entry {
525 struct mlx5_hlist_entry entry;
526 /**< hash list entry, 64-bits key inside. */
527 struct mlx5_flow_tbl_resource tbl;
528 /**< flow table resource. */
529 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
530 /**< matchers' header associated with the flow table. */
531 struct mlx5_flow_dv_jump_tbl_resource jump;
532 /**< jump resource, at most one for each table created. */
533 uint32_t idx; /**< index for the indexed mempool. */
536 /* Sub rdma-core actions list. */
537 struct mlx5_flow_sub_actions_list {
538 uint32_t actions_num; /**< Number of sample actions. */
539 uint64_t action_flags;
540 void *dr_queue_action;
543 void *dr_port_id_action;
544 void *dr_encap_action;
547 /* Sample sub-actions resource list. */
548 struct mlx5_flow_sub_actions_idx {
549 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
550 uint32_t rix_tag; /**< Index to the tag action. */
552 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
553 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
556 /* Sample action resource structure. */
557 struct mlx5_flow_dv_sample_resource {
558 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
559 uint32_t refcnt; /**< Reference counter. */
560 void *verbs_action; /**< Verbs sample action object. */
561 uint8_t ft_type; /** Flow Table Type */
562 uint32_t ft_id; /** Flow Table Level */
563 uint32_t ratio; /** Sample Ratio */
564 uint64_t set_action; /** Restore reg_c0 value */
565 void *normal_path_tbl; /** Flow Table pointer */
566 void *default_miss; /** default_miss dr_action. */
567 struct mlx5_flow_sub_actions_idx sample_idx;
568 /**< Action index resources. */
569 struct mlx5_flow_sub_actions_list sample_act;
570 /**< Action resources. */
573 #define MLX5_MAX_DEST_NUM 2
575 /* Destination array action resource structure. */
576 struct mlx5_flow_dv_dest_array_resource {
577 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
578 uint32_t refcnt; /**< Reference counter. */
579 uint8_t ft_type; /** Flow Table Type */
580 uint8_t num_of_dest; /**< Number of destination actions. */
581 void *action; /**< Pointer to the rdma core action. */
582 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
583 /**< Action index resources. */
584 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
585 /**< Action resources. */
588 /* Verbs specification header. */
589 struct ibv_spec_header {
590 enum ibv_flow_spec_type type;
594 /* RSS description. */
595 struct mlx5_flow_rss_desc {
597 uint32_t queue_num; /**< Number of entries in @p queue. */
598 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
599 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
600 uint16_t queue[]; /**< Destination queues to redirect traffic to. */
603 /* PMD flow priority for tunnel */
604 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
605 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
608 /** Device flow handle structure for DV mode only. */
609 struct mlx5_flow_handle_dv {
611 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
612 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
613 /**< Pointer to modify header resource in cache. */
614 uint32_t rix_encap_decap;
615 /**< Index to encap/decap resource in cache. */
616 uint32_t rix_push_vlan;
617 /**< Index to push VLAN action resource in cache. */
619 /**< Index to the tag action. */
621 /**< Index to sample action resource in cache. */
622 uint32_t rix_dest_array;
623 /**< Index to destination array resource in cache. */
626 /** Device flow handle structure: used both for creating & destroying. */
627 struct mlx5_flow_handle {
628 SILIST_ENTRY(uint32_t)next;
629 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
630 /**< Index to next device flow handle. */
632 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
633 void *drv_flow; /**< pointer to driver flow object. */
634 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
635 uint32_t mark:1; /**< Metadate rxq mark flag. */
636 uint32_t fate_action:3; /**< Fate action type. */
638 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
639 uint32_t rix_jump; /**< Index to the jump action resource. */
640 uint32_t rix_port_id_action;
641 /**< Index to port ID action resource. */
643 /**< Generic value indicates the fate action. */
644 uint32_t rix_default_fate;
645 /**< Indicates default miss fate action. */
647 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
648 struct mlx5_flow_handle_dv dvh;
653 * Size for Verbs device flow handle structure only. Do not use the DV only
654 * structure in Verbs. No DV flows attributes will be accessed.
655 * Macro offsetof() could also be used here.
657 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
658 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
659 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
661 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
665 * Max number of actions per DV flow.
666 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
667 * in rdma-core file providers/mlx5/verbs.c.
669 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
671 /** Device flow structure only for DV flow creation. */
672 struct mlx5_flow_dv_workspace {
673 uint32_t group; /**< The group index. */
674 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
675 int actions_n; /**< number of actions. */
676 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
677 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
678 /**< Pointer to encap/decap resource in cache. */
679 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
680 /**< Pointer to push VLAN action resource in cache. */
681 struct mlx5_flow_dv_tag_resource *tag_resource;
682 /**< pointer to the tag action. */
683 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
684 /**< Pointer to port ID action resource. */
685 struct mlx5_flow_dv_jump_tbl_resource *jump;
686 /**< Pointer to the jump action resource. */
687 struct mlx5_flow_dv_match_params value;
688 /**< Holds the value that the packet is compared to. */
689 struct mlx5_flow_dv_sample_resource *sample_res;
690 /**< Pointer to the sample action resource. */
691 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
692 /**< Pointer to the destination array resource. */
696 * Maximal Verbs flow specifications & actions size.
697 * Some elements are mutually exclusive, but enough space should be allocated.
698 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
699 * 2. One tunnel header (exception: GRE + MPLS),
700 * SPEC length: GRE == tunnel.
701 * Actions: 1. 1 Mark OR Flag.
702 * 2. 1 Drop (if any).
703 * 3. No limitation for counters, but it makes no sense to support too
704 * many counters in a single device flow.
706 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
707 #define MLX5_VERBS_MAX_SPEC_SIZE \
709 (2 * (sizeof(struct ibv_flow_spec_eth) + \
710 sizeof(struct ibv_flow_spec_ipv6) + \
711 sizeof(struct ibv_flow_spec_tcp_udp)) + \
712 sizeof(struct ibv_flow_spec_gre) + \
713 sizeof(struct ibv_flow_spec_mpls)) \
716 #define MLX5_VERBS_MAX_SPEC_SIZE \
718 (2 * (sizeof(struct ibv_flow_spec_eth) + \
719 sizeof(struct ibv_flow_spec_ipv6) + \
720 sizeof(struct ibv_flow_spec_tcp_udp)) + \
721 sizeof(struct ibv_flow_spec_tunnel)) \
725 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
726 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
727 #define MLX5_VERBS_MAX_ACT_SIZE \
729 sizeof(struct ibv_flow_spec_action_tag) + \
730 sizeof(struct ibv_flow_spec_action_drop) + \
731 sizeof(struct ibv_flow_spec_counter_action) * 4 \
734 #define MLX5_VERBS_MAX_ACT_SIZE \
736 sizeof(struct ibv_flow_spec_action_tag) + \
737 sizeof(struct ibv_flow_spec_action_drop) \
741 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
742 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
744 /** Device flow structure only for Verbs flow creation. */
745 struct mlx5_flow_verbs_workspace {
746 unsigned int size; /**< Size of the attribute. */
747 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
748 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
749 /**< Specifications & actions buffer of verbs flow. */
752 /** Maximal number of device sub-flows supported. */
753 #define MLX5_NUM_MAX_DEV_FLOWS 32
755 /** Device flow structure. */
757 struct rte_flow *flow; /**< Pointer to the main flow. */
758 uint32_t flow_idx; /**< The memory pool index to the main flow. */
759 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
761 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
762 bool external; /**< true if the flow is created external to PMD. */
763 uint8_t ingress; /**< 1 if the flow is ingress. */
765 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
766 struct mlx5_flow_dv_workspace dv;
768 struct mlx5_flow_verbs_workspace verbs;
770 struct mlx5_flow_handle *handle;
771 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
774 /* Flow meter state. */
775 #define MLX5_FLOW_METER_DISABLE 0
776 #define MLX5_FLOW_METER_ENABLE 1
778 #define MLX5_MAN_WIDTH 8
779 /* Modify this value if enum rte_mtr_color changes. */
780 #define RTE_MTR_DROPPED RTE_COLORS
782 /* Meter policer statistics */
783 struct mlx5_flow_policer_stats {
784 uint32_t cnt[RTE_COLORS + 1];
785 /**< Color counter, extra for drop. */
787 /**< Statistics mask for the colors. */
790 /* Meter table structure. */
791 struct mlx5_meter_domain_info {
792 struct mlx5_flow_tbl_resource *tbl;
794 struct mlx5_flow_tbl_resource *sfx_tbl;
795 /**< Meter suffix table. */
797 /**< Meter color not match default criteria. */
799 /**< Meter color match criteria. */
801 /**< Meter match action. */
802 void *policer_rules[RTE_MTR_DROPPED + 1];
803 /**< Meter policer for the match. */
806 /* Meter table set for TX RX FDB. */
807 struct mlx5_meter_domains_infos {
809 /**< Table user count. */
810 struct mlx5_meter_domain_info egress;
811 /**< TX meter table. */
812 struct mlx5_meter_domain_info ingress;
813 /**< RX meter table. */
814 struct mlx5_meter_domain_info transfer;
815 /**< FDB meter table. */
817 /**< Drop action as not matched. */
818 void *count_actns[RTE_MTR_DROPPED + 1];
819 /**< Counters for match and unmatched statistics. */
820 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
821 /**< Flow meter parameter. */
823 /**< Flow meter parameter size. */
825 /**< Flow meter action. */
828 /* Meter parameter structure. */
829 struct mlx5_flow_meter {
830 TAILQ_ENTRY(mlx5_flow_meter) next;
831 /**< Pointer to the next flow meter structure. */
832 uint32_t idx; /* Index to meter object. */
835 struct mlx5_flow_meter_profile *profile;
836 /**< Meter profile parameters. */
838 /** Policer actions (per meter output color). */
839 enum rte_mtr_policer_action action[RTE_COLORS];
841 /** Set of stats counters to be enabled.
842 * @see enum rte_mtr_stats_type
846 /**< Rule applies to ingress traffic. */
849 /**< Rule applies to egress traffic. */
852 * Instead of simply matching the properties of traffic as it would
853 * appear on a given DPDK port ID, enabling this attribute transfers
854 * a flow rule to the lowest possible level of any device endpoints
855 * found in the pattern.
857 * When supported, this effectively enables an application to
858 * re-route traffic not necessarily intended for it (e.g. coming
859 * from or addressed to different physical ports, VFs or
860 * applications) at the device level.
862 * It complements the behavior of some pattern items such as
863 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
865 * When transferring flow rules, ingress and egress attributes keep
866 * their original meaning, as if processing traffic emitted or
867 * received by the application.
870 struct mlx5_meter_domains_infos *mfts;
871 /**< Flow table created for this meter. */
872 struct mlx5_flow_policer_stats policer_stats;
873 /**< Meter policer statistics. */
876 uint32_t active_state:1;
879 /**< Meter shared or not. */
882 /* RFC2697 parameter structure. */
883 struct mlx5_flow_meter_srtcm_rfc2697_prm {
884 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
885 uint32_t cbs_exponent:5;
886 uint32_t cbs_mantissa:8;
887 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
888 uint32_t cir_exponent:5;
889 uint32_t cir_mantissa:8;
890 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
891 uint32_t ebs_exponent:5;
892 uint32_t ebs_mantissa:8;
895 /* Flow meter profile structure. */
896 struct mlx5_flow_meter_profile {
897 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
898 /**< Pointer to the next flow meter structure. */
899 uint32_t meter_profile_id; /**< Profile id. */
900 struct rte_mtr_meter_profile profile; /**< Profile detail. */
902 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
903 /**< srtcm_rfc2697 struct. */
905 uint32_t ref_cnt; /**< Use count. */
908 /* Fdir flow structure */
909 struct mlx5_fdir_flow {
910 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */
911 struct mlx5_fdir *fdir; /* Pointer to fdir. */
912 uint32_t rix_flow; /* Index to flow. */
915 #define HAIRPIN_FLOW_ID_BITS 28
917 /* Flow structure. */
919 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
920 struct mlx5_shared_action_rss *shared_rss; /** < Shred RSS action. */
921 uint32_t dev_handles;
922 /**< Device flow handles that are part of the flow. */
923 uint32_t drv_type:2; /**< Driver type. */
924 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */
925 uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS;
926 /**< The flow id used for hairpin. */
927 uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
928 uint32_t rix_mreg_copy;
929 /**< Index to metadata register copy table resource. */
930 uint32_t counter; /**< Holds flow counter. */
931 uint16_t meter; /**< Holds flow meter id. */
935 * Define list of valid combinations of RX Hash fields
936 * (see enum ibv_rx_hash_fields).
938 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
939 #define MLX5_RSS_HASH_IPV4_TCP \
940 (MLX5_RSS_HASH_IPV4 | \
941 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
942 #define MLX5_RSS_HASH_IPV4_UDP \
943 (MLX5_RSS_HASH_IPV4 | \
944 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
945 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
946 #define MLX5_RSS_HASH_IPV6_TCP \
947 (MLX5_RSS_HASH_IPV6 | \
948 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
949 #define MLX5_RSS_HASH_IPV6_UDP \
950 (MLX5_RSS_HASH_IPV6 | \
951 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
952 #define MLX5_RSS_HASH_NONE 0ULL
954 /* array of valid combinations of RX Hash fields for RSS */
955 static const uint64_t mlx5_rss_hash_fields[] = {
957 MLX5_RSS_HASH_IPV4_TCP,
958 MLX5_RSS_HASH_IPV4_UDP,
960 MLX5_RSS_HASH_IPV6_TCP,
961 MLX5_RSS_HASH_IPV6_UDP,
965 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
967 /* Shared RSS action structure */
968 struct mlx5_shared_action_rss {
969 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
970 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
971 uint16_t *queue; /**< Queue indices to use. */
972 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
973 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
974 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
975 /**< Hash RX queue indexes for tunneled RSS */
978 struct rte_flow_shared_action {
979 LIST_ENTRY(rte_flow_shared_action) next;
980 /**< Pointer to the next element. */
981 uint32_t refcnt; /**< Atomically accessed refcnt. */
983 /**< Shared action type (see MLX5_FLOW_ACTION_SHARED_*). */
985 struct mlx5_shared_action_rss rss;
986 /**< Shared RSS action. */
990 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
991 const struct rte_flow_attr *attr,
992 const struct rte_flow_item items[],
993 const struct rte_flow_action actions[],
996 struct rte_flow_error *error);
997 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
998 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
999 const struct rte_flow_item items[],
1000 const struct rte_flow_action actions[], struct rte_flow_error *error);
1001 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1002 struct mlx5_flow *dev_flow,
1003 const struct rte_flow_attr *attr,
1004 const struct rte_flow_item items[],
1005 const struct rte_flow_action actions[],
1006 struct rte_flow_error *error);
1007 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1008 struct rte_flow_error *error);
1009 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1010 struct rte_flow *flow);
1011 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1012 struct rte_flow *flow);
1013 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1014 struct rte_flow *flow,
1015 const struct rte_flow_action *actions,
1017 struct rte_flow_error *error);
1018 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1019 (struct rte_eth_dev *dev,
1020 const struct mlx5_flow_meter *fm);
1021 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1022 struct mlx5_meter_domains_infos *tbls);
1023 typedef int (*mlx5_flow_create_policer_rules_t)
1024 (struct rte_eth_dev *dev,
1025 struct mlx5_flow_meter *fm,
1026 const struct rte_flow_attr *attr);
1027 typedef int (*mlx5_flow_destroy_policer_rules_t)
1028 (struct rte_eth_dev *dev,
1029 const struct mlx5_flow_meter *fm,
1030 const struct rte_flow_attr *attr);
1031 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1032 (struct rte_eth_dev *dev);
1033 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1035 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1037 bool clear, uint64_t *pkts,
1039 typedef int (*mlx5_flow_get_aged_flows_t)
1040 (struct rte_eth_dev *dev,
1042 uint32_t nb_contexts,
1043 struct rte_flow_error *error);
1044 typedef int (*mlx5_flow_action_validate_t)
1045 (struct rte_eth_dev *dev,
1046 const struct rte_flow_shared_action_conf *conf,
1047 const struct rte_flow_action *action,
1048 struct rte_flow_error *error);
1049 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1050 (struct rte_eth_dev *dev,
1051 const struct rte_flow_shared_action_conf *conf,
1052 const struct rte_flow_action *action,
1053 struct rte_flow_error *error);
1054 typedef int (*mlx5_flow_action_destroy_t)
1055 (struct rte_eth_dev *dev,
1056 struct rte_flow_shared_action *action,
1057 struct rte_flow_error *error);
1058 typedef int (*mlx5_flow_action_update_t)
1059 (struct rte_eth_dev *dev,
1060 struct rte_flow_shared_action *action,
1061 const void *action_conf,
1062 struct rte_flow_error *error);
1063 struct mlx5_flow_driver_ops {
1064 mlx5_flow_validate_t validate;
1065 mlx5_flow_prepare_t prepare;
1066 mlx5_flow_translate_t translate;
1067 mlx5_flow_apply_t apply;
1068 mlx5_flow_remove_t remove;
1069 mlx5_flow_destroy_t destroy;
1070 mlx5_flow_query_t query;
1071 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1072 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1073 mlx5_flow_create_policer_rules_t create_policer_rules;
1074 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1075 mlx5_flow_counter_alloc_t counter_alloc;
1076 mlx5_flow_counter_free_t counter_free;
1077 mlx5_flow_counter_query_t counter_query;
1078 mlx5_flow_get_aged_flows_t get_aged_flows;
1079 mlx5_flow_action_validate_t action_validate;
1080 mlx5_flow_action_create_t action_create;
1081 mlx5_flow_action_destroy_t action_destroy;
1082 mlx5_flow_action_update_t action_update;
1087 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id);
1088 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
1089 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
1090 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
1092 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
1093 bool external, uint32_t group, bool fdb_def_rule,
1094 uint32_t *table, struct rte_flow_error *error);
1095 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1096 int tunnel, uint64_t layer_types,
1097 uint64_t hash_fields);
1098 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1099 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1100 uint32_t subpriority);
1101 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1102 enum mlx5_feature_name feature,
1104 struct rte_flow_error *error);
1105 const struct rte_flow_action *mlx5_flow_find_action
1106 (const struct rte_flow_action *actions,
1107 enum rte_flow_action_type action);
1108 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1109 const struct rte_flow_action *action,
1110 struct rte_flow_error *error);
1111 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1112 const struct rte_flow_attr *attr,
1113 struct rte_flow_error *error);
1114 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1115 const struct rte_flow_attr *attr,
1116 struct rte_flow_error *error);
1117 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1118 const struct rte_flow_attr *attr,
1119 struct rte_flow_error *error);
1120 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1121 uint64_t action_flags,
1122 const struct rte_flow_attr *attr,
1123 struct rte_flow_error *error);
1124 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1125 uint64_t action_flags,
1126 struct rte_eth_dev *dev,
1127 const struct rte_flow_attr *attr,
1128 struct rte_flow_error *error);
1129 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1130 uint64_t action_flags,
1131 struct rte_eth_dev *dev,
1132 const struct rte_flow_attr *attr,
1133 uint64_t item_flags,
1134 struct rte_flow_error *error);
1135 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1136 const struct rte_flow_attr *attr,
1137 struct rte_flow_error *error);
1138 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1139 const struct rte_flow_attr *attributes,
1140 struct rte_flow_error *error);
1141 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1142 const uint8_t *mask,
1143 const uint8_t *nic_mask,
1145 bool range_accepted,
1146 struct rte_flow_error *error);
1147 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1148 uint64_t item_flags,
1149 struct rte_flow_error *error);
1150 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1151 uint64_t item_flags,
1152 uint8_t target_protocol,
1153 struct rte_flow_error *error);
1154 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1155 uint64_t item_flags,
1156 const struct rte_flow_item *gre_item,
1157 struct rte_flow_error *error);
1158 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1159 uint64_t item_flags,
1161 uint16_t ether_type,
1162 const struct rte_flow_item_ipv4 *acc_mask,
1163 bool range_accepted,
1164 struct rte_flow_error *error);
1165 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1166 uint64_t item_flags,
1168 uint16_t ether_type,
1169 const struct rte_flow_item_ipv6 *acc_mask,
1170 struct rte_flow_error *error);
1171 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1172 const struct rte_flow_item *item,
1173 uint64_t item_flags,
1174 uint64_t prev_layer,
1175 struct rte_flow_error *error);
1176 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1177 uint64_t item_flags,
1178 uint8_t target_protocol,
1179 const struct rte_flow_item_tcp *flow_mask,
1180 struct rte_flow_error *error);
1181 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1182 uint64_t item_flags,
1183 uint8_t target_protocol,
1184 struct rte_flow_error *error);
1185 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1186 uint64_t item_flags,
1187 struct rte_eth_dev *dev,
1188 struct rte_flow_error *error);
1189 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1190 uint64_t item_flags,
1191 struct rte_flow_error *error);
1192 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1193 uint64_t item_flags,
1194 struct rte_eth_dev *dev,
1195 struct rte_flow_error *error);
1196 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1197 uint64_t item_flags,
1198 uint8_t target_protocol,
1199 struct rte_flow_error *error);
1200 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1201 uint64_t item_flags,
1202 uint8_t target_protocol,
1203 struct rte_flow_error *error);
1204 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1205 uint64_t item_flags,
1206 uint8_t target_protocol,
1207 struct rte_flow_error *error);
1208 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1209 uint64_t item_flags,
1210 struct rte_eth_dev *dev,
1211 struct rte_flow_error *error);
1212 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1213 uint64_t item_flags,
1215 uint16_t ether_type,
1216 const struct rte_flow_item_ecpri *acc_mask,
1217 struct rte_flow_error *error);
1218 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1219 (struct rte_eth_dev *dev,
1220 const struct mlx5_flow_meter *fm);
1221 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1222 struct mlx5_meter_domains_infos *tbl);
1223 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1224 struct mlx5_flow_meter *fm,
1225 const struct rte_flow_attr *attr);
1226 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1227 struct mlx5_flow_meter *fm,
1228 const struct rte_flow_attr *attr);
1229 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1230 struct rte_mtr_error *error);
1231 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1232 struct rte_flow_shared_action *mlx5_flow_get_shared_rss(struct rte_flow *flow);
1233 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1234 #endif /* RTE_PMD_MLX5_FLOW_H_ */