1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_alarm.h>
17 #include <mlx5_glue.h>
22 /* Private rte flow items. */
23 enum mlx5_rte_flow_item_type {
24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
25 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
38 MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS,
39 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
42 /* Matches on selected register. */
43 struct mlx5_rte_flow_item_tag {
48 /* Modify selected register. */
49 struct mlx5_rte_flow_action_set_tag {
54 struct mlx5_flow_action_copy_mreg {
59 /* Matches on source queue. */
60 struct mlx5_rte_flow_item_tx_queue {
64 /* Feature name to allocate metadata register. */
65 enum mlx5_feature_name {
78 /* Default queue number. */
79 #define MLX5_RSSQ_DEFAULT_NUM 16
81 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
82 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
83 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
84 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
85 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
86 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
88 /* Pattern inner Layer bits. */
89 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
90 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
91 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
92 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
93 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
94 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
96 /* Pattern tunnel Layer bits. */
97 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
98 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
99 #define MLX5_FLOW_LAYER_GRE (1u << 14)
100 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
101 /* List of tunnel Layer bits continued below. */
103 /* General pattern items bits. */
104 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
105 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
106 #define MLX5_FLOW_ITEM_TAG (1u << 18)
107 #define MLX5_FLOW_ITEM_MARK (1u << 19)
109 /* Pattern MISC bits. */
110 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
111 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
112 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
114 /* Pattern tunnel Layer bits (continued). */
115 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
116 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
117 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
118 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
121 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
123 /* Pattern tunnel Layer bits (continued). */
124 #define MLX5_FLOW_LAYER_GTP (1u << 28)
126 /* Pattern eCPRI Layer bit. */
127 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
129 /* IPv6 Fragment Extension Header bit. */
130 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
131 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
134 #define MLX5_FLOW_LAYER_OUTER_L3 \
135 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
136 #define MLX5_FLOW_LAYER_OUTER_L4 \
137 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
138 #define MLX5_FLOW_LAYER_OUTER \
139 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
140 MLX5_FLOW_LAYER_OUTER_L4)
143 #define MLX5_FLOW_LAYER_TUNNEL \
144 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
145 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
146 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
147 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
150 #define MLX5_FLOW_LAYER_INNER_L3 \
151 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
152 #define MLX5_FLOW_LAYER_INNER_L4 \
153 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
154 #define MLX5_FLOW_LAYER_INNER \
155 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
156 MLX5_FLOW_LAYER_INNER_L4)
159 #define MLX5_FLOW_LAYER_L2 \
160 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
161 #define MLX5_FLOW_LAYER_L3_IPV4 \
162 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
163 #define MLX5_FLOW_LAYER_L3_IPV6 \
164 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
165 #define MLX5_FLOW_LAYER_L3 \
166 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
167 #define MLX5_FLOW_LAYER_L4 \
168 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
171 #define MLX5_FLOW_ACTION_DROP (1u << 0)
172 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
173 #define MLX5_FLOW_ACTION_RSS (1u << 2)
174 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
175 #define MLX5_FLOW_ACTION_MARK (1u << 4)
176 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
177 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
178 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
179 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
180 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
181 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
182 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
183 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
184 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
185 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
186 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
187 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
188 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
189 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
190 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
191 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
192 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
193 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
194 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
195 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
196 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
197 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
198 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
199 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
200 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
201 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
202 #define MLX5_FLOW_ACTION_METER (1ull << 31)
203 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
204 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
205 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
206 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
207 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
208 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
209 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
211 #define MLX5_FLOW_FATE_ACTIONS \
212 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
213 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
214 MLX5_FLOW_ACTION_DEFAULT_MISS)
216 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
217 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
218 MLX5_FLOW_ACTION_JUMP)
221 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
222 MLX5_FLOW_ACTION_SET_IPV4_DST | \
223 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
224 MLX5_FLOW_ACTION_SET_IPV6_DST | \
225 MLX5_FLOW_ACTION_SET_TP_SRC | \
226 MLX5_FLOW_ACTION_SET_TP_DST | \
227 MLX5_FLOW_ACTION_SET_TTL | \
228 MLX5_FLOW_ACTION_DEC_TTL | \
229 MLX5_FLOW_ACTION_SET_MAC_SRC | \
230 MLX5_FLOW_ACTION_SET_MAC_DST | \
231 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
232 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
233 MLX5_FLOW_ACTION_INC_TCP_ACK | \
234 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
235 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
236 MLX5_FLOW_ACTION_SET_TAG | \
237 MLX5_FLOW_ACTION_MARK_EXT | \
238 MLX5_FLOW_ACTION_SET_META | \
239 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
240 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
242 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
243 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
245 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
248 #define IPPROTO_MPLS 137
251 /* UDP port number for MPLS */
252 #define MLX5_UDP_PORT_MPLS 6635
254 /* UDP port numbers for VxLAN. */
255 #define MLX5_UDP_PORT_VXLAN 4789
256 #define MLX5_UDP_PORT_VXLAN_GPE 4790
258 /* UDP port numbers for GENEVE. */
259 #define MLX5_UDP_PORT_GENEVE 6081
261 /* Priority reserved for default flows. */
262 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
265 * Number of sub priorities.
266 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
267 * matching on the NIC (firmware dependent) L4 most have the higher priority
268 * followed by L3 and ending with L2.
270 #define MLX5_PRIORITY_MAP_L2 2
271 #define MLX5_PRIORITY_MAP_L3 1
272 #define MLX5_PRIORITY_MAP_L4 0
273 #define MLX5_PRIORITY_MAP_MAX 3
275 /* Valid layer type for IPV4 RSS. */
276 #define MLX5_IPV4_LAYER_TYPES \
277 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
278 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
279 ETH_RSS_NONFRAG_IPV4_OTHER)
281 /* IBV hash source bits for IPV4. */
282 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
284 /* Valid layer type for IPV6 RSS. */
285 #define MLX5_IPV6_LAYER_TYPES \
286 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
287 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
288 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
290 /* IBV hash source bits for IPV6. */
291 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
293 /* IBV hash bits for L3 SRC. */
294 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
296 /* IBV hash bits for L3 DST. */
297 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
299 /* IBV hash bits for TCP. */
300 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
301 IBV_RX_HASH_DST_PORT_TCP)
303 /* IBV hash bits for UDP. */
304 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
305 IBV_RX_HASH_DST_PORT_UDP)
307 /* IBV hash bits for L4 SRC. */
308 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
309 IBV_RX_HASH_SRC_PORT_UDP)
311 /* IBV hash bits for L4 DST. */
312 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
313 IBV_RX_HASH_DST_PORT_UDP)
315 /* Geneve header first 16Bit */
316 #define MLX5_GENEVE_VER_MASK 0x3
317 #define MLX5_GENEVE_VER_SHIFT 14
318 #define MLX5_GENEVE_VER_VAL(a) \
319 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
320 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
321 #define MLX5_GENEVE_OPTLEN_SHIFT 7
322 #define MLX5_GENEVE_OPTLEN_VAL(a) \
323 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
324 #define MLX5_GENEVE_OAMF_MASK 0x1
325 #define MLX5_GENEVE_OAMF_SHIFT 7
326 #define MLX5_GENEVE_OAMF_VAL(a) \
327 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
328 #define MLX5_GENEVE_CRITO_MASK 0x1
329 #define MLX5_GENEVE_CRITO_SHIFT 6
330 #define MLX5_GENEVE_CRITO_VAL(a) \
331 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
332 #define MLX5_GENEVE_RSVD_MASK 0x3F
333 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
335 * The length of the Geneve options fields, expressed in four byte multiples,
336 * not including the eight byte fixed tunnel.
338 #define MLX5_GENEVE_OPT_LEN_0 14
339 #define MLX5_GENEVE_OPT_LEN_1 63
341 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
342 sizeof(struct rte_flow_item_ipv4))
344 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
345 #define MLX5_IPV4_FRAG_OFFSET_MASK \
346 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
348 /* Specific item's fields can accept a range of values (using spec and last). */
349 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
350 #define MLX5_ITEM_RANGE_ACCEPTED true
352 /* Software header modify action numbers of a flow. */
353 #define MLX5_ACT_NUM_MDF_IPV4 1
354 #define MLX5_ACT_NUM_MDF_IPV6 4
355 #define MLX5_ACT_NUM_MDF_MAC 2
356 #define MLX5_ACT_NUM_MDF_VID 1
357 #define MLX5_ACT_NUM_MDF_PORT 2
358 #define MLX5_ACT_NUM_MDF_TTL 1
359 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
360 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
361 #define MLX5_ACT_NUM_MDF_TCPACK 1
362 #define MLX5_ACT_NUM_SET_REG 1
363 #define MLX5_ACT_NUM_SET_TAG 1
364 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
365 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
366 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
367 #define MLX5_ACT_NUM_SET_DSCP 1
369 enum mlx5_flow_drv_type {
372 MLX5_FLOW_TYPE_VERBS,
376 /* Fate action type. */
377 enum mlx5_flow_fate_type {
378 MLX5_FLOW_FATE_NONE, /* Egress flow. */
379 MLX5_FLOW_FATE_QUEUE,
381 MLX5_FLOW_FATE_PORT_ID,
383 MLX5_FLOW_FATE_DEFAULT_MISS,
387 /* Hash list callback context */
388 struct mlx5_flow_cb_ctx {
389 struct rte_eth_dev *dev;
390 struct rte_flow_error *error;
394 /* Matcher PRM representation */
395 struct mlx5_flow_dv_match_params {
397 /**< Size of match value. Do NOT split size and key! */
398 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
399 /**< Matcher value. This value is used as the mask or as a key. */
402 /* Matcher structure. */
403 struct mlx5_flow_dv_matcher {
404 LIST_ENTRY(mlx5_flow_dv_matcher) next;
405 /**< Pointer to the next element. */
406 struct mlx5_flow_tbl_resource *tbl;
407 /**< Pointer to the table(group) the matcher associated with. */
408 uint32_t refcnt; /**< Reference counter. */
409 void *matcher_object; /**< Pointer to DV matcher */
410 uint16_t crc; /**< CRC of key. */
411 uint16_t priority; /**< Priority of matcher. */
412 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
415 #define MLX5_ENCAP_MAX_LEN 132
417 /* Encap/decap resource key of the hash organization. */
418 union mlx5_flow_encap_decap_key {
420 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
421 uint32_t refmt_type:8; /**< Header reformat type. */
422 uint32_t buf_size:8; /**< Encap buf size. */
423 uint32_t table_level:8; /**< Root table or not. */
424 uint32_t cksum; /**< Encap buf check sum. */
426 uint64_t v64; /**< full 64bits value of key */
429 /* Encap/decap resource structure. */
430 struct mlx5_flow_dv_encap_decap_resource {
431 struct mlx5_hlist_entry entry;
432 /* Pointer to next element. */
433 uint32_t refcnt; /**< Reference counter. */
435 /**< Encap/decap action object. */
436 uint8_t buf[MLX5_ENCAP_MAX_LEN];
438 uint8_t reformat_type;
440 uint64_t flags; /**< Flags for RDMA API. */
441 uint32_t idx; /**< Index for the index memory pool. */
444 /* Tag resource structure. */
445 struct mlx5_flow_dv_tag_resource {
446 struct mlx5_hlist_entry entry;
447 /**< hash list entry for tag resource, tag value as the key. */
449 /**< Tag action object. */
450 uint32_t refcnt; /**< Reference counter. */
451 uint32_t idx; /**< Index for the index memory pool. */
455 * Number of modification commands.
456 * The maximal actions amount in FW is some constant, and it is 16 in the
457 * latest releases. In some old releases, it will be limited to 8.
458 * Since there is no interface to query the capacity, the maximal value should
459 * be used to allow PMD to create the flow. The validation will be done in the
460 * lower driver layer or FW. A failure will be returned if exceeds the maximal
461 * supported actions number on the root table.
462 * On non-root tables, there is no limitation, but 32 is enough right now.
464 #define MLX5_MAX_MODIFY_NUM 32
465 #define MLX5_ROOT_TBL_MODIFY_NUM 16
467 /* Modify resource structure */
468 struct mlx5_flow_dv_modify_hdr_resource {
469 struct mlx5_hlist_entry entry;
470 void *action; /**< Modify header action object. */
471 /* Key area for hash list matching: */
472 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
473 uint32_t actions_num; /**< Number of modification actions. */
474 uint64_t flags; /**< Flags for RDMA API. */
475 struct mlx5_modification_cmd actions[];
476 /**< Modification actions. */
479 /* Modify resource key of the hash organization. */
480 union mlx5_flow_modify_hdr_key {
482 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
483 uint32_t actions_num:5; /**< Number of modification actions. */
484 uint32_t group:19; /**< Flow group id. */
485 uint32_t cksum; /**< Actions check sum. */
487 uint64_t v64; /**< full 64bits value of key */
490 /* Jump action resource structure. */
491 struct mlx5_flow_dv_jump_tbl_resource {
492 void *action; /**< Pointer to the rdma core action. */
495 /* Port ID resource structure. */
496 struct mlx5_flow_dv_port_id_action_resource {
497 ILIST_ENTRY(uint32_t)next;
498 /* Pointer to next element. */
499 uint32_t refcnt; /**< Reference counter. */
501 /**< Action object. */
502 uint32_t port_id; /**< Port ID value. */
505 /* Push VLAN action resource structure */
506 struct mlx5_flow_dv_push_vlan_action_resource {
507 ILIST_ENTRY(uint32_t)next;
508 /* Pointer to next element. */
509 uint32_t refcnt; /**< Reference counter. */
510 void *action; /**< Action object. */
511 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
512 rte_be32_t vlan_tag; /**< VLAN tag value. */
515 /* Metadata register copy table entry. */
516 struct mlx5_flow_mreg_copy_resource {
518 * Hash list entry for copy table.
519 * - Key is 32/64-bit MARK action ID.
520 * - MUST be the first entry.
522 struct mlx5_hlist_entry hlist_ent;
523 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
524 /* List entry for device flows. */
526 uint32_t rix_flow; /* Built flow for copy. */
529 /* Table tunnel parameter. */
530 struct mlx5_flow_tbl_tunnel_prm {
531 const struct mlx5_flow_tunnel *tunnel;
536 /* Table data structure of the hash organization. */
537 struct mlx5_flow_tbl_data_entry {
538 struct mlx5_hlist_entry entry;
539 /**< hash list entry, 64-bits key inside. */
540 struct mlx5_flow_tbl_resource tbl;
541 /**< flow table resource. */
542 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
543 /**< matchers' header associated with the flow table. */
544 struct mlx5_flow_dv_jump_tbl_resource jump;
545 /**< jump resource, at most one for each table created. */
546 uint32_t idx; /**< index for the indexed mempool. */
547 /**< tunnel offload */
548 const struct mlx5_flow_tunnel *tunnel;
551 bool tunnel_offload; /* Tunnel offlod table or not. */
554 /* Sub rdma-core actions list. */
555 struct mlx5_flow_sub_actions_list {
556 uint32_t actions_num; /**< Number of sample actions. */
557 uint64_t action_flags;
558 void *dr_queue_action;
561 void *dr_port_id_action;
562 void *dr_encap_action;
565 /* Sample sub-actions resource list. */
566 struct mlx5_flow_sub_actions_idx {
567 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
568 uint32_t rix_tag; /**< Index to the tag action. */
570 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
571 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
574 /* Sample action resource structure. */
575 struct mlx5_flow_dv_sample_resource {
576 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
577 uint32_t refcnt; /**< Reference counter. */
578 void *verbs_action; /**< Verbs sample action object. */
579 uint8_t ft_type; /** Flow Table Type */
580 uint32_t ft_id; /** Flow Table Level */
581 uint32_t ratio; /** Sample Ratio */
582 uint64_t set_action; /** Restore reg_c0 value */
583 void *normal_path_tbl; /** Flow Table pointer */
584 void *default_miss; /** default_miss dr_action. */
585 struct mlx5_flow_sub_actions_idx sample_idx;
586 /**< Action index resources. */
587 struct mlx5_flow_sub_actions_list sample_act;
588 /**< Action resources. */
591 #define MLX5_MAX_DEST_NUM 2
593 /* Destination array action resource structure. */
594 struct mlx5_flow_dv_dest_array_resource {
595 ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
596 uint32_t refcnt; /**< Reference counter. */
597 uint8_t ft_type; /** Flow Table Type */
598 uint8_t num_of_dest; /**< Number of destination actions. */
599 void *action; /**< Pointer to the rdma core action. */
600 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
601 /**< Action index resources. */
602 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
603 /**< Action resources. */
606 /* Verbs specification header. */
607 struct ibv_spec_header {
608 enum ibv_flow_spec_type type;
612 /* RSS description. */
613 struct mlx5_flow_rss_desc {
615 uint32_t queue_num; /**< Number of entries in @p queue. */
616 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
617 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
618 uint16_t *queue; /**< Destination queues. */
621 /* PMD flow priority for tunnel */
622 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
623 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
626 /** Device flow handle structure for DV mode only. */
627 struct mlx5_flow_handle_dv {
629 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
630 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
631 /**< Pointer to modify header resource in cache. */
632 uint32_t rix_encap_decap;
633 /**< Index to encap/decap resource in cache. */
634 uint32_t rix_push_vlan;
635 /**< Index to push VLAN action resource in cache. */
637 /**< Index to the tag action. */
639 /**< Index to sample action resource in cache. */
640 uint32_t rix_dest_array;
641 /**< Index to destination array resource in cache. */
644 /** Device flow handle structure: used both for creating & destroying. */
645 struct mlx5_flow_handle {
646 SILIST_ENTRY(uint32_t)next;
647 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
648 /**< Index to next device flow handle. */
650 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
651 void *drv_flow; /**< pointer to driver flow object. */
652 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
653 uint32_t mark:1; /**< Metadate rxq mark flag. */
654 uint32_t fate_action:3; /**< Fate action type. */
656 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
657 uint32_t rix_jump; /**< Index to the jump action resource. */
658 uint32_t rix_port_id_action;
659 /**< Index to port ID action resource. */
661 /**< Generic value indicates the fate action. */
662 uint32_t rix_default_fate;
663 /**< Indicates default miss fate action. */
665 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
666 struct mlx5_flow_handle_dv dvh;
671 * Size for Verbs device flow handle structure only. Do not use the DV only
672 * structure in Verbs. No DV flows attributes will be accessed.
673 * Macro offsetof() could also be used here.
675 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
676 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
677 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
679 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
683 * Max number of actions per DV flow.
684 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
685 * in rdma-core file providers/mlx5/verbs.c.
687 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
689 /** Device flow structure only for DV flow creation. */
690 struct mlx5_flow_dv_workspace {
691 uint32_t group; /**< The group index. */
692 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
693 int actions_n; /**< number of actions. */
694 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
695 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
696 /**< Pointer to encap/decap resource in cache. */
697 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
698 /**< Pointer to push VLAN action resource in cache. */
699 struct mlx5_flow_dv_tag_resource *tag_resource;
700 /**< pointer to the tag action. */
701 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
702 /**< Pointer to port ID action resource. */
703 struct mlx5_flow_dv_jump_tbl_resource *jump;
704 /**< Pointer to the jump action resource. */
705 struct mlx5_flow_dv_match_params value;
706 /**< Holds the value that the packet is compared to. */
707 struct mlx5_flow_dv_sample_resource *sample_res;
708 /**< Pointer to the sample action resource. */
709 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
710 /**< Pointer to the destination array resource. */
714 * Maximal Verbs flow specifications & actions size.
715 * Some elements are mutually exclusive, but enough space should be allocated.
716 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
717 * 2. One tunnel header (exception: GRE + MPLS),
718 * SPEC length: GRE == tunnel.
719 * Actions: 1. 1 Mark OR Flag.
720 * 2. 1 Drop (if any).
721 * 3. No limitation for counters, but it makes no sense to support too
722 * many counters in a single device flow.
724 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
725 #define MLX5_VERBS_MAX_SPEC_SIZE \
727 (2 * (sizeof(struct ibv_flow_spec_eth) + \
728 sizeof(struct ibv_flow_spec_ipv6) + \
729 sizeof(struct ibv_flow_spec_tcp_udp)) + \
730 sizeof(struct ibv_flow_spec_gre) + \
731 sizeof(struct ibv_flow_spec_mpls)) \
734 #define MLX5_VERBS_MAX_SPEC_SIZE \
736 (2 * (sizeof(struct ibv_flow_spec_eth) + \
737 sizeof(struct ibv_flow_spec_ipv6) + \
738 sizeof(struct ibv_flow_spec_tcp_udp)) + \
739 sizeof(struct ibv_flow_spec_tunnel)) \
743 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
744 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
745 #define MLX5_VERBS_MAX_ACT_SIZE \
747 sizeof(struct ibv_flow_spec_action_tag) + \
748 sizeof(struct ibv_flow_spec_action_drop) + \
749 sizeof(struct ibv_flow_spec_counter_action) * 4 \
752 #define MLX5_VERBS_MAX_ACT_SIZE \
754 sizeof(struct ibv_flow_spec_action_tag) + \
755 sizeof(struct ibv_flow_spec_action_drop) \
759 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
760 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
762 /** Device flow structure only for Verbs flow creation. */
763 struct mlx5_flow_verbs_workspace {
764 unsigned int size; /**< Size of the attribute. */
765 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
766 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
767 /**< Specifications & actions buffer of verbs flow. */
770 /** Maximal number of device sub-flows supported. */
771 #define MLX5_NUM_MAX_DEV_FLOWS 32
773 /** Device flow structure. */
775 struct rte_flow *flow; /**< Pointer to the main flow. */
776 uint32_t flow_idx; /**< The memory pool index to the main flow. */
777 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
779 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
780 bool external; /**< true if the flow is created external to PMD. */
781 uint8_t ingress; /**< 1 if the flow is ingress. */
783 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
784 struct mlx5_flow_dv_workspace dv;
786 struct mlx5_flow_verbs_workspace verbs;
788 struct mlx5_flow_handle *handle;
789 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
790 const struct mlx5_flow_tunnel *tunnel;
793 /* Flow meter state. */
794 #define MLX5_FLOW_METER_DISABLE 0
795 #define MLX5_FLOW_METER_ENABLE 1
797 #define MLX5_MAN_WIDTH 8
798 /* Modify this value if enum rte_mtr_color changes. */
799 #define RTE_MTR_DROPPED RTE_COLORS
801 /* Meter policer statistics */
802 struct mlx5_flow_policer_stats {
803 uint32_t cnt[RTE_COLORS + 1];
804 /**< Color counter, extra for drop. */
806 /**< Statistics mask for the colors. */
809 /* Meter table structure. */
810 struct mlx5_meter_domain_info {
811 struct mlx5_flow_tbl_resource *tbl;
813 struct mlx5_flow_tbl_resource *sfx_tbl;
814 /**< Meter suffix table. */
816 /**< Meter color not match default criteria. */
818 /**< Meter color match criteria. */
820 /**< Meter match action. */
821 void *policer_rules[RTE_MTR_DROPPED + 1];
822 /**< Meter policer for the match. */
825 /* Meter table set for TX RX FDB. */
826 struct mlx5_meter_domains_infos {
828 /**< Table user count. */
829 struct mlx5_meter_domain_info egress;
830 /**< TX meter table. */
831 struct mlx5_meter_domain_info ingress;
832 /**< RX meter table. */
833 struct mlx5_meter_domain_info transfer;
834 /**< FDB meter table. */
836 /**< Drop action as not matched. */
837 void *count_actns[RTE_MTR_DROPPED + 1];
838 /**< Counters for match and unmatched statistics. */
839 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
840 /**< Flow meter parameter. */
842 /**< Flow meter parameter size. */
844 /**< Flow meter action. */
847 /* Meter parameter structure. */
848 struct mlx5_flow_meter {
849 TAILQ_ENTRY(mlx5_flow_meter) next;
850 /**< Pointer to the next flow meter structure. */
851 uint32_t idx; /* Index to meter object. */
854 struct mlx5_flow_meter_profile *profile;
855 /**< Meter profile parameters. */
857 rte_spinlock_t sl; /**< Meter action spinlock. */
859 /** Policer actions (per meter output color). */
860 enum rte_mtr_policer_action action[RTE_COLORS];
862 /** Set of stats counters to be enabled.
863 * @see enum rte_mtr_stats_type
867 /**< Rule applies to ingress traffic. */
870 /**< Rule applies to egress traffic. */
873 * Instead of simply matching the properties of traffic as it would
874 * appear on a given DPDK port ID, enabling this attribute transfers
875 * a flow rule to the lowest possible level of any device endpoints
876 * found in the pattern.
878 * When supported, this effectively enables an application to
879 * re-route traffic not necessarily intended for it (e.g. coming
880 * from or addressed to different physical ports, VFs or
881 * applications) at the device level.
883 * It complements the behavior of some pattern items such as
884 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
886 * When transferring flow rules, ingress and egress attributes keep
887 * their original meaning, as if processing traffic emitted or
888 * received by the application.
891 struct mlx5_meter_domains_infos *mfts;
892 /**< Flow table created for this meter. */
893 struct mlx5_flow_policer_stats policer_stats;
894 /**< Meter policer statistics. */
897 uint32_t active_state:1;
900 /**< Meter shared or not. */
903 /* RFC2697 parameter structure. */
904 struct mlx5_flow_meter_srtcm_rfc2697_prm {
905 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
906 uint32_t cbs_exponent:5;
907 uint32_t cbs_mantissa:8;
908 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
909 uint32_t cir_exponent:5;
910 uint32_t cir_mantissa:8;
911 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
912 uint32_t ebs_exponent:5;
913 uint32_t ebs_mantissa:8;
916 /* Flow meter profile structure. */
917 struct mlx5_flow_meter_profile {
918 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
919 /**< Pointer to the next flow meter structure. */
920 uint32_t meter_profile_id; /**< Profile id. */
921 struct rte_mtr_meter_profile profile; /**< Profile detail. */
923 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
924 /**< srtcm_rfc2697 struct. */
926 uint32_t ref_cnt; /**< Use count. */
929 /* Fdir flow structure */
930 struct mlx5_fdir_flow {
931 LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */
932 struct mlx5_fdir *fdir; /* Pointer to fdir. */
933 uint32_t rix_flow; /* Index to flow. */
936 #define MLX5_MAX_TUNNELS 256
937 #define MLX5_TNL_MISS_RULE_PRIORITY 3
938 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
941 * When tunnel offload is active, all JUMP group ids are converted
942 * using the same method. That conversion is applied both to tunnel and
943 * regular rule types.
944 * Group ids used in tunnel rules are relative to it's tunnel (!).
945 * Application can create number of steer rules, using the same
946 * tunnel, with different group id in each rule.
947 * Each tunnel stores its groups internally in PMD tunnel object.
948 * Groups used in regular rules do not belong to any tunnel and are stored
952 struct mlx5_flow_tunnel {
953 LIST_ENTRY(mlx5_flow_tunnel) chain;
954 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
955 uint32_t tunnel_id; /** unique tunnel ID */
957 struct rte_flow_action action;
958 struct rte_flow_item item;
959 struct mlx5_hlist *groups; /** tunnel groups */
962 /** PMD tunnel related context */
963 struct mlx5_flow_tunnel_hub {
964 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
965 struct mlx5_hlist *groups; /** non tunnel groups */
968 /* convert jump group to flow table ID in tunnel rules */
969 struct tunnel_tbl_entry {
970 struct mlx5_hlist_entry hash;
974 static inline uint32_t
975 tunnel_id_to_flow_tbl(uint32_t id)
977 return id | (1u << 16);
980 static inline uint32_t
981 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
983 return flow_tbl & ~(1u << 16);
986 union tunnel_tbl_key {
994 static inline struct mlx5_flow_tunnel_hub *
995 mlx5_tunnel_hub(struct rte_eth_dev *dev)
997 struct mlx5_priv *priv = dev->data->dev_private;
998 return priv->sh->tunnel_hub;
1002 is_tunnel_offload_active(struct rte_eth_dev *dev)
1004 struct mlx5_priv *priv = dev->data->dev_private;
1005 return !!priv->config.dv_miss_info;
1009 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
1010 __rte_unused const struct rte_flow_attr *attr,
1011 __rte_unused const struct rte_flow_item items[],
1012 __rte_unused const struct rte_flow_action actions[])
1014 return (items[0].type == (typeof(items[0].type))
1015 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1019 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1020 __rte_unused const struct rte_flow_attr *attr,
1021 __rte_unused const struct rte_flow_item items[],
1022 __rte_unused const struct rte_flow_action actions[])
1024 return (actions[0].type == (typeof(actions[0].type))
1025 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1028 static inline const struct mlx5_flow_tunnel *
1029 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1031 return actions[0].conf;
1034 static inline const struct mlx5_flow_tunnel *
1035 flow_items_to_tunnel(const struct rte_flow_item items[])
1037 return items[0].spec;
1040 /* Flow structure. */
1042 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1043 struct mlx5_shared_action_rss *shared_rss; /** < Shred RSS action. */
1044 uint32_t dev_handles;
1045 /**< Device flow handles that are part of the flow. */
1046 uint32_t drv_type:2; /**< Driver type. */
1047 uint32_t fdir:1; /**< Identifier of associated FDIR if any. */
1049 uint32_t meter:16; /**< Holds flow meter id. */
1050 uint32_t rix_mreg_copy;
1051 /**< Index to metadata register copy table resource. */
1052 uint32_t counter; /**< Holds flow counter. */
1053 uint32_t tunnel_id; /**< Tunnel id */
1057 * Define list of valid combinations of RX Hash fields
1058 * (see enum ibv_rx_hash_fields).
1060 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1061 #define MLX5_RSS_HASH_IPV4_TCP \
1062 (MLX5_RSS_HASH_IPV4 | \
1063 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1064 #define MLX5_RSS_HASH_IPV4_UDP \
1065 (MLX5_RSS_HASH_IPV4 | \
1066 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1067 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1068 #define MLX5_RSS_HASH_IPV6_TCP \
1069 (MLX5_RSS_HASH_IPV6 | \
1070 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1071 #define MLX5_RSS_HASH_IPV6_UDP \
1072 (MLX5_RSS_HASH_IPV6 | \
1073 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1074 #define MLX5_RSS_HASH_NONE 0ULL
1076 /* array of valid combinations of RX Hash fields for RSS */
1077 static const uint64_t mlx5_rss_hash_fields[] = {
1079 MLX5_RSS_HASH_IPV4_TCP,
1080 MLX5_RSS_HASH_IPV4_UDP,
1082 MLX5_RSS_HASH_IPV6_TCP,
1083 MLX5_RSS_HASH_IPV6_UDP,
1087 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
1089 /* Shared RSS action structure */
1090 struct mlx5_shared_action_rss {
1091 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1092 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1093 uint16_t *queue; /**< Queue indices to use. */
1094 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1095 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1096 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
1097 /**< Hash RX queue indexes for tunneled RSS */
1100 struct rte_flow_shared_action {
1101 LIST_ENTRY(rte_flow_shared_action) next;
1102 /**< Pointer to the next element. */
1103 uint32_t refcnt; /**< Atomically accessed refcnt. */
1105 /**< Shared action type (see MLX5_FLOW_ACTION_SHARED_*). */
1107 struct mlx5_shared_action_rss rss;
1108 /**< Shared RSS action. */
1112 /* Thread specific flow workspace intermediate data. */
1113 struct mlx5_flow_workspace {
1114 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1115 struct mlx5_flow_rss_desc rss_desc[2];
1116 uint32_t rssq_num[2]; /* Allocated queue num in rss_desc. */
1117 int flow_idx; /* Intermediate device flow index. */
1118 int flow_nested_idx; /* Intermediate device flow index, nested. */
1121 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1122 const struct rte_flow_attr *attr,
1123 const struct rte_flow_item items[],
1124 const struct rte_flow_action actions[],
1127 struct rte_flow_error *error);
1128 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1129 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1130 const struct rte_flow_item items[],
1131 const struct rte_flow_action actions[], struct rte_flow_error *error);
1132 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1133 struct mlx5_flow *dev_flow,
1134 const struct rte_flow_attr *attr,
1135 const struct rte_flow_item items[],
1136 const struct rte_flow_action actions[],
1137 struct rte_flow_error *error);
1138 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1139 struct rte_flow_error *error);
1140 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1141 struct rte_flow *flow);
1142 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1143 struct rte_flow *flow);
1144 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1145 struct rte_flow *flow,
1146 const struct rte_flow_action *actions,
1148 struct rte_flow_error *error);
1149 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1150 (struct rte_eth_dev *dev,
1151 const struct mlx5_flow_meter *fm);
1152 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1153 struct mlx5_meter_domains_infos *tbls);
1154 typedef int (*mlx5_flow_create_policer_rules_t)
1155 (struct rte_eth_dev *dev,
1156 struct mlx5_flow_meter *fm,
1157 const struct rte_flow_attr *attr);
1158 typedef int (*mlx5_flow_destroy_policer_rules_t)
1159 (struct rte_eth_dev *dev,
1160 const struct mlx5_flow_meter *fm,
1161 const struct rte_flow_attr *attr);
1162 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1163 (struct rte_eth_dev *dev);
1164 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1166 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1168 bool clear, uint64_t *pkts,
1170 typedef int (*mlx5_flow_get_aged_flows_t)
1171 (struct rte_eth_dev *dev,
1173 uint32_t nb_contexts,
1174 struct rte_flow_error *error);
1175 typedef int (*mlx5_flow_action_validate_t)
1176 (struct rte_eth_dev *dev,
1177 const struct rte_flow_shared_action_conf *conf,
1178 const struct rte_flow_action *action,
1179 struct rte_flow_error *error);
1180 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1181 (struct rte_eth_dev *dev,
1182 const struct rte_flow_shared_action_conf *conf,
1183 const struct rte_flow_action *action,
1184 struct rte_flow_error *error);
1185 typedef int (*mlx5_flow_action_destroy_t)
1186 (struct rte_eth_dev *dev,
1187 struct rte_flow_shared_action *action,
1188 struct rte_flow_error *error);
1189 typedef int (*mlx5_flow_action_update_t)
1190 (struct rte_eth_dev *dev,
1191 struct rte_flow_shared_action *action,
1192 const void *action_conf,
1193 struct rte_flow_error *error);
1194 typedef int (*mlx5_flow_sync_domain_t)
1195 (struct rte_eth_dev *dev,
1198 struct mlx5_flow_driver_ops {
1199 mlx5_flow_validate_t validate;
1200 mlx5_flow_prepare_t prepare;
1201 mlx5_flow_translate_t translate;
1202 mlx5_flow_apply_t apply;
1203 mlx5_flow_remove_t remove;
1204 mlx5_flow_destroy_t destroy;
1205 mlx5_flow_query_t query;
1206 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1207 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1208 mlx5_flow_create_policer_rules_t create_policer_rules;
1209 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1210 mlx5_flow_counter_alloc_t counter_alloc;
1211 mlx5_flow_counter_free_t counter_free;
1212 mlx5_flow_counter_query_t counter_query;
1213 mlx5_flow_get_aged_flows_t get_aged_flows;
1214 mlx5_flow_action_validate_t action_validate;
1215 mlx5_flow_action_create_t action_create;
1216 mlx5_flow_action_destroy_t action_destroy;
1217 mlx5_flow_action_update_t action_update;
1218 mlx5_flow_sync_domain_t sync_domain;
1223 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1225 struct flow_grp_info {
1226 uint64_t external:1;
1227 uint64_t transfer:1;
1228 uint64_t fdb_def_rule:1;
1229 /* force standard group translation */
1230 uint64_t std_tbl_fix:1;
1234 tunnel_use_standard_attr_group_translate
1235 (struct rte_eth_dev *dev,
1236 const struct mlx5_flow_tunnel *tunnel,
1237 const struct rte_flow_attr *attr,
1238 const struct rte_flow_item items[],
1239 const struct rte_flow_action actions[])
1243 if (!is_tunnel_offload_active(dev))
1244 /* no tunnel offload API */
1248 * OvS will use jump to group 0 in tunnel steer rule.
1249 * If tunnel steer rule starts from group 0 (attr.group == 0)
1250 * that 0 group must be translated with standard method.
1251 * attr.group == 0 in tunnel match rule translated with tunnel
1254 verdict = !attr->group &&
1255 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1258 * non-tunnel group translation uses standard method for
1259 * root group only: attr.group == 0
1261 verdict = !attr->group;
1267 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1268 const struct mlx5_flow_tunnel *tunnel,
1269 uint32_t group, uint32_t *table,
1270 struct flow_grp_info flags,
1271 struct rte_flow_error *error);
1272 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1273 int tunnel, uint64_t layer_types,
1274 uint64_t hash_fields);
1275 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1276 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1277 uint32_t subpriority);
1278 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1279 enum mlx5_feature_name feature,
1281 struct rte_flow_error *error);
1282 const struct rte_flow_action *mlx5_flow_find_action
1283 (const struct rte_flow_action *actions,
1284 enum rte_flow_action_type action);
1285 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1286 const struct rte_flow_action *action,
1287 struct rte_flow_error *error);
1288 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1289 const struct rte_flow_attr *attr,
1290 struct rte_flow_error *error);
1291 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1292 const struct rte_flow_attr *attr,
1293 struct rte_flow_error *error);
1294 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1295 const struct rte_flow_attr *attr,
1296 struct rte_flow_error *error);
1297 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1298 uint64_t action_flags,
1299 const struct rte_flow_attr *attr,
1300 struct rte_flow_error *error);
1301 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1302 uint64_t action_flags,
1303 struct rte_eth_dev *dev,
1304 const struct rte_flow_attr *attr,
1305 struct rte_flow_error *error);
1306 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1307 uint64_t action_flags,
1308 struct rte_eth_dev *dev,
1309 const struct rte_flow_attr *attr,
1310 uint64_t item_flags,
1311 struct rte_flow_error *error);
1312 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1313 const struct rte_flow_attr *attr,
1314 struct rte_flow_error *error);
1315 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1316 const struct rte_flow_attr *attributes,
1317 struct rte_flow_error *error);
1318 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1319 const uint8_t *mask,
1320 const uint8_t *nic_mask,
1322 bool range_accepted,
1323 struct rte_flow_error *error);
1324 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1325 uint64_t item_flags, bool ext_vlan_sup,
1326 struct rte_flow_error *error);
1327 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1328 uint64_t item_flags,
1329 uint8_t target_protocol,
1330 struct rte_flow_error *error);
1331 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1332 uint64_t item_flags,
1333 const struct rte_flow_item *gre_item,
1334 struct rte_flow_error *error);
1335 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1336 uint64_t item_flags,
1338 uint16_t ether_type,
1339 const struct rte_flow_item_ipv4 *acc_mask,
1340 bool range_accepted,
1341 struct rte_flow_error *error);
1342 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1343 uint64_t item_flags,
1345 uint16_t ether_type,
1346 const struct rte_flow_item_ipv6 *acc_mask,
1347 struct rte_flow_error *error);
1348 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1349 const struct rte_flow_item *item,
1350 uint64_t item_flags,
1351 uint64_t prev_layer,
1352 struct rte_flow_error *error);
1353 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1354 uint64_t item_flags,
1355 uint8_t target_protocol,
1356 const struct rte_flow_item_tcp *flow_mask,
1357 struct rte_flow_error *error);
1358 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1359 uint64_t item_flags,
1360 uint8_t target_protocol,
1361 struct rte_flow_error *error);
1362 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1363 uint64_t item_flags,
1364 struct rte_eth_dev *dev,
1365 struct rte_flow_error *error);
1366 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1367 uint64_t item_flags,
1368 struct rte_flow_error *error);
1369 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1370 uint64_t item_flags,
1371 struct rte_eth_dev *dev,
1372 struct rte_flow_error *error);
1373 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1374 uint64_t item_flags,
1375 uint8_t target_protocol,
1376 struct rte_flow_error *error);
1377 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1378 uint64_t item_flags,
1379 uint8_t target_protocol,
1380 struct rte_flow_error *error);
1381 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1382 uint64_t item_flags,
1383 uint8_t target_protocol,
1384 struct rte_flow_error *error);
1385 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1386 uint64_t item_flags,
1387 struct rte_eth_dev *dev,
1388 struct rte_flow_error *error);
1389 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1390 uint64_t item_flags,
1392 uint16_t ether_type,
1393 const struct rte_flow_item_ecpri *acc_mask,
1394 struct rte_flow_error *error);
1395 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1396 (struct rte_eth_dev *dev,
1397 const struct mlx5_flow_meter *fm);
1398 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1399 struct mlx5_meter_domains_infos *tbl);
1400 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1401 struct mlx5_flow_meter *fm,
1402 const struct rte_flow_attr *attr);
1403 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1404 struct mlx5_flow_meter *fm,
1405 const struct rte_flow_attr *attr);
1406 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1407 struct rte_mtr_error *error);
1408 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1409 struct rte_flow_shared_action *mlx5_flow_get_shared_rss(struct rte_flow *flow);
1410 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1411 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1412 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1414 /* Hash list callbacks for flow tables: */
1415 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1416 uint64_t key, void *entry_ctx);
1417 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1418 struct mlx5_hlist_entry *entry);
1419 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1420 uint32_t table_id, uint8_t egress, uint8_t transfer,
1421 bool external, const struct mlx5_flow_tunnel *tunnel,
1422 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error);
1424 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1425 uint64_t key, void *cb_ctx);
1426 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1427 struct mlx5_hlist_entry *entry);
1429 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1430 struct mlx5_hlist_entry *entry,
1431 uint64_t key, void *cb_ctx);
1432 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1433 uint64_t key, void *ctx);
1434 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1435 struct mlx5_hlist_entry *entry);
1437 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1438 uint64_t key, void *ctx);
1439 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1440 struct mlx5_hlist_entry *entry);
1442 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1443 struct mlx5_hlist_entry *entry,
1444 uint64_t key, void *cb_ctx);
1445 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1446 uint64_t key, void *cb_ctx);
1447 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1448 struct mlx5_hlist_entry *entry);
1449 #endif /* RTE_PMD_MLX5_FLOW_H_ */