1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
30 /* Private rte flow items. */
31 enum mlx5_rte_flow_item_type {
32 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
33 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
34 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
37 /* Private (internal) rte flow actions. */
38 enum mlx5_rte_flow_action_type {
39 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
40 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
41 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
44 /* Matches on selected register. */
45 struct mlx5_rte_flow_item_tag {
50 /* Modify selected register. */
51 struct mlx5_rte_flow_action_set_tag {
56 struct mlx5_flow_action_copy_mreg {
61 /* Matches on source queue. */
62 struct mlx5_rte_flow_item_tx_queue {
66 /* Feature name to allocate metadata register. */
67 enum mlx5_feature_name {
78 /* Pattern outer Layer bits. */
79 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
80 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
81 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
82 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
83 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
84 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
86 /* Pattern inner Layer bits. */
87 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
88 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
89 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
90 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
91 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
92 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
94 /* Pattern tunnel Layer bits. */
95 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
96 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
97 #define MLX5_FLOW_LAYER_GRE (1u << 14)
98 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
99 /* List of tunnel Layer bits continued below. */
101 /* General pattern items bits. */
102 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
103 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
104 #define MLX5_FLOW_ITEM_TAG (1u << 18)
105 #define MLX5_FLOW_ITEM_MARK (1u << 19)
107 /* Pattern MISC bits. */
108 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
109 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
110 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
112 /* Pattern tunnel Layer bits (continued). */
113 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
114 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
115 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
116 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
119 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
122 #define MLX5_FLOW_LAYER_OUTER_L3 \
123 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
124 #define MLX5_FLOW_LAYER_OUTER_L4 \
125 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
126 #define MLX5_FLOW_LAYER_OUTER \
127 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
128 MLX5_FLOW_LAYER_OUTER_L4)
130 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
131 #define MLX5_FLOW_LAYER_IPV4_LRO \
132 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
133 #define MLX5_FLOW_LAYER_IPV6_LRO \
134 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
137 #define MLX5_FLOW_LAYER_TUNNEL \
138 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
139 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
140 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
141 MLX5_FLOW_LAYER_GENEVE)
144 #define MLX5_FLOW_LAYER_INNER_L3 \
145 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
146 #define MLX5_FLOW_LAYER_INNER_L4 \
147 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
148 #define MLX5_FLOW_LAYER_INNER \
149 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
150 MLX5_FLOW_LAYER_INNER_L4)
153 #define MLX5_FLOW_LAYER_L2 \
154 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
155 #define MLX5_FLOW_LAYER_L3_IPV4 \
156 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
157 #define MLX5_FLOW_LAYER_L3_IPV6 \
158 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
159 #define MLX5_FLOW_LAYER_L3 \
160 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
161 #define MLX5_FLOW_LAYER_L4 \
162 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
165 #define MLX5_FLOW_ACTION_DROP (1u << 0)
166 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
167 #define MLX5_FLOW_ACTION_RSS (1u << 2)
168 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
169 #define MLX5_FLOW_ACTION_MARK (1u << 4)
170 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
171 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
172 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
173 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
174 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
175 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
176 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
177 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
178 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
179 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
180 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
181 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
182 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
183 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
184 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
185 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
186 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
187 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
188 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
189 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
190 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
191 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
192 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
193 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
194 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
195 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
196 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
197 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
198 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33)
199 #define MLX5_FLOW_ACTION_SET_META (1ull << 34)
201 #define MLX5_FLOW_FATE_ACTIONS \
202 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
203 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
205 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
206 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
207 MLX5_FLOW_ACTION_JUMP)
209 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
210 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
211 MLX5_FLOW_ACTION_RAW_ENCAP | \
212 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
214 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
215 MLX5_FLOW_ACTION_NVGRE_DECAP | \
216 MLX5_FLOW_ACTION_RAW_DECAP | \
217 MLX5_FLOW_ACTION_OF_POP_VLAN)
219 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
220 MLX5_FLOW_ACTION_SET_IPV4_DST | \
221 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
222 MLX5_FLOW_ACTION_SET_IPV6_DST | \
223 MLX5_FLOW_ACTION_SET_TP_SRC | \
224 MLX5_FLOW_ACTION_SET_TP_DST | \
225 MLX5_FLOW_ACTION_SET_TTL | \
226 MLX5_FLOW_ACTION_DEC_TTL | \
227 MLX5_FLOW_ACTION_SET_MAC_SRC | \
228 MLX5_FLOW_ACTION_SET_MAC_DST | \
229 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
230 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
231 MLX5_FLOW_ACTION_INC_TCP_ACK | \
232 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
233 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
234 MLX5_FLOW_ACTION_SET_TAG | \
235 MLX5_FLOW_ACTION_MARK_EXT | \
236 MLX5_FLOW_ACTION_SET_META)
238 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
239 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
241 #define IPPROTO_MPLS 137
244 /* UDP port number for MPLS */
245 #define MLX5_UDP_PORT_MPLS 6635
247 /* UDP port numbers for VxLAN. */
248 #define MLX5_UDP_PORT_VXLAN 4789
249 #define MLX5_UDP_PORT_VXLAN_GPE 4790
251 /* UDP port numbers for GENEVE. */
252 #define MLX5_UDP_PORT_GENEVE 6081
254 /* Priority reserved for default flows. */
255 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
258 * Number of sub priorities.
259 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
260 * matching on the NIC (firmware dependent) L4 most have the higher priority
261 * followed by L3 and ending with L2.
263 #define MLX5_PRIORITY_MAP_L2 2
264 #define MLX5_PRIORITY_MAP_L3 1
265 #define MLX5_PRIORITY_MAP_L4 0
266 #define MLX5_PRIORITY_MAP_MAX 3
268 /* Valid layer type for IPV4 RSS. */
269 #define MLX5_IPV4_LAYER_TYPES \
270 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
271 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
272 ETH_RSS_NONFRAG_IPV4_OTHER)
274 /* IBV hash source bits for IPV4. */
275 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
277 /* Valid layer type for IPV6 RSS. */
278 #define MLX5_IPV6_LAYER_TYPES \
279 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
280 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
281 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
283 /* IBV hash source bits for IPV6. */
284 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
287 /* Geneve header first 16Bit */
288 #define MLX5_GENEVE_VER_MASK 0x3
289 #define MLX5_GENEVE_VER_SHIFT 14
290 #define MLX5_GENEVE_VER_VAL(a) \
291 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
292 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
293 #define MLX5_GENEVE_OPTLEN_SHIFT 7
294 #define MLX5_GENEVE_OPTLEN_VAL(a) \
295 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
296 #define MLX5_GENEVE_OAMF_MASK 0x1
297 #define MLX5_GENEVE_OAMF_SHIFT 7
298 #define MLX5_GENEVE_OAMF_VAL(a) \
299 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
300 #define MLX5_GENEVE_CRITO_MASK 0x1
301 #define MLX5_GENEVE_CRITO_SHIFT 6
302 #define MLX5_GENEVE_CRITO_VAL(a) \
303 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
304 #define MLX5_GENEVE_RSVD_MASK 0x3F
305 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
307 * The length of the Geneve options fields, expressed in four byte multiples,
308 * not including the eight byte fixed tunnel.
310 #define MLX5_GENEVE_OPT_LEN_0 14
311 #define MLX5_GENEVE_OPT_LEN_1 63
313 enum mlx5_flow_drv_type {
316 MLX5_FLOW_TYPE_VERBS,
320 /* Matcher PRM representation */
321 struct mlx5_flow_dv_match_params {
323 /**< Size of match value. Do NOT split size and key! */
324 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
325 /**< Matcher value. This value is used as the mask or as a key. */
328 /* Matcher structure. */
329 struct mlx5_flow_dv_matcher {
330 LIST_ENTRY(mlx5_flow_dv_matcher) next;
331 /* Pointer to the next element. */
332 rte_atomic32_t refcnt; /**< Reference counter. */
333 void *matcher_object; /**< Pointer to DV matcher */
334 uint16_t crc; /**< CRC of key. */
335 uint16_t priority; /**< Priority of matcher. */
336 uint8_t egress; /**< Egress matcher. */
337 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
338 uint32_t group; /**< The matcher group. */
339 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
342 #define MLX5_ENCAP_MAX_LEN 132
344 /* Encap/decap resource structure. */
345 struct mlx5_flow_dv_encap_decap_resource {
346 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
347 /* Pointer to next element. */
348 rte_atomic32_t refcnt; /**< Reference counter. */
350 /**< Verbs encap/decap action object. */
351 uint8_t buf[MLX5_ENCAP_MAX_LEN];
353 uint8_t reformat_type;
355 uint64_t flags; /**< Flags for RDMA API. */
358 /* Tag resource structure. */
359 struct mlx5_flow_dv_tag_resource {
360 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
361 /* Pointer to next element. */
362 rte_atomic32_t refcnt; /**< Reference counter. */
364 /**< Verbs tag action object. */
365 uint32_t tag; /**< the tag value. */
369 * Number of modification commands.
370 * If extensive metadata registers are supported
371 * the maximal actions amount is 16 and 8 otherwise.
373 #define MLX5_MODIFY_NUM 16
374 #define MLX5_MODIFY_NUM_NO_MREG 8
376 /* Modify resource structure */
377 struct mlx5_flow_dv_modify_hdr_resource {
378 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
379 /* Pointer to next element. */
380 rte_atomic32_t refcnt; /**< Reference counter. */
381 struct ibv_flow_action *verbs_action;
382 /**< Verbs modify header action object. */
383 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
384 uint32_t actions_num; /**< Number of modification actions. */
385 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
386 /**< Modification actions. */
387 uint64_t flags; /**< Flags for RDMA API. */
390 /* Jump action resource structure. */
391 struct mlx5_flow_dv_jump_tbl_resource {
392 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
393 /* Pointer to next element. */
394 rte_atomic32_t refcnt; /**< Reference counter. */
395 void *action; /**< Pointer to the rdma core action. */
396 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
397 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
400 /* Port ID resource structure. */
401 struct mlx5_flow_dv_port_id_action_resource {
402 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
403 /* Pointer to next element. */
404 rte_atomic32_t refcnt; /**< Reference counter. */
406 /**< Verbs tag action object. */
407 uint32_t port_id; /**< Port ID value. */
410 /* Push VLAN action resource structure */
411 struct mlx5_flow_dv_push_vlan_action_resource {
412 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
413 /* Pointer to next element. */
414 rte_atomic32_t refcnt; /**< Reference counter. */
415 void *action; /**< Direct verbs action object. */
416 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
417 rte_be32_t vlan_tag; /**< VLAN tag value. */
421 * Max number of actions per DV flow.
422 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
423 * In rdma-core file providers/mlx5/verbs.c
425 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
427 /* DV flows structure. */
428 struct mlx5_flow_dv {
429 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
431 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
432 struct mlx5_flow_dv_match_params value;
433 /**< Holds the value that the packet is compared to. */
434 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
435 /**< Pointer to encap/decap resource in cache. */
436 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
437 /**< Pointer to modify header resource in cache. */
438 struct ibv_flow *flow; /**< Installed flow. */
439 struct mlx5_flow_dv_jump_tbl_resource *jump;
440 /**< Pointer to the jump action resource. */
441 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
442 /**< Pointer to port ID action resource. */
443 struct mlx5_vf_vlan vf_vlan;
444 /**< Structure for VF VLAN workaround. */
445 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
446 /**< Pointer to push VLAN action resource in cache. */
447 struct mlx5_flow_dv_tag_resource *tag_resource;
448 /**< pointer to the tag action. */
449 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
450 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
453 int actions_n; /**< number of actions. */
456 /* Verbs specification header. */
457 struct ibv_spec_header {
458 enum ibv_flow_spec_type type;
462 /** Handles information leading to a drop fate. */
463 struct mlx5_flow_verbs {
464 LIST_ENTRY(mlx5_flow_verbs) next;
465 unsigned int size; /**< Size of the attribute. */
467 struct ibv_flow_attr *attr;
468 /**< Pointer to the Specification buffer. */
469 uint8_t *specs; /**< Pointer to the specifications. */
471 struct ibv_flow *flow; /**< Verbs flow pointer. */
472 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
473 struct mlx5_vf_vlan vf_vlan;
474 /**< Structure for VF VLAN workaround. */
477 struct mlx5_flow_rss {
479 uint32_t queue_num; /**< Number of entries in @p queue. */
480 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
481 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
482 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
485 /** Device flow structure. */
487 LIST_ENTRY(mlx5_flow) next;
488 struct rte_flow *flow; /**< Pointer to the main flow. */
490 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
492 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
493 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
494 uint8_t ingress; /**< 1 if the flow is ingress. */
495 uint32_t group; /**< The group index. */
496 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
498 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
499 struct mlx5_flow_dv dv;
501 struct mlx5_flow_verbs verbs;
503 bool external; /**< true if the flow is created external to PMD. */
506 /* Flow structure. */
508 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
509 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
510 struct mlx5_flow_rss rss; /**< RSS context. */
511 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
512 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
513 /**< Device flows that are part of the flow. */
514 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
515 uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
518 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
519 const struct rte_flow_attr *attr,
520 const struct rte_flow_item items[],
521 const struct rte_flow_action actions[],
523 struct rte_flow_error *error);
524 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
525 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
526 const struct rte_flow_action actions[], struct rte_flow_error *error);
527 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
528 struct mlx5_flow *dev_flow,
529 const struct rte_flow_attr *attr,
530 const struct rte_flow_item items[],
531 const struct rte_flow_action actions[],
532 struct rte_flow_error *error);
533 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
534 struct rte_flow_error *error);
535 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
536 struct rte_flow *flow);
537 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
538 struct rte_flow *flow);
539 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
540 struct rte_flow *flow,
541 const struct rte_flow_action *actions,
543 struct rte_flow_error *error);
544 struct mlx5_flow_driver_ops {
545 mlx5_flow_validate_t validate;
546 mlx5_flow_prepare_t prepare;
547 mlx5_flow_translate_t translate;
548 mlx5_flow_apply_t apply;
549 mlx5_flow_remove_t remove;
550 mlx5_flow_destroy_t destroy;
551 mlx5_flow_query_t query;
555 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
556 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
557 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
558 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
562 struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(void);
563 void mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool);
564 uint32_t mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id);
565 uint32_t mlx5_flow_id_release(struct mlx5_flow_id_pool *pool,
567 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
568 bool external, uint32_t group, uint32_t *table,
569 struct rte_flow_error *error);
570 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
571 uint64_t layer_types,
572 uint64_t hash_fields);
573 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
574 uint32_t subpriority);
575 enum modify_reg mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
576 enum mlx5_feature_name feature,
578 struct rte_flow_error *error);
579 const struct rte_flow_action *mlx5_flow_find_action
580 (const struct rte_flow_action *actions,
581 enum rte_flow_action_type action);
582 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
583 const struct rte_flow_attr *attr,
584 struct rte_flow_error *error);
585 int mlx5_flow_validate_action_drop(uint64_t action_flags,
586 const struct rte_flow_attr *attr,
587 struct rte_flow_error *error);
588 int mlx5_flow_validate_action_flag(uint64_t action_flags,
589 const struct rte_flow_attr *attr,
590 struct rte_flow_error *error);
591 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
592 uint64_t action_flags,
593 const struct rte_flow_attr *attr,
594 struct rte_flow_error *error);
595 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
596 uint64_t action_flags,
597 struct rte_eth_dev *dev,
598 const struct rte_flow_attr *attr,
599 struct rte_flow_error *error);
600 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
601 uint64_t action_flags,
602 struct rte_eth_dev *dev,
603 const struct rte_flow_attr *attr,
605 struct rte_flow_error *error);
606 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
607 const struct rte_flow_attr *attributes,
608 struct rte_flow_error *error);
609 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
611 const uint8_t *nic_mask,
613 struct rte_flow_error *error);
614 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
616 struct rte_flow_error *error);
617 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
619 uint8_t target_protocol,
620 struct rte_flow_error *error);
621 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
623 const struct rte_flow_item *gre_item,
624 struct rte_flow_error *error);
625 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
629 const struct rte_flow_item_ipv4 *acc_mask,
630 struct rte_flow_error *error);
631 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
635 const struct rte_flow_item_ipv6 *acc_mask,
636 struct rte_flow_error *error);
637 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
638 const struct rte_flow_item *item,
641 struct rte_flow_error *error);
642 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
644 uint8_t target_protocol,
645 const struct rte_flow_item_tcp *flow_mask,
646 struct rte_flow_error *error);
647 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
649 uint8_t target_protocol,
650 struct rte_flow_error *error);
651 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
653 struct rte_eth_dev *dev,
654 struct rte_flow_error *error);
655 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
657 struct rte_flow_error *error);
658 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
660 struct rte_eth_dev *dev,
661 struct rte_flow_error *error);
662 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
664 uint8_t target_protocol,
665 struct rte_flow_error *error);
666 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
668 uint8_t target_protocol,
669 struct rte_flow_error *error);
670 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
672 uint8_t target_protocol,
673 struct rte_flow_error *error);
674 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
676 struct rte_eth_dev *dev,
677 struct rte_flow_error *error);
678 #endif /* RTE_PMD_MLX5_FLOW_H_ */