drivers/net/mlx5/mlx5_flow_age.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4 #include <mlx5_prm.h>
   5 #include <rte_malloc.h>
   6 #include <rte_cycles.h>
   7 #include <rte_eal_paging.h>
   8
   9 #include <mlx5_malloc.h>
  10 #include <mlx5_common_os.h>
  11 #include <mlx5_common_devx.h>
  12
  13 #include "mlx5.h"
  14 #include "mlx5_flow.h"
  15
  16
  17 /**
  18  * Destroy Completion Queue used for ASO access.
  19  *
  20  * @param[in] cq
  21  *   ASO CQ to destroy.
  22  */
  23 static void
  24 mlx5_aso_cq_destroy(struct mlx5_aso_cq *cq)
  25 {
  26         if (cq->cq_obj.cq)
  27                 mlx5_devx_cq_destroy(&cq->cq_obj);
  28         memset(cq, 0, sizeof(*cq));
  29 }
  30
  31 /**
  32  * Create Completion Queue used for ASO access.
  33  *
  34  * @param[in] ctx
  35  *   Context returned from mlx5 open_device() glue function.
  36  * @param[in/out] cq
  37  *   Pointer to CQ to create.
  38  * @param[in] log_desc_n
  39  *   Log of number of descriptors in queue.
  40  * @param[in] socket
  41  *   Socket to use for allocation.
  42  * @param[in] uar_page_id
  43  *   UAR page ID to use.
  44  *
  45  * @return
  46  *   0 on success, a negative errno value otherwise and rte_errno is set.
  47  */
  48 static int
  49 mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n,
  50                    int socket, int uar_page_id)
  51 {
  52         struct mlx5_devx_cq_attr attr = {
  53                 .uar_page_id = uar_page_id,
  54         };
  55
  56         cq->log_desc_n = log_desc_n;
  57         cq->cq_ci = 0;
  58         return mlx5_devx_cq_create(ctx, &cq->cq_obj, log_desc_n, &attr, socket);
  59 }
  60
  61 /**
  62  * Free MR resources.
  63  *
  64  * @param[in] mr
  65  *   MR to free.
  66  */
  67 static void
  68 mlx5_aso_devx_dereg_mr(struct mlx5_aso_devx_mr *mr)
  69 {
  70         claim_zero(mlx5_devx_cmd_destroy(mr->mkey));
  71         if (!mr->is_indirect && mr->umem)
  72                 claim_zero(mlx5_glue->devx_umem_dereg(mr->umem));
  73         mlx5_free(mr->buf);
  74         memset(mr, 0, sizeof(*mr));
  75 }
  76
  77 /**
  78  * Register Memory Region.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param[in] length
  83  *   Size of MR buffer.
  84  * @param[in/out] mr
  85  *   Pointer to MR to create.
  86  * @param[in] socket
  87  *   Socket to use for allocation.
  88  * @param[in] pdn
  89  *   Protection Domain number to use.
  90  *
  91  * @return
  92  *   0 on success, a negative errno value otherwise and rte_errno is set.
  93  */
  94 static int
  95 mlx5_aso_devx_reg_mr(void *ctx, size_t length, struct mlx5_aso_devx_mr *mr,
  96                      int socket, int pdn)
  97 {
  98         struct mlx5_devx_mkey_attr mkey_attr;
  99
 100         mr->buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, length, 4096,
 101                               socket);
 102         if (!mr->buf) {
 103                 DRV_LOG(ERR, "Failed to create ASO bits mem for MR by Devx.");
 104                 return -1;
 105         }
 106         mr->umem = mlx5_os_umem_reg(ctx, mr->buf, length,
 107                                                  IBV_ACCESS_LOCAL_WRITE);
 108         if (!mr->umem) {
 109                 DRV_LOG(ERR, "Failed to register Umem for MR by Devx.");
 110                 goto error;
 111         }
 112         mkey_attr.addr = (uintptr_t)mr->buf;
 113         mkey_attr.size = length;
 114         mkey_attr.umem_id = mlx5_os_get_umem_id(mr->umem);
 115         mkey_attr.pd = pdn;
 116         mkey_attr.pg_access = 1;
 117         mkey_attr.klm_array = NULL;
 118         mkey_attr.klm_num = 0;
 119         mkey_attr.relaxed_ordering_read = 0;
 120         mkey_attr.relaxed_ordering_write = 0;
 121         mr->mkey = mlx5_devx_cmd_mkey_create(ctx, &mkey_attr);
 122         if (!mr->mkey) {
 123                 DRV_LOG(ERR, "Failed to create direct Mkey.");
 124                 goto error;
 125         }
 126         mr->length = length;
 127         mr->is_indirect = false;
 128         return 0;
 129 error:
 130         if (mr->umem)
 131                 claim_zero(mlx5_glue->devx_umem_dereg(mr->umem));
 132         mlx5_free(mr->buf);
 133         return -1;
 134 }
 135
 136 /**
 137  * Destroy Send Queue used for ASO access.
 138  *
 139  * @param[in] sq
 140  *   ASO SQ to destroy.
 141  */
 142 static void
 143 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
 144 {
 145         mlx5_devx_sq_destroy(&sq->sq_obj);
 146         mlx5_aso_cq_destroy(&sq->cq);
 147         mlx5_aso_devx_dereg_mr(&sq->mr);
 148         memset(sq, 0, sizeof(*sq));
 149 }
 150
 151 /**
 152  * Initialize Send Queue used for ASO access.
 153  *
 154  * @param[in] sq
 155  *   ASO SQ to initialize.
 156  */
 157 static void
 158 mlx5_aso_init_sq(struct mlx5_aso_sq *sq)
 159 {
 160         volatile struct mlx5_aso_wqe *restrict wqe;
 161         int i;
 162         int size = 1 << sq->log_desc_n;
 163         uint64_t addr;
 164
 165         /* All the next fields state should stay constant. */
 166         for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
 167                 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
 168                                                           (sizeof(*wqe) >> 4));
 169                 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.mkey->id);
 170                 addr = (uint64_t)((uint64_t *)sq->mr.buf + i *
 171                                             MLX5_ASO_AGE_ACTIONS_PER_POOL / 64);
 172                 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
 173                 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
 174                 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
 175                         (0u |
 176                          (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
 177                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
 178                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
 179                          (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
 180                 wqe->aso_cseg.data_mask = RTE_BE64(UINT64_MAX);
 181         }
 182 }
 183
 184 /**
 185  * Create Send Queue used for ASO access.
 186  *
 187  * @param[in] ctx
 188  *   Context returned from mlx5 open_device() glue function.
 189  * @param[in/out] sq
 190  *   Pointer to SQ to create.
 191  * @param[in] socket
 192  *   Socket to use for allocation.
 193  * @param[in] uar
 194  *   User Access Region object.
 195  * @param[in] pdn
 196  *   Protection Domain number to use.
 197  * @param[in] log_desc_n
 198  *   Log of number of descriptors in queue.
 199  *
 200  * @return
 201  *   0 on success, a negative errno value otherwise and rte_errno is set.
 202  */
 203 static int
 204 mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,
 205                    void *uar, uint32_t pdn,  uint16_t log_desc_n,
 206                    uint32_t ts_format)
 207 {
 208         struct mlx5_devx_create_sq_attr attr = {
 209                 .user_index = 0xFFFF,
 210                 .wq_attr = (struct mlx5_devx_wq_attr){
 211                         .pd = pdn,
 212                         .uar_page = mlx5_os_get_devx_uar_page_id(uar),
 213                 },
 214                 .ts_format = mlx5_ts_format_conv(ts_format),
 215         };
 216         struct mlx5_devx_modify_sq_attr modify_attr = {
 217                 .state = MLX5_SQC_STATE_RDY,
 218         };
 219         uint32_t sq_desc_n = 1 << log_desc_n;
 220         uint16_t log_wqbb_n;
 221         int ret;
 222
 223         if (mlx5_aso_devx_reg_mr(ctx, (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *
 224                                  sq_desc_n, &sq->mr, socket, pdn))
 225                 return -1;
 226         if (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, socket,
 227                                mlx5_os_get_devx_uar_page_id(uar)))
 228                 goto error;
 229         sq->log_desc_n = log_desc_n;
 230         attr.cqn = sq->cq.cq_obj.cq->id;
 231         /* for mlx5_aso_wqe that is twice the size of mlx5_wqe */
 232         log_wqbb_n = log_desc_n + 1;
 233         ret = mlx5_devx_sq_create(ctx, &sq->sq_obj, log_wqbb_n, &attr, socket);
 234         if (ret) {
 235                 DRV_LOG(ERR, "Can't create SQ object.");
 236                 rte_errno = ENOMEM;
 237                 goto error;
 238         }
 239         ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);
 240         if (ret) {
 241                 DRV_LOG(ERR, "Can't change SQ state to ready.");
 242                 rte_errno = ENOMEM;
 243                 goto error;
 244         }
 245         sq->pi = 0;
 246         sq->head = 0;
 247         sq->tail = 0;
 248         sq->sqn = sq->sq_obj.sq->id;
 249         sq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar);
 250         mlx5_aso_init_sq(sq);
 251         return 0;
 252 error:
 253         mlx5_aso_destroy_sq(sq);
 254         return -1;
 255 }
 256
 257 /**
 258  * API to create and initialize Send Queue used for ASO access.
 259  *
 260  * @param[in] sh
 261  *   Pointer to shared device context.
 262  *
 263  * @return
 264  *   0 on success, a negative errno value otherwise and rte_errno is set.
 265  */
 266 int
 267 mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh)
 268 {
 269         return mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,
 270                                   sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
 271                                   sh->sq_ts_format);
 272 }
 273
 274 /**
 275  * API to destroy Send Queue used for ASO access.
 276  *
 277  * @param[in] sh
 278  *   Pointer to shared device context.
 279  */
 280 void
 281 mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh)
 282 {
 283         mlx5_aso_destroy_sq(&sh->aso_age_mng->aso_sq);
 284 }
 285
 286 /**
 287  * Write a burst of WQEs to ASO SQ.
 288  *
 289  * @param[in] mng
 290  *   ASO management data, contains the SQ.
 291  * @param[in] n
 292  *   Index of the last valid pool.
 293  *
 294  * @return
 295  *   Number of WQEs in burst.
 296  */
 297 static uint16_t
 298 mlx5_aso_sq_enqueue_burst(struct mlx5_aso_age_mng *mng, uint16_t n)
 299 {
 300         volatile struct mlx5_aso_wqe *wqe;
 301         struct mlx5_aso_sq *sq = &mng->aso_sq;
 302         struct mlx5_aso_age_pool *pool;
 303         uint16_t size = 1 << sq->log_desc_n;
 304         uint16_t mask = size - 1;
 305         uint16_t max;
 306         uint16_t start_head = sq->head;
 307
 308         max = RTE_MIN(size - (uint16_t)(sq->head - sq->tail), n - sq->next);
 309         if (unlikely(!max))
 310                 return 0;
 311         sq->elts[start_head & mask].burst_size = max;
 312         do {
 313                 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
 314                 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
 315                 /* Fill next WQE. */
 316                 rte_spinlock_lock(&mng->resize_sl);
 317                 pool = mng->pools[sq->next];
 318                 rte_spinlock_unlock(&mng->resize_sl);
 319                 sq->elts[sq->head & mask].pool = pool;
 320                 wqe->general_cseg.misc =
 321                                 rte_cpu_to_be_32(((struct mlx5_devx_obj *)
 322                                                  (pool->flow_hit_aso_obj))->id);
 323                 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
 324                                                          MLX5_COMP_MODE_OFFSET);
 325                 wqe->general_cseg.opcode = rte_cpu_to_be_32
 326                                                 (MLX5_OPCODE_ACCESS_ASO |
 327                                                  (ASO_OPC_MOD_FLOW_HIT <<
 328                                                   WQE_CSEG_OPC_MOD_OFFSET) |
 329                                                  (sq->pi <<
 330                                                   WQE_CSEG_WQE_INDEX_OFFSET));
 331                 sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
 332                 sq->head++;
 333                 sq->next++;
 334                 max--;
 335         } while (max);
 336         wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 337                                                          MLX5_COMP_MODE_OFFSET);
 338         rte_io_wmb();
 339         sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
 340         rte_wmb();
 341         *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/
 342         rte_wmb();
 343         return sq->elts[start_head & mask].burst_size;
 344 }
 345
 346 /**
 347  * Debug utility function. Dump contents of error CQE and WQE.
 348  *
 349  * @param[in] cqe
 350  *   Error CQE to dump.
 351  * @param[in] wqe
 352  *   Error WQE to dump.
 353  */
 354 static void
 355 mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
 356 {
 357         int i;
 358
 359         DRV_LOG(ERR, "Error cqe:");
 360         for (i = 0; i < 16; i += 4)
 361                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 362                         cqe[i + 2], cqe[i + 3]);
 363         DRV_LOG(ERR, "\nError wqe:");
 364         for (i = 0; i < (int)sizeof(struct mlx5_aso_wqe) / 4; i += 4)
 365                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 366                         wqe[i + 2], wqe[i + 3]);
 367 }
 368
 369 /**
 370  * Handle case of error CQE.
 371  *
 372  * @param[in] sq
 373  *   ASO SQ to use.
 374  */
 375 static void
 376 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
 377 {
 378         struct mlx5_aso_cq *cq = &sq->cq;
 379         uint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1);
 380         volatile struct mlx5_err_cqe *cqe =
 381                         (volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx];
 382
 383         cq->errors++;
 384         idx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);
 385         mlx5_aso_dump_err_objs((volatile uint32_t *)cqe,
 386                                (volatile uint32_t *)&sq->sq_obj.aso_wqes[idx]);
 387 }
 388
 389 /**
 390  * Update ASO objects upon completion.
 391  *
 392  * @param[in] sh
 393  *   Shared device context.
 394  * @param[in] n
 395  *   Number of completed ASO objects.
 396  */
 397 static void
 398 mlx5_aso_age_action_update(struct mlx5_dev_ctx_shared *sh, uint16_t n)
 399 {
 400         struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
 401         struct mlx5_aso_sq *sq = &mng->aso_sq;
 402         struct mlx5_age_info *age_info;
 403         const uint16_t size = 1 << sq->log_desc_n;
 404         const uint16_t mask = size - 1;
 405         const uint64_t curr = MLX5_CURR_TIME_SEC;
 406         uint16_t expected = AGE_CANDIDATE;
 407         uint16_t i;
 408
 409         for (i = 0; i < n; ++i) {
 410                 uint16_t idx = (sq->tail + i) & mask;
 411                 struct mlx5_aso_age_pool *pool = sq->elts[idx].pool;
 412                 uint64_t diff = curr - pool->time_of_last_age_check;
 413                 uint64_t *addr = sq->mr.buf;
 414                 int j;
 415
 416                 addr += idx * MLX5_ASO_AGE_ACTIONS_PER_POOL / 64;
 417                 pool->time_of_last_age_check = curr;
 418                 for (j = 0; j < MLX5_ASO_AGE_ACTIONS_PER_POOL; j++) {
 419                         struct mlx5_aso_age_action *act = &pool->actions[j];
 420                         struct mlx5_age_param *ap = &act->age_params;
 421                         uint8_t byte;
 422                         uint8_t offset;
 423                         uint8_t *u8addr;
 424                         uint8_t hit;
 425
 426                         if (__atomic_load_n(&ap->state, __ATOMIC_RELAXED) !=
 427                                             AGE_CANDIDATE)
 428                                 continue;
 429                         byte = 63 - (j / 8);
 430                         offset = j % 8;
 431                         u8addr = (uint8_t *)addr;
 432                         hit = (u8addr[byte] >> offset) & 0x1;
 433                         if (hit) {
 434                                 __atomic_store_n(&ap->sec_since_last_hit, 0,
 435                                                  __ATOMIC_RELAXED);
 436                         } else {
 437                                 struct mlx5_priv *priv;
 438
 439                                 __atomic_fetch_add(&ap->sec_since_last_hit,
 440                                                    diff, __ATOMIC_RELAXED);
 441                                 /* If timeout passed add to aged-out list. */
 442                                 if (ap->sec_since_last_hit <= ap->timeout)
 443                                         continue;
 444                                 priv =
 445                                 rte_eth_devices[ap->port_id].data->dev_private;
 446                                 age_info = GET_PORT_AGE_INFO(priv);
 447                                 rte_spinlock_lock(&age_info->aged_sl);
 448                                 if (__atomic_compare_exchange_n(&ap->state,
 449                                                                 &expected,
 450                                                                 AGE_TMOUT,
 451                                                                 false,
 452                                                                __ATOMIC_RELAXED,
 453                                                             __ATOMIC_RELAXED)) {
 454                                         LIST_INSERT_HEAD(&age_info->aged_aso,
 455                                                          act, next);
 456                                         MLX5_AGE_SET(age_info,
 457                                                      MLX5_AGE_EVENT_NEW);
 458                                 }
 459                                 rte_spinlock_unlock(&age_info->aged_sl);
 460                         }
 461                 }
 462         }
 463         mlx5_age_event_prepare(sh);
 464 }
 465
 466 /**
 467  * Handle completions from WQEs sent to ASO SQ.
 468  *
 469  * @param[in] sh
 470  *   Shared device context.
 471  *
 472  * @return
 473  *   Number of CQEs handled.
 474  */
 475 static uint16_t
 476 mlx5_aso_completion_handle(struct mlx5_dev_ctx_shared *sh)
 477 {
 478         struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
 479         struct mlx5_aso_sq *sq = &mng->aso_sq;
 480         struct mlx5_aso_cq *cq = &sq->cq;
 481         volatile struct mlx5_cqe *restrict cqe;
 482         const unsigned int cq_size = 1 << cq->log_desc_n;
 483         const unsigned int mask = cq_size - 1;
 484         uint32_t idx;
 485         uint32_t next_idx = cq->cq_ci & mask;
 486         const uint16_t max = (uint16_t)(sq->head - sq->tail);
 487         uint16_t i = 0;
 488         int ret;
 489         if (unlikely(!max))
 490                 return 0;
 491         do {
 492                 idx = next_idx;
 493                 next_idx = (cq->cq_ci + 1) & mask;
 494                 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
 495                 cqe = &cq->cq_obj.cqes[idx];
 496                 ret = check_cqe(cqe, cq_size, cq->cq_ci);
 497                 /*
 498                  * Be sure owner read is done before any other cookie field or
 499                  * opaque field.
 500                  */
 501                 rte_io_rmb();
 502                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 503                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 504                                 break;
 505                         mlx5_aso_cqe_err_handle(sq);
 506                 } else {
 507                         i += sq->elts[(sq->tail + i) & mask].burst_size;
 508                 }
 509                 cq->cq_ci++;
 510         } while (1);
 511         if (likely(i)) {
 512                 mlx5_aso_age_action_update(sh, i);
 513                 sq->tail += i;
 514                 rte_io_wmb();
 515                 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
 516         }
 517         return i;
 518 }
 519
 520 /**
 521  * Periodically read CQEs and send WQEs to ASO SQ.
 522  *
 523  * @param[in] arg
 524  *   Shared device context containing the ASO SQ.
 525  */
 526 static void
 527 mlx5_flow_aso_alarm(void *arg)
 528 {
 529         struct mlx5_dev_ctx_shared *sh = arg;
 530         struct mlx5_aso_sq *sq = &sh->aso_age_mng->aso_sq;
 531         uint32_t us = 100u;
 532         uint16_t n;
 533
 534         rte_spinlock_lock(&sh->aso_age_mng->resize_sl);
 535         n = sh->aso_age_mng->next;
 536         rte_spinlock_unlock(&sh->aso_age_mng->resize_sl);
 537         mlx5_aso_completion_handle(sh);
 538         if (sq->next == n) {
 539                 /* End of loop: wait 1 second. */
 540                 us = US_PER_S;
 541                 sq->next = 0;
 542         }
 543         mlx5_aso_sq_enqueue_burst(sh->aso_age_mng, n);
 544         if (rte_eal_alarm_set(us, mlx5_flow_aso_alarm, sh))
 545                 DRV_LOG(ERR, "Cannot reinitialize aso alarm.");
 546 }
 547
 548 /**
 549  * API to start ASO access using ASO SQ.
 550  *
 551  * @param[in] sh
 552  *   Pointer to shared device context.
 553  *
 554  * @return
 555  *   0 on success, a negative errno value otherwise and rte_errno is set.
 556  */
 557 int
 558 mlx5_aso_queue_start(struct mlx5_dev_ctx_shared *sh)
 559 {
 560         if (rte_eal_alarm_set(US_PER_S, mlx5_flow_aso_alarm, sh)) {
 561                 DRV_LOG(ERR, "Cannot reinitialize ASO age alarm.");
 562                 return -rte_errno;
 563         }
 564         return 0;
 565 }
 566
 567 /**
 568  * API to stop ASO access using ASO SQ.
 569  *
 570  * @param[in] sh
 571  *   Pointer to shared device context.
 572  *
 573  * @return
 574  *   0 on success, a negative errno value otherwise and rte_errno is set.
 575  */
 576 int
 577 mlx5_aso_queue_stop(struct mlx5_dev_ctx_shared *sh)
 578 {
 579         int retries = 1024;
 580
 581         if (!sh->aso_age_mng->aso_sq.sq_obj.sq)
 582                 return -EINVAL;
 583         rte_errno = 0;
 584         while (--retries) {
 585                 rte_eal_alarm_cancel(mlx5_flow_aso_alarm, sh);
 586                 if (rte_errno != EINPROGRESS)
 587                         break;
 588                 rte_pause();
 589         }
 590         return -rte_errno;
 591 }