1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
5 #include <rte_malloc.h>
6 #include <rte_cycles.h>
7 #include <rte_eal_paging.h>
9 #include <mlx5_malloc.h>
10 #include <mlx5_common_os.h>
11 #include <mlx5_common_devx.h>
14 #include "mlx5_flow.h"
17 * Destroy Completion Queue used for ASO access.
23 mlx5_aso_cq_destroy(struct mlx5_aso_cq *cq)
26 mlx5_devx_cq_destroy(&cq->cq_obj);
27 memset(cq, 0, sizeof(*cq));
31 * Create Completion Queue used for ASO access.
34 * Context returned from mlx5 open_device() glue function.
36 * Pointer to CQ to create.
37 * @param[in] log_desc_n
38 * Log of number of descriptors in queue.
40 * Socket to use for allocation.
41 * @param[in] uar_page_id
45 * 0 on success, a negative errno value otherwise and rte_errno is set.
48 mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n,
49 int socket, int uar_page_id)
51 struct mlx5_devx_cq_attr attr = {
52 .uar_page_id = uar_page_id,
55 cq->log_desc_n = log_desc_n;
57 return mlx5_devx_cq_create(ctx, &cq->cq_obj, log_desc_n, &attr, socket);
64 * Pointer to shared device context.
69 mlx5_aso_dereg_mr(struct mlx5_dev_ctx_shared *sh, struct mlx5_pmd_mr *mr)
71 void *addr = mr->addr;
73 sh->share_cache.dereg_mr_cb(mr);
75 memset(mr, 0, sizeof(*mr));
79 * Register Memory Region.
82 * Pointer to shared device context.
86 * Pointer to MR to create.
88 * Socket to use for allocation.
91 * 0 on success, a negative errno value otherwise and rte_errno is set.
94 mlx5_aso_reg_mr(struct mlx5_dev_ctx_shared *sh, size_t length,
95 struct mlx5_pmd_mr *mr, int socket)
100 mr->addr = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, length, 4096,
103 DRV_LOG(ERR, "Failed to create ASO bits mem for MR.");
106 ret = sh->share_cache.reg_mr_cb(sh->pd, mr->addr, length, mr);
108 DRV_LOG(ERR, "Failed to create direct Mkey.");
116 * Destroy Send Queue used for ASO access.
122 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
124 mlx5_devx_sq_destroy(&sq->sq_obj);
125 mlx5_aso_cq_destroy(&sq->cq);
126 memset(sq, 0, sizeof(*sq));
130 * Initialize Send Queue used for ASO access.
133 * ASO SQ to initialize.
136 mlx5_aso_age_init_sq(struct mlx5_aso_sq *sq)
138 volatile struct mlx5_aso_wqe *restrict wqe;
140 int size = 1 << sq->log_desc_n;
143 /* All the next fields state should stay constant. */
144 for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
145 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
146 (sizeof(*wqe) >> 4));
147 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.lkey);
148 addr = (uint64_t)((uint64_t *)sq->mr.addr + i *
149 MLX5_ASO_AGE_ACTIONS_PER_POOL / 64);
150 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
151 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
152 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
154 (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
155 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
156 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
157 (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
158 wqe->aso_cseg.data_mask = RTE_BE64(UINT64_MAX);
163 * Initialize Send Queue used for ASO flow meter access.
166 * ASO SQ to initialize.
169 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)
171 volatile struct mlx5_aso_wqe *restrict wqe;
173 int size = 1 << sq->log_desc_n;
175 /* All the next fields state should stay constant. */
176 for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
177 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
178 (sizeof(*wqe) >> 4));
179 wqe->aso_cseg.operand_masks = RTE_BE32(0u |
180 (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
181 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
182 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
183 (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
184 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
185 MLX5_COMP_MODE_OFFSET);
190 * Initialize Send Queue used for ASO connection tracking.
193 * ASO SQ to initialize.
196 mlx5_aso_ct_init_sq(struct mlx5_aso_sq *sq)
198 volatile struct mlx5_aso_wqe *restrict wqe;
200 int size = 1 << sq->log_desc_n;
203 /* All the next fields state should stay constant. */
204 for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
205 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
206 (sizeof(*wqe) >> 4));
207 /* One unique MR for the query data. */
208 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.lkey);
209 /* Magic number 64 represents the length of a ASO CT obj. */
210 addr = (uint64_t)((uintptr_t)sq->mr.addr + i * 64);
211 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
212 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
214 * The values of operand_masks are different for modify
216 * And data_mask may be different for each modification. In
217 * query, it could be zero and ignored.
218 * CQE generation is always needed, in order to decide when
219 * it is available to create the flow or read the data.
221 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
222 MLX5_COMP_MODE_OFFSET);
227 * Create Send Queue used for ASO access.
230 * Context returned from mlx5 open_device() glue function.
232 * Pointer to SQ to create.
234 * Socket to use for allocation.
236 * User Access Region object.
238 * Protection Domain number to use.
239 * @param[in] log_desc_n
240 * Log of number of descriptors in queue.
241 * @param[in] ts_format
242 * timestamp format supported by the queue.
245 * 0 on success, a negative errno value otherwise and rte_errno is set.
248 mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket, void *uar,
249 uint32_t pdn, uint16_t log_desc_n, uint32_t ts_format)
251 struct mlx5_devx_create_sq_attr attr = {
252 .user_index = 0xFFFF,
253 .wq_attr = (struct mlx5_devx_wq_attr){
255 .uar_page = mlx5_os_get_devx_uar_page_id(uar),
257 .ts_format = mlx5_ts_format_conv(ts_format),
259 struct mlx5_devx_modify_sq_attr modify_attr = {
260 .state = MLX5_SQC_STATE_RDY,
265 if (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, socket,
266 mlx5_os_get_devx_uar_page_id(uar)))
268 sq->log_desc_n = log_desc_n;
269 attr.cqn = sq->cq.cq_obj.cq->id;
270 /* for mlx5_aso_wqe that is twice the size of mlx5_wqe */
271 log_wqbb_n = log_desc_n + 1;
272 ret = mlx5_devx_sq_create(ctx, &sq->sq_obj, log_wqbb_n, &attr, socket);
274 DRV_LOG(ERR, "Can't create SQ object.");
278 ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);
280 DRV_LOG(ERR, "Can't change SQ state to ready.");
287 sq->sqn = sq->sq_obj.sq->id;
288 sq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar);
289 rte_spinlock_init(&sq->sqsl);
292 mlx5_aso_destroy_sq(sq);
297 * API to create and initialize Send Queue used for ASO access.
300 * Pointer to shared device context.
301 * @param[in] aso_opc_mod
302 * Mode of ASO feature.
305 * 0 on success, a negative errno value otherwise and rte_errno is set.
308 mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
309 enum mlx5_access_aso_opc_mod aso_opc_mod)
311 uint32_t sq_desc_n = 1 << MLX5_ASO_QUEUE_LOG_DESC;
312 struct mlx5_common_device *cdev = sh->cdev;
314 switch (aso_opc_mod) {
315 case ASO_OPC_MOD_FLOW_HIT:
316 if (mlx5_aso_reg_mr(sh, (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *
317 sq_desc_n, &sh->aso_age_mng->aso_sq.mr, 0))
319 if (mlx5_aso_sq_create(cdev->ctx, &sh->aso_age_mng->aso_sq, 0,
320 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
322 mlx5_aso_dereg_mr(sh, &sh->aso_age_mng->aso_sq.mr);
325 mlx5_aso_age_init_sq(&sh->aso_age_mng->aso_sq);
327 case ASO_OPC_MOD_POLICER:
328 if (mlx5_aso_sq_create(cdev->ctx, &sh->mtrmng->pools_mng.sq, 0,
329 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
332 mlx5_aso_mtr_init_sq(&sh->mtrmng->pools_mng.sq);
334 case ASO_OPC_MOD_CONNECTION_TRACKING:
335 /* 64B per object for query. */
336 if (mlx5_aso_reg_mr(sh, 64 * sq_desc_n,
337 &sh->ct_mng->aso_sq.mr, 0))
339 if (mlx5_aso_sq_create(cdev->ctx, &sh->ct_mng->aso_sq, 0,
340 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
342 mlx5_aso_dereg_mr(sh, &sh->ct_mng->aso_sq.mr);
345 mlx5_aso_ct_init_sq(&sh->ct_mng->aso_sq);
348 DRV_LOG(ERR, "Unknown ASO operation mode");
355 * API to destroy Send Queue used for ASO access.
358 * Pointer to shared device context.
359 * @param[in] aso_opc_mod
360 * Mode of ASO feature.
363 mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
364 enum mlx5_access_aso_opc_mod aso_opc_mod)
366 struct mlx5_aso_sq *sq;
368 switch (aso_opc_mod) {
369 case ASO_OPC_MOD_FLOW_HIT:
370 mlx5_aso_dereg_mr(sh, &sh->aso_age_mng->aso_sq.mr);
371 sq = &sh->aso_age_mng->aso_sq;
373 case ASO_OPC_MOD_POLICER:
374 sq = &sh->mtrmng->pools_mng.sq;
376 case ASO_OPC_MOD_CONNECTION_TRACKING:
377 mlx5_aso_dereg_mr(sh, &sh->ct_mng->aso_sq.mr);
378 sq = &sh->ct_mng->aso_sq;
381 DRV_LOG(ERR, "Unknown ASO operation mode");
384 mlx5_aso_destroy_sq(sq);
388 * Write a burst of WQEs to ASO SQ.
391 * ASO management data, contains the SQ.
393 * Index of the last valid pool.
396 * Number of WQEs in burst.
399 mlx5_aso_sq_enqueue_burst(struct mlx5_aso_age_mng *mng, uint16_t n)
401 volatile struct mlx5_aso_wqe *wqe;
402 struct mlx5_aso_sq *sq = &mng->aso_sq;
403 struct mlx5_aso_age_pool *pool;
404 uint16_t size = 1 << sq->log_desc_n;
405 uint16_t mask = size - 1;
407 uint16_t start_head = sq->head;
409 max = RTE_MIN(size - (uint16_t)(sq->head - sq->tail), n - sq->next);
412 sq->elts[start_head & mask].burst_size = max;
414 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
415 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
417 rte_spinlock_lock(&mng->resize_sl);
418 pool = mng->pools[sq->next];
419 rte_spinlock_unlock(&mng->resize_sl);
420 sq->elts[sq->head & mask].pool = pool;
421 wqe->general_cseg.misc =
422 rte_cpu_to_be_32(((struct mlx5_devx_obj *)
423 (pool->flow_hit_aso_obj))->id);
424 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
425 MLX5_COMP_MODE_OFFSET);
426 wqe->general_cseg.opcode = rte_cpu_to_be_32
427 (MLX5_OPCODE_ACCESS_ASO |
428 (ASO_OPC_MOD_FLOW_HIT <<
429 WQE_CSEG_OPC_MOD_OFFSET) |
431 WQE_CSEG_WQE_INDEX_OFFSET));
432 sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
437 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
438 MLX5_COMP_MODE_OFFSET);
440 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
442 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/
444 return sq->elts[start_head & mask].burst_size;
448 * Debug utility function. Dump contents of error CQE and WQE.
456 mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
460 DRV_LOG(ERR, "Error cqe:");
461 for (i = 0; i < 16; i += 4)
462 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
463 cqe[i + 2], cqe[i + 3]);
464 DRV_LOG(ERR, "\nError wqe:");
465 for (i = 0; i < (int)sizeof(struct mlx5_aso_wqe) / 4; i += 4)
466 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
467 wqe[i + 2], wqe[i + 3]);
471 * Handle case of error CQE.
477 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
479 struct mlx5_aso_cq *cq = &sq->cq;
480 uint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1);
481 volatile struct mlx5_err_cqe *cqe =
482 (volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx];
485 idx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);
486 mlx5_aso_dump_err_objs((volatile uint32_t *)cqe,
487 (volatile uint32_t *)&sq->sq_obj.aso_wqes[idx]);
491 * Update ASO objects upon completion.
494 * Shared device context.
496 * Number of completed ASO objects.
499 mlx5_aso_age_action_update(struct mlx5_dev_ctx_shared *sh, uint16_t n)
501 struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
502 struct mlx5_aso_sq *sq = &mng->aso_sq;
503 struct mlx5_age_info *age_info;
504 const uint16_t size = 1 << sq->log_desc_n;
505 const uint16_t mask = size - 1;
506 const uint64_t curr = MLX5_CURR_TIME_SEC;
507 uint16_t expected = AGE_CANDIDATE;
510 for (i = 0; i < n; ++i) {
511 uint16_t idx = (sq->tail + i) & mask;
512 struct mlx5_aso_age_pool *pool = sq->elts[idx].pool;
513 uint64_t diff = curr - pool->time_of_last_age_check;
514 uint64_t *addr = sq->mr.addr;
517 addr += idx * MLX5_ASO_AGE_ACTIONS_PER_POOL / 64;
518 pool->time_of_last_age_check = curr;
519 for (j = 0; j < MLX5_ASO_AGE_ACTIONS_PER_POOL; j++) {
520 struct mlx5_aso_age_action *act = &pool->actions[j];
521 struct mlx5_age_param *ap = &act->age_params;
527 if (__atomic_load_n(&ap->state, __ATOMIC_RELAXED) !=
532 u8addr = (uint8_t *)addr;
533 hit = (u8addr[byte] >> offset) & 0x1;
535 __atomic_store_n(&ap->sec_since_last_hit, 0,
538 struct mlx5_priv *priv;
540 __atomic_fetch_add(&ap->sec_since_last_hit,
541 diff, __ATOMIC_RELAXED);
542 /* If timeout passed add to aged-out list. */
543 if (ap->sec_since_last_hit <= ap->timeout)
546 rte_eth_devices[ap->port_id].data->dev_private;
547 age_info = GET_PORT_AGE_INFO(priv);
548 rte_spinlock_lock(&age_info->aged_sl);
549 if (__atomic_compare_exchange_n(&ap->state,
555 LIST_INSERT_HEAD(&age_info->aged_aso,
557 MLX5_AGE_SET(age_info,
560 rte_spinlock_unlock(&age_info->aged_sl);
564 mlx5_age_event_prepare(sh);
568 * Handle completions from WQEs sent to ASO SQ.
571 * Shared device context.
574 * Number of CQEs handled.
577 mlx5_aso_completion_handle(struct mlx5_dev_ctx_shared *sh)
579 struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
580 struct mlx5_aso_sq *sq = &mng->aso_sq;
581 struct mlx5_aso_cq *cq = &sq->cq;
582 volatile struct mlx5_cqe *restrict cqe;
583 const unsigned int cq_size = 1 << cq->log_desc_n;
584 const unsigned int mask = cq_size - 1;
586 uint32_t next_idx = cq->cq_ci & mask;
587 const uint16_t max = (uint16_t)(sq->head - sq->tail);
594 next_idx = (cq->cq_ci + 1) & mask;
595 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
596 cqe = &cq->cq_obj.cqes[idx];
597 ret = check_cqe(cqe, cq_size, cq->cq_ci);
599 * Be sure owner read is done before any other cookie field or
603 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
604 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
606 mlx5_aso_cqe_err_handle(sq);
608 i += sq->elts[(sq->tail + i) & mask].burst_size;
613 mlx5_aso_age_action_update(sh, i);
616 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
622 * Periodically read CQEs and send WQEs to ASO SQ.
625 * Shared device context containing the ASO SQ.
628 mlx5_flow_aso_alarm(void *arg)
630 struct mlx5_dev_ctx_shared *sh = arg;
631 struct mlx5_aso_sq *sq = &sh->aso_age_mng->aso_sq;
635 rte_spinlock_lock(&sh->aso_age_mng->resize_sl);
636 n = sh->aso_age_mng->next;
637 rte_spinlock_unlock(&sh->aso_age_mng->resize_sl);
638 mlx5_aso_completion_handle(sh);
640 /* End of loop: wait 1 second. */
644 mlx5_aso_sq_enqueue_burst(sh->aso_age_mng, n);
645 if (rte_eal_alarm_set(us, mlx5_flow_aso_alarm, sh))
646 DRV_LOG(ERR, "Cannot reinitialize aso alarm.");
650 * API to start ASO access using ASO SQ.
653 * Pointer to shared device context.
656 * 0 on success, a negative errno value otherwise and rte_errno is set.
659 mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh)
661 if (rte_eal_alarm_set(US_PER_S, mlx5_flow_aso_alarm, sh)) {
662 DRV_LOG(ERR, "Cannot reinitialize ASO age alarm.");
669 * API to stop ASO access using ASO SQ.
672 * Pointer to shared device context.
675 * 0 on success, a negative errno value otherwise and rte_errno is set.
678 mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh)
682 if (!sh->aso_age_mng->aso_sq.sq_obj.sq)
686 rte_eal_alarm_cancel(mlx5_flow_aso_alarm, sh);
687 if (rte_errno != EINPROGRESS)
695 mlx5_aso_mtr_sq_enqueue_single(struct mlx5_aso_sq *sq,
696 struct mlx5_aso_mtr *aso_mtr)
698 volatile struct mlx5_aso_wqe *wqe = NULL;
699 struct mlx5_flow_meter_info *fm = NULL;
700 struct mlx5_flow_meter_profile *fmp;
701 uint16_t size = 1 << sq->log_desc_n;
702 uint16_t mask = size - 1;
704 uint32_t dseg_idx = 0;
705 struct mlx5_aso_mtr_pool *pool = NULL;
707 rte_spinlock_lock(&sq->sqsl);
708 res = size - (uint16_t)(sq->head - sq->tail);
709 if (unlikely(!res)) {
710 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
711 rte_spinlock_unlock(&sq->sqsl);
714 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
715 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
718 sq->elts[sq->head & mask].mtr = aso_mtr;
719 pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
720 mtrs[aso_mtr->offset]);
721 wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
722 (aso_mtr->offset >> 1));
723 wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
724 (ASO_OPC_MOD_POLICER <<
725 WQE_CSEG_OPC_MOD_OFFSET) |
726 sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
727 /* There are 2 meters in one ASO cache line. */
728 dseg_idx = aso_mtr->offset & 0x1;
729 wqe->aso_cseg.data_mask =
730 RTE_BE64(MLX5_IFC_FLOW_METER_PARAM_MASK << (32 * !dseg_idx));
732 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
733 fm->profile->srtcm_prm.cbs_cir;
734 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir =
735 fm->profile->srtcm_prm.ebs_eir;
737 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
738 RTE_BE32(MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL);
739 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir = 0;
742 if (fmp->profile.packet_mode)
743 wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm =
744 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
745 (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET) |
746 (MLX5_METER_MODE_PKT << ASO_DSEG_MTR_MODE));
748 wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm =
749 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
750 (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET));
751 switch (fmp->profile.alg) {
752 case RTE_MTR_SRTCM_RFC2697:
753 /* Only needed for RFC2697. */
754 if (fm->profile->srtcm_prm.ebs_eir)
755 wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm |=
756 RTE_BE32(1 << ASO_DSEG_BO_OFFSET);
758 case RTE_MTR_TRTCM_RFC2698:
759 wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm |=
760 RTE_BE32(1 << ASO_DSEG_BBOG_OFFSET);
762 case RTE_MTR_TRTCM_RFC4115:
768 * Due to software performance reason, the token fields will not be
769 * set when posting the WQE to ASO SQ. It will be filled by the HW
773 sq->pi += 2;/* Each WQE contains 2 WQEBB's. */
775 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
777 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
779 rte_spinlock_unlock(&sq->sqsl);
784 mlx5_aso_mtrs_status_update(struct mlx5_aso_sq *sq, uint16_t aso_mtrs_nums)
786 uint16_t size = 1 << sq->log_desc_n;
787 uint16_t mask = size - 1;
789 struct mlx5_aso_mtr *aso_mtr = NULL;
790 uint8_t exp_state = ASO_METER_WAIT;
792 for (i = 0; i < aso_mtrs_nums; ++i) {
793 aso_mtr = sq->elts[(sq->tail + i) & mask].mtr;
794 MLX5_ASSERT(aso_mtr);
795 (void)__atomic_compare_exchange_n(&aso_mtr->state,
796 &exp_state, ASO_METER_READY,
797 false, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
802 mlx5_aso_mtr_completion_handle(struct mlx5_aso_sq *sq)
804 struct mlx5_aso_cq *cq = &sq->cq;
805 volatile struct mlx5_cqe *restrict cqe;
806 const unsigned int cq_size = 1 << cq->log_desc_n;
807 const unsigned int mask = cq_size - 1;
809 uint32_t next_idx = cq->cq_ci & mask;
814 rte_spinlock_lock(&sq->sqsl);
815 max = (uint16_t)(sq->head - sq->tail);
816 if (unlikely(!max)) {
817 rte_spinlock_unlock(&sq->sqsl);
822 next_idx = (cq->cq_ci + 1) & mask;
823 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
824 cqe = &cq->cq_obj.cqes[idx];
825 ret = check_cqe(cqe, cq_size, cq->cq_ci);
827 * Be sure owner read is done before any other cookie field or
831 if (ret != MLX5_CQE_STATUS_SW_OWN) {
832 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
834 mlx5_aso_cqe_err_handle(sq);
841 mlx5_aso_mtrs_status_update(sq, n);
844 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
846 rte_spinlock_unlock(&sq->sqsl);
850 * Update meter parameter by send WQE.
853 * Pointer to Ethernet device.
855 * Pointer to mlx5 private data structure.
857 * Pointer to flow meter to be modified.
860 * 0 on success, a negative errno value otherwise and rte_errno is set.
863 mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
864 struct mlx5_aso_mtr *mtr)
866 struct mlx5_aso_sq *sq = &sh->mtrmng->pools_mng.sq;
867 uint32_t poll_wqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
870 mlx5_aso_mtr_completion_handle(sq);
871 if (mlx5_aso_mtr_sq_enqueue_single(sq, mtr))
873 /* Waiting for wqe resource. */
874 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
875 } while (--poll_wqe_times);
876 DRV_LOG(ERR, "Fail to send WQE for ASO meter offset %d",
882 * Wait for meter to be ready.
885 * Pointer to Ethernet device.
887 * Pointer to mlx5 private data structure.
889 * Pointer to flow meter to be modified.
892 * 0 on success, a negative errno value otherwise and rte_errno is set.
895 mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
896 struct mlx5_aso_mtr *mtr)
898 struct mlx5_aso_sq *sq = &sh->mtrmng->pools_mng.sq;
899 uint32_t poll_cqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
901 if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
905 mlx5_aso_mtr_completion_handle(sq);
906 if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
909 /* Waiting for CQE ready. */
910 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
911 } while (--poll_cqe_times);
912 DRV_LOG(ERR, "Fail to poll CQE ready for ASO meter offset %d",
918 * Post a WQE to the ASO CT SQ to modify the context.
921 * Pointer to the CT pools management structure.
923 * Pointer to the generic CT structure related to the context.
925 * Pointer to configuration profile.
928 * 1 on success (WQE number), 0 on failure.
931 mlx5_aso_ct_sq_enqueue_single(struct mlx5_aso_ct_pools_mng *mng,
932 struct mlx5_aso_ct_action *ct,
933 const struct rte_flow_action_conntrack *profile)
935 volatile struct mlx5_aso_wqe *wqe = NULL;
936 struct mlx5_aso_sq *sq = &mng->aso_sq;
937 uint16_t size = 1 << sq->log_desc_n;
938 uint16_t mask = size - 1;
940 struct mlx5_aso_ct_pool *pool;
945 rte_spinlock_lock(&sq->sqsl);
946 /* Prevent other threads to update the index. */
947 res = size - (uint16_t)(sq->head - sq->tail);
948 if (unlikely(!res)) {
949 rte_spinlock_unlock(&sq->sqsl);
950 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
953 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
954 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
956 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_WAIT);
957 sq->elts[sq->head & mask].ct = ct;
958 sq->elts[sq->head & mask].query_data = NULL;
959 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
960 /* Each WQE will have a single CT object. */
961 wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
963 wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
964 (ASO_OPC_MOD_CONNECTION_TRACKING <<
965 WQE_CSEG_OPC_MOD_OFFSET) |
966 sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
967 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
969 (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
970 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
971 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
972 (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
973 wqe->aso_cseg.data_mask = UINT64_MAX;
974 /* To make compiler happy. */
975 desg = (void *)(uintptr_t)wqe->aso_dseg.data;
976 MLX5_SET(conn_track_aso, desg, valid, 1);
977 MLX5_SET(conn_track_aso, desg, state, profile->state);
978 MLX5_SET(conn_track_aso, desg, freeze_track, !profile->enable);
979 MLX5_SET(conn_track_aso, desg, connection_assured,
980 profile->live_connection);
981 MLX5_SET(conn_track_aso, desg, sack_permitted, profile->selective_ack);
982 MLX5_SET(conn_track_aso, desg, challenged_acked,
983 profile->challenge_ack_passed);
984 /* Heartbeat, retransmission_counter, retranmission_limit_exceeded: 0 */
985 MLX5_SET(conn_track_aso, desg, heartbeat, 0);
986 MLX5_SET(conn_track_aso, desg, max_ack_window,
987 profile->max_ack_window);
988 MLX5_SET(conn_track_aso, desg, retransmission_counter, 0);
989 MLX5_SET(conn_track_aso, desg, retranmission_limit_exceeded, 0);
990 MLX5_SET(conn_track_aso, desg, retranmission_limit,
991 profile->retransmission_limit);
992 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_scale,
993 profile->reply_dir.scale);
994 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_close_initiated,
995 profile->reply_dir.close_initiated);
996 /* Both directions will use the same liberal mode. */
997 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_liberal_enabled,
998 profile->liberal_mode);
999 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_data_unacked,
1000 profile->reply_dir.data_unacked);
1001 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_max_ack,
1002 profile->reply_dir.last_ack_seen);
1003 MLX5_SET(conn_track_aso, desg, original_direction_tcp_scale,
1004 profile->original_dir.scale);
1005 MLX5_SET(conn_track_aso, desg, original_direction_tcp_close_initiated,
1006 profile->original_dir.close_initiated);
1007 MLX5_SET(conn_track_aso, desg, original_direction_tcp_liberal_enabled,
1008 profile->liberal_mode);
1009 MLX5_SET(conn_track_aso, desg, original_direction_tcp_data_unacked,
1010 profile->original_dir.data_unacked);
1011 MLX5_SET(conn_track_aso, desg, original_direction_tcp_max_ack,
1012 profile->original_dir.last_ack_seen);
1013 MLX5_SET(conn_track_aso, desg, last_win, profile->last_window);
1014 MLX5_SET(conn_track_aso, desg, last_dir, profile->last_direction);
1015 MLX5_SET(conn_track_aso, desg, last_index, profile->last_index);
1016 MLX5_SET(conn_track_aso, desg, last_seq, profile->last_seq);
1017 MLX5_SET(conn_track_aso, desg, last_ack, profile->last_ack);
1018 MLX5_SET(conn_track_aso, desg, last_end, profile->last_end);
1019 orig_dir = MLX5_ADDR_OF(conn_track_aso, desg, original_dir);
1020 MLX5_SET(tcp_window_params, orig_dir, sent_end,
1021 profile->original_dir.sent_end);
1022 MLX5_SET(tcp_window_params, orig_dir, reply_end,
1023 profile->original_dir.reply_end);
1024 MLX5_SET(tcp_window_params, orig_dir, max_win,
1025 profile->original_dir.max_win);
1026 MLX5_SET(tcp_window_params, orig_dir, max_ack,
1027 profile->original_dir.max_ack);
1028 reply_dir = MLX5_ADDR_OF(conn_track_aso, desg, reply_dir);
1029 MLX5_SET(tcp_window_params, reply_dir, sent_end,
1030 profile->reply_dir.sent_end);
1031 MLX5_SET(tcp_window_params, reply_dir, reply_end,
1032 profile->reply_dir.reply_end);
1033 MLX5_SET(tcp_window_params, reply_dir, max_win,
1034 profile->reply_dir.max_win);
1035 MLX5_SET(tcp_window_params, reply_dir, max_ack,
1036 profile->reply_dir.max_ack);
1038 sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
1040 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
1042 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
1044 rte_spinlock_unlock(&sq->sqsl);
1049 * Update the status field of CTs to indicate ready to be used by flows.
1050 * A continuous number of CTs since last update.
1053 * Pointer to ASO CT SQ.
1055 * Number of CT structures to be updated.
1058 * 0 on success, a negative value.
1061 mlx5_aso_ct_status_update(struct mlx5_aso_sq *sq, uint16_t num)
1063 uint16_t size = 1 << sq->log_desc_n;
1064 uint16_t mask = size - 1;
1066 struct mlx5_aso_ct_action *ct = NULL;
1069 for (i = 0; i < num; i++) {
1070 idx = (uint16_t)((sq->tail + i) & mask);
1071 ct = sq->elts[idx].ct;
1073 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_READY);
1074 if (sq->elts[idx].query_data)
1075 rte_memcpy(sq->elts[idx].query_data,
1076 (char *)((uintptr_t)sq->mr.addr + idx * 64),
1082 * Post a WQE to the ASO CT SQ to query the current context.
1085 * Pointer to the CT pools management structure.
1087 * Pointer to the generic CT structure related to the context.
1089 * Pointer to data area to be filled.
1092 * 1 on success (WQE number), 0 on failure.
1095 mlx5_aso_ct_sq_query_single(struct mlx5_aso_ct_pools_mng *mng,
1096 struct mlx5_aso_ct_action *ct, char *data)
1098 volatile struct mlx5_aso_wqe *wqe = NULL;
1099 struct mlx5_aso_sq *sq = &mng->aso_sq;
1100 uint16_t size = 1 << sq->log_desc_n;
1101 uint16_t mask = size - 1;
1104 struct mlx5_aso_ct_pool *pool;
1105 enum mlx5_aso_ct_state state =
1106 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
1108 if (state == ASO_CONNTRACK_FREE) {
1109 DRV_LOG(ERR, "Fail: No context to query");
1111 } else if (state == ASO_CONNTRACK_WAIT) {
1114 rte_spinlock_lock(&sq->sqsl);
1115 res = size - (uint16_t)(sq->head - sq->tail);
1116 if (unlikely(!res)) {
1117 rte_spinlock_unlock(&sq->sqsl);
1118 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
1121 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_QUERY);
1122 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
1123 /* Confirm the location and address of the prefetch instruction. */
1124 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
1125 /* Fill next WQE. */
1126 wqe_idx = sq->head & mask;
1127 sq->elts[wqe_idx].ct = ct;
1128 sq->elts[wqe_idx].query_data = data;
1129 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
1130 /* Each WQE will have a single CT object. */
1131 wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
1133 wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
1134 (ASO_OPC_MOD_CONNECTION_TRACKING <<
1135 WQE_CSEG_OPC_MOD_OFFSET) |
1136 sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
1138 * There is no write request is required.
1139 * ASO_OPER_LOGICAL_AND and ASO_OP_ALWAYS_FALSE are both 0.
1140 * "BYTEWISE_64BYTE" is needed for a whole context.
1141 * Set to 0 directly to reduce an endian swap. (Modify should rewrite.)
1142 * "data_mask" is ignored.
1143 * Buffer address was already filled during initialization.
1145 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32(BYTEWISE_64BYTE <<
1146 ASO_CSEG_DATA_MASK_MODE_OFFSET);
1147 wqe->aso_cseg.data_mask = 0;
1150 * Each WQE contains 2 WQEBB's, even though
1151 * data segment is not used in this case.
1155 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
1157 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
1159 rte_spinlock_unlock(&sq->sqsl);
1164 * Handle completions from WQEs sent to ASO CT.
1167 * Pointer to the CT pools management structure.
1170 mlx5_aso_ct_completion_handle(struct mlx5_aso_ct_pools_mng *mng)
1172 struct mlx5_aso_sq *sq = &mng->aso_sq;
1173 struct mlx5_aso_cq *cq = &sq->cq;
1174 volatile struct mlx5_cqe *restrict cqe;
1175 const uint32_t cq_size = 1 << cq->log_desc_n;
1176 const uint32_t mask = cq_size - 1;
1183 rte_spinlock_lock(&sq->sqsl);
1184 max = (uint16_t)(sq->head - sq->tail);
1185 if (unlikely(!max)) {
1186 rte_spinlock_unlock(&sq->sqsl);
1189 next_idx = cq->cq_ci & mask;
1192 next_idx = (cq->cq_ci + 1) & mask;
1193 /* Need to confirm the position of the prefetch. */
1194 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
1195 cqe = &cq->cq_obj.cqes[idx];
1196 ret = check_cqe(cqe, cq_size, cq->cq_ci);
1198 * Be sure owner read is done before any other cookie field or
1202 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1203 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
1205 mlx5_aso_cqe_err_handle(sq);
1212 mlx5_aso_ct_status_update(sq, n);
1215 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
1217 rte_spinlock_unlock(&sq->sqsl);
1221 * Update connection tracking ASO context by sending WQE.
1224 * Pointer to mlx5_dev_ctx_shared object.
1226 * Pointer to connection tracking offload object.
1227 * @param[in] profile
1228 * Pointer to connection tracking TCP parameter.
1231 * 0 on success, -1 on failure.
1234 mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1235 struct mlx5_aso_ct_action *ct,
1236 const struct rte_flow_action_conntrack *profile)
1238 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
1239 uint32_t poll_wqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;
1240 struct mlx5_aso_ct_pool *pool;
1244 mlx5_aso_ct_completion_handle(mng);
1245 if (mlx5_aso_ct_sq_enqueue_single(mng, ct, profile))
1247 /* Waiting for wqe resource. */
1248 rte_delay_us_sleep(10u);
1249 } while (--poll_wqe_times);
1250 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
1251 DRV_LOG(ERR, "Fail to send WQE for ASO CT %d in pool %d",
1252 ct->offset, pool->index);
1257 * The routine is used to wait for WQE completion to continue with queried data.
1260 * Pointer to mlx5_dev_ctx_shared object.
1262 * Pointer to connection tracking offload object.
1265 * 0 on success, -1 on failure.
1268 mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh,
1269 struct mlx5_aso_ct_action *ct)
1271 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
1272 uint32_t poll_cqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;
1273 struct mlx5_aso_ct_pool *pool;
1275 if (__atomic_load_n(&ct->state, __ATOMIC_RELAXED) ==
1276 ASO_CONNTRACK_READY)
1279 mlx5_aso_ct_completion_handle(mng);
1280 if (__atomic_load_n(&ct->state, __ATOMIC_RELAXED) ==
1281 ASO_CONNTRACK_READY)
1283 /* Waiting for CQE ready, consider should block or sleep. */
1284 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
1285 } while (--poll_cqe_times);
1286 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
1287 DRV_LOG(ERR, "Fail to poll CQE for ASO CT %d in pool %d",
1288 ct->offset, pool->index);
1293 * Convert the hardware conntrack data format into the profile.
1295 * @param[in] profile
1296 * Pointer to conntrack profile to be filled after query.
1298 * Pointer to data fetched from hardware.
1301 mlx5_aso_ct_obj_analyze(struct rte_flow_action_conntrack *profile,
1304 void *o_dir = MLX5_ADDR_OF(conn_track_aso, wdata, original_dir);
1305 void *r_dir = MLX5_ADDR_OF(conn_track_aso, wdata, reply_dir);
1307 /* MLX5_GET16 should be taken into consideration. */
1308 profile->state = (enum rte_flow_conntrack_state)
1309 MLX5_GET(conn_track_aso, wdata, state);
1310 profile->enable = !MLX5_GET(conn_track_aso, wdata, freeze_track);
1311 profile->selective_ack = MLX5_GET(conn_track_aso, wdata,
1313 profile->live_connection = MLX5_GET(conn_track_aso, wdata,
1314 connection_assured);
1315 profile->challenge_ack_passed = MLX5_GET(conn_track_aso, wdata,
1317 profile->max_ack_window = MLX5_GET(conn_track_aso, wdata,
1319 profile->retransmission_limit = MLX5_GET(conn_track_aso, wdata,
1320 retranmission_limit);
1321 profile->last_window = MLX5_GET(conn_track_aso, wdata, last_win);
1322 profile->last_direction = MLX5_GET(conn_track_aso, wdata, last_dir);
1323 profile->last_index = (enum rte_flow_conntrack_tcp_last_index)
1324 MLX5_GET(conn_track_aso, wdata, last_index);
1325 profile->last_seq = MLX5_GET(conn_track_aso, wdata, last_seq);
1326 profile->last_ack = MLX5_GET(conn_track_aso, wdata, last_ack);
1327 profile->last_end = MLX5_GET(conn_track_aso, wdata, last_end);
1328 profile->liberal_mode = MLX5_GET(conn_track_aso, wdata,
1329 reply_direction_tcp_liberal_enabled) |
1330 MLX5_GET(conn_track_aso, wdata,
1331 original_direction_tcp_liberal_enabled);
1332 /* No liberal in the RTE structure profile. */
1333 profile->reply_dir.scale = MLX5_GET(conn_track_aso, wdata,
1334 reply_direction_tcp_scale);
1335 profile->reply_dir.close_initiated = MLX5_GET(conn_track_aso, wdata,
1336 reply_direction_tcp_close_initiated);
1337 profile->reply_dir.data_unacked = MLX5_GET(conn_track_aso, wdata,
1338 reply_direction_tcp_data_unacked);
1339 profile->reply_dir.last_ack_seen = MLX5_GET(conn_track_aso, wdata,
1340 reply_direction_tcp_max_ack);
1341 profile->reply_dir.sent_end = MLX5_GET(tcp_window_params,
1343 profile->reply_dir.reply_end = MLX5_GET(tcp_window_params,
1345 profile->reply_dir.max_win = MLX5_GET(tcp_window_params,
1347 profile->reply_dir.max_ack = MLX5_GET(tcp_window_params,
1349 profile->original_dir.scale = MLX5_GET(conn_track_aso, wdata,
1350 original_direction_tcp_scale);
1351 profile->original_dir.close_initiated = MLX5_GET(conn_track_aso, wdata,
1352 original_direction_tcp_close_initiated);
1353 profile->original_dir.data_unacked = MLX5_GET(conn_track_aso, wdata,
1354 original_direction_tcp_data_unacked);
1355 profile->original_dir.last_ack_seen = MLX5_GET(conn_track_aso, wdata,
1356 original_direction_tcp_max_ack);
1357 profile->original_dir.sent_end = MLX5_GET(tcp_window_params,
1359 profile->original_dir.reply_end = MLX5_GET(tcp_window_params,
1361 profile->original_dir.max_win = MLX5_GET(tcp_window_params,
1363 profile->original_dir.max_ack = MLX5_GET(tcp_window_params,
1368 * Query connection tracking information parameter by send WQE.
1371 * Pointer to Ethernet device.
1373 * Pointer to connection tracking offload object.
1374 * @param[out] profile
1375 * Pointer to connection tracking TCP information.
1378 * 0 on success, -1 on failure.
1381 mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,
1382 struct mlx5_aso_ct_action *ct,
1383 struct rte_flow_action_conntrack *profile)
1385 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
1386 uint32_t poll_wqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;
1387 struct mlx5_aso_ct_pool *pool;
1388 char out_data[64 * 2];
1393 mlx5_aso_ct_completion_handle(mng);
1394 ret = mlx5_aso_ct_sq_query_single(mng, ct, out_data);
1399 /* Waiting for wqe resource or state. */
1401 rte_delay_us_sleep(10u);
1402 } while (--poll_wqe_times);
1403 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
1404 DRV_LOG(ERR, "Fail to send WQE for ASO CT %d in pool %d",
1405 ct->offset, pool->index);
1408 ret = mlx5_aso_ct_wait_ready(sh, ct);
1410 mlx5_aso_ct_obj_analyze(profile, out_data);
1415 * Make sure the conntrack context is synchronized with hardware before
1416 * creating a flow rule that uses it.
1419 * Pointer to shared device context.
1421 * Pointer to connection tracking offload object.
1424 * 0 on success, a negative errno value otherwise and rte_errno is set.
1427 mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
1428 struct mlx5_aso_ct_action *ct)
1430 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
1431 uint32_t poll_cqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;
1432 enum mlx5_aso_ct_state state =
1433 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
1435 if (state == ASO_CONNTRACK_FREE) {
1438 } else if (state == ASO_CONNTRACK_READY ||
1439 state == ASO_CONNTRACK_QUERY) {
1443 mlx5_aso_ct_completion_handle(mng);
1444 state = __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
1445 if (state == ASO_CONNTRACK_READY ||
1446 state == ASO_CONNTRACK_QUERY)
1448 /* Waiting for CQE ready, consider should block or sleep. */
1449 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
1450 } while (--poll_cqe_times);